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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_rcvr_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
rcvr_lint
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 
 
 
 

 
       
 
 
              
              Dut
              
              
                                   spirit:library="cde"
                                   spirit:name="serial"
                                   spirit:version="rcvr_dut.params"/>
              
              
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 
 

 
 
 
 
 
 
 

 
 
 
   
      fs-lint
      
        
        ../verilog/lint/serial_rcvr_lint
        verilogSource
        module
      
 
 
 
   
 
 
 
 

 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`rcvr_lint`
16
17	133	jt_eaton
18	131	jt_eaton
19	133	jt_eaton
20			`elab_verilog`
21			`103.0`
22			`none`
23			`:Simulation:`
24			`>`
25			`./tools/verilog/elab_verilog`
26
27
28			`configuration`
29			`default`
30
31
32			`dest_dir`
33			`io_ports`
34
35
36
37	131	jt_eaton
38	133	jt_eaton
39			`gen_design`
40			`103.0`
41			`none`
42			`:Simulation:`
43			`>`
44			`./tools/verilog/gen_design`
45
46
47			`dest_dir`
48			`io_ports`
49
50
51
52	131	jt_eaton
53	133	jt_eaton
54	131	jt_eaton
55
56
57	133	jt_eaton
58
59
60
61	131	jt_eaton
62
63
64
65
66
67			`Dut`
68
69
70			`spirit:library="cde"`
71			`spirit:name="serial"`
72			`spirit:version="rcvr_dut.params"/>`
73
74
75
76
77			`lint`
78			`:Lint:`
79			`Verilog`
80			`fs-lint`
81
82
83
84
85
86			`rtl_check`
87
88
89			`spirit:library="Testbench"`
90			`spirit:name="toolflow"`
91			`spirit:version="rtl_check"/>`
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
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111
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113			`fs-lint`
114
115
116			`../verilog/lint/serial_rcvr_lint`
117			`verilogSource`
118			`module`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_rcvr_lint.xml] - Blame information for rev 133