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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
cde
sram
 
 
3
_
_
_
VARIANT
 
 
 

 
/ip/sram/doc
sram/doc
 
 
 

 
  
   def
   Synchronous one-port ram
  
 
  
   dp
   Synchronous two-port ram with seperate read/write ports
  
 
  
   byte
   Synchronous one-port byte wide ram with byte enable
  
 
 
  
   word
   Synchronous one-port word wide ram with byte enable
  
 
 
 
 

 
 

 
  
   ADDR
   Number of address bits
  
 
  
   WIDTH
   Number of data bits
  
 
  
   WORDS
   Number of memory words. Must be fully addressable by ADDR address bits
  
 
  
   WRITETHRU
   If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new
  
 
 
 

 
 
 

 
  
   addr
   Memory address bits
  
 
  
   raddr
   Memory read address bits
  
 
  
   waddr
   Memory write address bits
  
 
  
   clk
   Active high clock
  
 
  
   cs
   Active high chip select
  
 
  
   rd
   Active high read enable
  
 
  
   wr
   Active high write enable
  
 
 
  
   be
   Active high byte enable
  
 
  
   rdata
   read data out
  
 
  
   wdata
   write data in
  
 
 

 
 
 
 
 
 
 
 

 
 

 
 
 
 
 default
 def
 dp
 
    ADDR8
    WORDS256
    WIDTH8
    WRITETHRU1
 
 
 
 
 
 
 
 
 byte
 byte
 
    ADDR8
    WORDS256
    WRITETHRU1
 

 
 
 
 
 word
 word
 
    ADDR8
    WORDS256
    WRITETHRU1
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 

 
sram/sim
 
 
 
 
 
 

 
 

sram_sys_lint
sys_lint

  rtl_check


 

 
 
 

 

default
sram_sys_lint

 

 
 

 
 
 
 
 

 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
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6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`cde`
12			`sram`
13
14
15			`3`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
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25			`/ip/sram/doc`
26			`sram/doc`
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33			`def`
34			`Synchronous one-port ram`
35
36
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38			`dp`
39			`Synchronous two-port ram with seperate read/write ports`
40
41
42
43	134	jt_eaton	`byte`
44			`Synchronous one-port byte wide ram with byte enable`
45	131	jt_eaton
46
47
48	134	jt_eaton
49			`word`
50			`Synchronous one-port word wide ram with byte enable`
51
52	131	jt_eaton
53	134	jt_eaton
54
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56	131	jt_eaton
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62			`ADDR`
63			`Number of address bits`
64
65
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67			`WIDTH`
68			`Number of data bits`
69
70
71
72			`WORDS`
73			`Number of memory words. Must be fully addressable by ADDR address bits`
74
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77			`WRITETHRU`
78			`If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new`
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90			`addr`
91			`Memory address bits`
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95			`raddr`
96			`Memory read address bits`
97
98
99
100			`waddr`
101			`Memory write address bits`
102
103
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105			`clk`
106			`Active high clock`
107
108
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110			`cs`
111			`Active high chip select`
112
113
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115			`rd`
116			`Active high read enable`
117
118
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120			`wr`
121			`Active high write enable`
122
123
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126			`be`
127			`Active high byte enable`
128
129
130
131			`rdata`
132			`read data out`
133
134
135
136			`wdata`
137			`write data in`
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153	134	jt_eaton
154	131	jt_eaton
155
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157	134	jt_eaton
158			`default`
159			`def`
160			`dp`
161
162			`ADDR8`
163			`WORDS256`
164			`WIDTH8`
165			`WRITETHRU1`
166
167
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174			`byte`
175			`byte`
176
177			`ADDR8`
178			`WORDS256`
179			`WRITETHRU1`
180
181
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186			`word`
187			`word`
188
189			`ADDR8`
190			`WORDS256`
191			`WRITETHRU1`
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206	135	jt_eaton
207
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211			`sram/sim`
212
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222			`sram_sys_lint`
223			`sys_lint`
224
225			`rtl_check`
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236			`default`
237			`sram_sys_lint`
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249	131	jt_eaton
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