OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [doc/] [sch/] [cde_sram_dp.sch] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
v 20100214 1
2
C 1800 300 1 0 0 in_port_vector.sym
3
{
4
T 1800 300 5 10 1 1 0 6 1 1
5
refdes=wdata[WIDTH-1:0]
6
}
7
C 1800 700 1 0 0 in_port_vector.sym
8
{
9
T 1800 700 5 10 1 1 0 6 1 1
10
refdes=waddr[ADDR-1:0]
11
}
12
C 1800 1100 1 0 0 in_port_vector.sym
13
{
14
T 1800 1100 5 10 1 1 0 6 1 1
15
refdes=raddr[ADDR-1:0]
16
}
17
C 1800 1500 1 0 0 in_port.sym
18
{
19
T 1800 1500 5 10 1 1 0 6 1 1
20
refdes=wr
21
}
22
C 1800 1900 1 0 0 in_port.sym
23
{
24
T 1800 1900 5 10 1 1 0 6 1 1
25
refdes=rd
26
}
27
C 1800 2300 1 0 0 in_port.sym
28
{
29
T 1800 2300 5 10 1 1 0 6 1 1
30
refdes=cs
31
}
32
C 1800 2700 1 0 0 in_port.sym
33
{
34
T 1800 2700 5 10 1 1 0 6 1 1
35
refdes=clk
36
}
37
C 4700 300  1 0  0 out_port_vector.sym
38
{
39
T 5700 300 5  10 1 1 0 0 1 1
40
refdes=rdata[WIDTH-1:0]
41
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.