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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_byte.v] - Blame information for rev 133

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 module
  cde_sram_byte
    #( parameter
      ADDR=10,
      WORDS=1024,
      WRITETHRU=0,
      DEFAULT={WIDTH{1'b1}}
      )
     (
 input wire               be,
 input wire               clk,
 input wire               cs,
 input wire               be,
 input wire               rd,
 input wire               wr,
 input wire [ ADDR-1 : 0] addr,
 input wire [ 7 : 0]       wdata,
 output reg [ 7 : 0]       rdata);
  // Simple loop back for linting and code coverage
  always@(posedge clk)
        if( rd && cs ) rdata             <= wdata;
        else           rdata             <= DEFAULT;
  endmodule

Line No.	Rev	Author	Line
1	133	jt_eaton	`module`
2			`cde_sram_byte`
3			`#( parameter`
4			`ADDR=10,`
5			`WORDS=1024,`
6			`WRITETHRU=0,`
7			`DEFAULT={WIDTH{1'b1}}`
8			`)`
9			`(`
10			`input wire be,`
11			`input wire clk,`
12			`input wire cs,`
13			`input wire be,`
14			`input wire rd,`
15			`input wire wr,`
16			`input wire [ ADDR-1 : 0] addr,`
17			`input wire [ 7 : 0] wdata,`
18			`output reg [ 7 : 0] rdata);`
19			`// Simple loop back for linting and code coverage`
20			`always@(posedge clk)`
21			`if( rd && cs ) rdata <= wdata;`
22			`else rdata <= DEFAULT;`
23			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_byte.v] - Blame information for rev 133