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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_def.v] - Blame information for rev 134

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 module
  cde_sram_def
    #( parameter
      ADDR=10,
      WIDTH=8,
      WORDS=1024,
      WRITETHRU=0
     )
     (
 input   wire                 clk,
 input   wire                 cs,
 input   wire                 rd,
 input   wire                 wr,
 input   wire    [ ADDR-1 :  0]        addr,
 input   wire    [ WIDTH-1 :  0]        wdata,
 output   reg    [ WIDTH-1 :  0]        rdata);
  // Simple loop back for linting and code coverage
  always@(posedge clk)
        if( rd && cs ) rdata             <= wdata;
        else           rdata             <= {WIDTH{1'b1}};
  endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`module`
2			`cde_sram_def`
3			`#( parameter`
4			`ADDR=10,`
5			`WIDTH=8,`
6			`WORDS=1024,`
7	134	jt_eaton	`WRITETHRU=0`
8			`)`
9	131	jt_eaton	`(`
10			`input wire clk,`
11			`input wire cs,`
12			`input wire rd,`
13			`input wire wr,`
14			`input wire [ ADDR-1 : 0] addr,`
15			`input wire [ WIDTH-1 : 0] wdata,`
16			`output reg [ WIDTH-1 : 0] rdata);`
17			`// Simple loop back for linting and code coverage`
18			`always@(posedge clk)`
19			`if( rd && cs ) rdata <= wdata;`
20	134	jt_eaton	`else rdata <= {WIDTH{1'b1}};`
21	131	jt_eaton	`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_def.v] - Blame information for rev 134