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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_word.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 module
  cde_sram_word
    #( parameter
      ADDR=10,
      WORDS=1024,
      WRITETHRU=0,
      DEFAULT={16'hffff},
      INIT_FILE="NONE")
     (
 input wire               clk,
 input wire               cs,
 input wire               rd,
 input wire               wr,
 input wire [ ADDR-1 : 0] addr,
 input wire [ 15 : 0]      wdata,
 input wire [  1 : 0]     be,
 output reg [ 15 : 0]      rdata);
 
  always@(posedge clk)
        if( rd && cs ) rdata             <= wdata  ;
        else           rdata             <= DEFAULT;
 
 
  endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21			`module`
22			`cde_sram_word`
23			`#( parameter`
24			`ADDR=10,`
25			`WORDS=1024,`
26			`WRITETHRU=0,`
27			`DEFAULT={16'hffff},`
28			`INIT_FILE="NONE")`
29			`(`
30			`input wire clk,`
31			`input wire cs,`
32			`input wire rd,`
33			`input wire wr,`
34			`input wire [ ADDR-1 : 0] addr,`
35			`input wire [ 15 : 0] wdata,`
36			`input wire [ 1 : 0] be,`
37			`output reg [ 15 : 0] rdata);`
38
39			`always@(posedge clk)`
40			`if( rd && cs ) rdata <= wdata ;`
41			`else rdata <= DEFAULT;`
42
43
44			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_word.v] - Blame information for rev 131