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// Memory Array

reg [7:0] mem [0:WORDS-1];

initial

  begin

  $display("SRAM byte %m.mem");

  $display("  AddrBits=%d DataBits = 8  Words = %d  ",ADDR,WORDS);

  end

// Write function

always@(posedge clk)

        if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0];

generate

if( WRITETHRU)

  begin

  // Read function gets new data if also a write cycle

  // latch the read addr for next cycle

  reg   [ADDR-1:0]          l_raddr;

  reg                       l_cycle;

  always@(posedge clk)

    begin

       l_raddr    <=  addr;

       l_cycle    <=  rd && cs ;

    end

  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block

  wire  [7:0] tmp_rdata;

  assign         tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff;

  always@(*)         rdata  =      tmp_rdata;

  end

else

  begin

  // Read function gets old data if also a write cycle

  always@(posedge clk)

        if( rd && cs ) rdata             <= mem[{addr[ADDR-1:0]}];

        else           rdata             <= 8'hff;

  end

endgenerate