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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_byte.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
byte  default
 
 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
 
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
              
 
 
 
 
      
 
 
 

ADDR0
WORDS0
WRITETHRU0
DEFAULT{8'bxxxxxxxx}

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
be
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
70

 
rdata
reg
out
70

 
 
 

 

 
 
 
 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
 
      
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	133	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`byte default`
16
17
18
19
20
21
22
23
24
25
26
27
28
29			`sim:Simulation:`
30
31			`Verilog`
32
33
34			`fs-sim`
35
36
37
38
39			`syn:Synthesis:`
40
41			`Verilog`
42
43
44			`fs-syn`
45
46
47
48
49
50			`lintlint`
51
52			`Verilog`
53
54
55			`fs-lint`
56
57
58
59
60
61
62
63			`doc`
64
65
66			`spirit:library="Testbench"`
67			`spirit:name="toolflow"`
68			`spirit:version="documentation"/>`
69
70			`:Documentation:`
71			`Verilog`
72
73
74
75
76
77
78
79
80
81
82
83			`ADDR0`
84			`WORDS0`
85			`WRITETHRU0`
86			`DEFAULT{8'bxxxxxxxx}`
87
88
89
90
91			`clk`
92			`wire`
93			`in`
94
95
96			`cs`
97			`wire`
98			`in`
99
100
101			`wr`
102			`wire`
103			`in`
104
105
106			`rd`
107			`wire`
108			`in`
109
110
111			`be`
112			`wire`
113			`in`
114
115
116
117			`addr`
118			`wire`
119			`in`
120			`ADDR-10`
121
122
123
124			`wdata`
125			`wire`
126			`in`
127			`70`
128
129
130			`rdata`
131			`reg`
132			`out`
133			`70`
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152			`fs-sim`
153
154
155			`dest_dir../verilog/`
156			`verilogSourcelibraryDir`
157
158
159
160
161
162
163			`fs-syn`
164
165
166			`dest_dir../verilog/`
167			`verilogSourcelibraryDir`
168
169
170
171
172
173
174
175
176			`fs-lint`
177
178
179
180			`dest_dir../verilog/lint/`
181			`verilogSourcelibraryDir`
182
183
184
185
186
187
188
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_byte.xml] - Blame information for rev 133