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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_byte.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
byte  default
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sram_byte
    
  

 
 
 
 
 
 

 
 
 
 
 
 

       
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
             
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
 
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
              
 
 
 
 
      
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
be
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
70

 
rdata
reg
out
70

 
 
 

 

 
 
 
 
 
 

 
   
      fs-common
 
 
 
 
      
        
        ../verilog/sram_byte
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
    
        
        ../verilog/common/sram_byte
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
    
        
        ../verilog/common/sram_byte
        verilogSourcemodule
      
 
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_byte.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	133	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`byte default`
16
17
18
19	134	jt_eaton
20	133	jt_eaton
21
22
23	134	jt_eaton
24			`gen_verilog`
25			`104.0`
26			`none`
27			`common`
28			`./tools/verilog/gen_verilog`
29
30
31			`destination`
32			`sram_byte`
33
34
35
36	133	jt_eaton
37
38	134	jt_eaton
39
40
41
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43
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49	133	jt_eaton
50
51
52	134	jt_eaton
53			`verilog`
54
55
56			`spirit:library="Testbench"`
57			`spirit:name="toolflow"`
58			`spirit:version="verilog"/>`
59
60
61	133	jt_eaton
62	134	jt_eaton
63			`commoncommon`
64			`Verilog`
65
66
67			`fs-common`
68
69
70
71
72
73	133	jt_eaton
74			`sim:Simulation:`
75
76			`Verilog`
77
78
79			`fs-sim`
80
81
82
83
84			`syn:Synthesis:`
85
86			`Verilog`
87
88
89			`fs-syn`
90
91
92
93
94
95			`lintlint`
96
97			`Verilog`
98
99
100			`fs-lint`
101
102
103
104
105
106
107
108			`doc`
109
110
111			`spirit:library="Testbench"`
112			`spirit:name="toolflow"`
113			`spirit:version="documentation"/>`
114
115			`:Documentation:`
116			`Verilog`
117
118
119
120
121
122
123
124
125
126
127
128			`clk`
129			`wire`
130			`in`
131
132
133			`cs`
134			`wire`
135			`in`
136
137
138			`wr`
139			`wire`
140			`in`
141
142
143			`rd`
144			`wire`
145			`in`
146
147
148			`be`
149			`wire`
150			`in`
151
152
153
154			`addr`
155			`wire`
156			`in`
157			`ADDR-10`
158
159
160
161			`wdata`
162			`wire`
163			`in`
164			`70`
165
166
167			`rdata`
168			`reg`
169			`out`
170			`70`
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186	134	jt_eaton
187			`fs-common`
188	133	jt_eaton
189
190	134	jt_eaton
191
192
193
194			`../verilog/sram_byte`
195			`verilogSourcefragment`
196
197
198
199
200
201	133	jt_eaton
202			`fs-sim`
203
204	134	jt_eaton
205
206			`../verilog/copyright`
207			`verilogSourceinclude`
208
209
210
211
212			`../verilog/common/sram_byte`
213			`verilogSourcemodule`
214
215
216
217
218	133	jt_eaton
219	134	jt_eaton	`dest_dir../views/sim/`
220	133	jt_eaton	`verilogSourcelibraryDir`
221
222
223
224
225
226
227			`fs-syn`
228
229	134	jt_eaton
230	133	jt_eaton
231	134	jt_eaton
232			`../verilog/copyright`
233			`verilogSourceinclude`
234
235
236
237
238			`../verilog/common/sram_byte`
239			`verilogSourcemodule`
240
241
242
243
244
245
246
247			`dest_dir../views/syn/`
248	133	jt_eaton	`verilogSourcelibraryDir`
249
250
251
252
253
254
255
256
257			`fs-lint`
258
259
260
261	134	jt_eaton	`dest_dir../views/syn/`
262	133	jt_eaton	`verilogSourcelibraryDir`
263
264
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