Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

cde

sram

def

 slave_clk

        clk

        clk

 mem

        cs

        cs

        wr

        wr

        rd

        rd

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      sram_def

                                verilog

                                verilog

                                cde_sram_def

                                                ADDR

                                                8

                                                WIDTH

                                                8

                                                WORDS

                                                256

                                                WRITETHRU

                                                1

                                        fs-sim

        rtl

        verilog:Kactus2:

        verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              lint:*Lint:*

              Verilog

                            fs-lint

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

                                be

                                        in

                                                        wire

                                clk

                                        in

                                                        wire

                                cs

                                        in

                                                        wire

                                rd

                                        in

                                                        wire

                                wr

                                        in

                                                        wire

                                addr

                                        in

                                                         ADDR-1

                                                        0

                                                        wire

                                wdata

                                        in

                                                         WIDTH-1

                                                        0

                                                        wire

                                rdata

                                        out

                                                         WIDTH-1

                                                        0

                                                        reg

      fs-common

        ../verilog/sram_def

        verilogSourcefragment

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/sram_def

        verilogSourcemodule

        dest_dir../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/sram_def

        verilogSourcemodule

        dest_dir../views/syn/

        verilogSourcelibraryDir

      fs-lint

        dest_dir../views/syn/

        verilogSourcelibraryDir

  mem

  8

     mem

     0x0000

       mem