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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 mem
  
  
  
  
  
    
 
      
        cs
        cs
        
      
 
      
        wr
        wr
        
      
 
      
        rd
        rd
        
      
 
    
 
 

 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

ADDR0
WIDTH0
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}

 

 
 
 
cs
wire
in

 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 

 
 
 
 
   
      fs-sim
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
  mem
  8
   
     mem
     0x0000
      
       mem
     
   
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`def default`
16
17
18
19
20
21			`slave_clk`
22
23
24
25
26
27			`clk`
28			`clk`
29
30
31
32
33
34			`mem`
35
36
37
38
39
40
41
42
43			`cs`
44			`cs`
45
46
47
48
49			`wr`
50			`wr`
51
52
53
54
55			`rd`
56			`rd`
57
58
59
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61
62
63
64
65
66
67
68
69
70			`sim:Simulation:`
71			`Verilog`
72
73
74			`fs-sim`
75
76
77
78
79			`syn:Synthesis:`
80			`Verilog`
81
82
83			`fs-syn`
84
85
86
87
88
89			`lintlint`
90			`Verilog`
91
92
93			`fs-lint`
94
95
96
97
98
99
100
101
102			`doc`
103
104
105			`spirit:library="Testbench"`
106			`spirit:name="toolflow"`
107			`spirit:version="documentation"/>`
108
109			`:Documentation:`
110			`Verilog`
111
112
113
114
115
116
117
118
119
120
121			`ADDR0`
122			`WIDTH0`
123			`WORDS0`
124			`WRITETHRU0`
125			`DEFAULT{WIDTH{1'bx}}`
126
127
128
129
130
131
132			`cs`
133			`wire`
134			`in`
135
136
137			`addr`
138			`wire`
139			`in`
140			`ADDR-10`
141
142
143
144			`wdata`
145			`wire`
146			`in`
147			`WIDTH-10`
148
149
150			`rdata`
151			`reg`
152			`out`
153			`WIDTH-10`
154
155
156
157
158
159
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163
164
165
166
167
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169
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172
173
174			`fs-sim`
175
176
177
178
179			`dest_dir../verilog/`
180			`verilogSourcelibraryDir`
181
182
183
184
185
186
187
188
189			`fs-syn`
190
191
192
193
194			`dest_dir../verilog/`
195			`verilogSourcelibraryDir`
196
197
198
199
200
201
202
203
204
205
206			`fs-lint`
207
208
209
210			`dest_dir../verilog/lint/`
211			`verilogSourcelibraryDir`
212
213
214
215
216
217
218
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224
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228
229
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231
232
233			`mem`
234			`8`
235
236			`mem`
237			`0x0000`
238
239			`mem`
240
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