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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 mem
  
  
  
  
  
    
 
      
        cs
        cs
        
      
 
      
        wr
        wr
        
      
 
      
        rd
        rd
        
      
 
    
 
 

 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sram_def
    
  

 

 
 
 
 
 
 
 

       
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
             
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

 
 
 
cs
wire
in

 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/sram_def
        verilogSourcefragment
      
 
 
 
 
 
 
   
 
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
    
        
        ../verilog/common/sram_def
        verilogSourcemodule
      
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
    
        
        ../verilog/common/sram_def
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
  mem
  8
   
     mem
     0x0000
      
       mem
     
   
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`def default`
16
17
18
19
20
21			`slave_clk`
22
23
24
25
26
27			`clk`
28			`clk`
29
30
31
32
33
34			`mem`
35
36
37
38
39
40
41
42
43			`cs`
44			`cs`
45
46
47
48
49			`wr`
50			`wr`
51
52
53
54
55			`rd`
56			`rd`
57
58
59
60
61
62
63
64
65
66	134	jt_eaton
67
68
69
70
71			`gen_verilog`
72			`104.0`
73			`none`
74			`common`
75			`./tools/verilog/gen_verilog`
76
77
78			`destination`
79			`sram_def`
80
81
82
83
84
85
86
87
88
89
90
91
92	131	jt_eaton
93
94
95	134	jt_eaton
96			`verilog`
97
98
99			`spirit:library="Testbench"`
100			`spirit:name="toolflow"`
101			`spirit:version="verilog"/>`
102
103
104
105
106			`commoncommon`
107			`Verilog`
108
109
110			`fs-common`
111
112
113
114
115
116
117	131	jt_eaton
118			`sim:Simulation:`
119			`Verilog`
120
121
122			`fs-sim`
123
124
125
126
127			`syn:Synthesis:`
128			`Verilog`
129
130
131			`fs-syn`
132
133
134
135
136
137			`lintlint`
138			`Verilog`
139
140
141			`fs-lint`
142
143
144
145
146
147
148
149
150			`doc`
151
152
153			`spirit:library="Testbench"`
154			`spirit:name="toolflow"`
155			`spirit:version="documentation"/>`
156
157			`:Documentation:`
158			`Verilog`
159
160
161
162
163
164
165
166
167
168
169
170
171
172			`cs`
173			`wire`
174			`in`
175
176
177			`addr`
178			`wire`
179			`in`
180			`ADDR-10`
181
182
183
184			`wdata`
185			`wire`
186			`in`
187			`WIDTH-10`
188
189
190			`rdata`
191			`reg`
192			`out`
193			`WIDTH-10`
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211	134	jt_eaton
212			`fs-common`
213	131	jt_eaton
214	134	jt_eaton
215
216			`../verilog/sram_def`
217			`verilogSourcefragment`
218
219	131	jt_eaton
220	134	jt_eaton
221
222
223
224
225
226
227
228
229
230	131	jt_eaton
231			`fs-sim`
232
233	134	jt_eaton
234
235			`../verilog/copyright`
236			`verilogSourceinclude`
237
238	131	jt_eaton
239
240	134	jt_eaton
241
242			`../verilog/common/sram_def`
243			`verilogSourcemodule`
244
245
246
247	131	jt_eaton
248	134	jt_eaton	`dest_dir../views/sim/`
249	131	jt_eaton	`verilogSourcelibraryDir`
250
251
252
253
254
255
256
257
258			`fs-syn`
259
260	134	jt_eaton
261
262			`../verilog/copyright`
263			`verilogSourceinclude`
264
265	131	jt_eaton
266
267	134	jt_eaton
268
269			`../verilog/common/sram_def`
270			`verilogSourcemodule`
271
272
273
274
275	131	jt_eaton
276	134	jt_eaton	`dest_dir../views/syn/`
277	131	jt_eaton	`verilogSourcelibraryDir`
278
279
280
281
282
283
284
285
286
287
288			`fs-lint`
289
290
291
292	134	jt_eaton	`dest_dir../views/syn/`
293	131	jt_eaton	`verilogSourcelibraryDir`
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315			`mem`
316			`8`
317
318			`mem`
319			`0x0000`
320
321			`mem`
322
323
324
325
326
327
328
329
330
331
332