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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
dp  default
 
 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lintlint
              Verilog
                     
                            fs-lint
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

 
ADDR0
WIDTH0
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}
 

 
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
waddr
wire
in
ADDR-10

 
raddr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
   
      fs-lint
 
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`dp default`
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29			`sim:Simulation:`
30			`Verilog`
31
32			`fs-sim`
33
34
35
36
37			`syn:Synthesis:`
38			`Verilog`
39
40			`fs-syn`
41
42
43
44
45			`lintlint`
46			`Verilog`
47
48			`fs-lint`
49
50
51
52
53
54			`doc`
55
56
57			`spirit:library="Testbench"`
58			`spirit:name="toolflow"`
59			`spirit:version="documentation"/>`
60
61			`:Documentation:`
62			`Verilog`
63
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76			`ADDR0`
77			`WIDTH0`
78			`WORDS0`
79			`WRITETHRU0`
80			`DEFAULT{WIDTH{1'bx}}`
81
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88			`clk`
89			`wire`
90			`in`
91
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93			`cs`
94			`wire`
95			`in`
96
97
98			`wr`
99			`wire`
100			`in`
101
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103			`rd`
104			`wire`
105			`in`
106
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109			`waddr`
110			`wire`
111			`in`
112			`ADDR-10`
113
114
115			`raddr`
116			`wire`
117			`in`
118			`ADDR-10`
119
120
121
122			`wdata`
123			`wire`
124			`in`
125			`WIDTH-10`
126
127
128			`rdata`
129			`reg`
130			`out`
131			`WIDTH-10`
132
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150			`fs-sim`
151
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153			`dest_dir../verilog/`
154			`verilogSourcelibraryDir`
155
156
157
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161
162
163			`fs-syn`
164
165
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167			`dest_dir../verilog/`
168			`verilogSourcelibraryDir`
169
170
171
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179			`fs-lint`
180
181
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184			`dest_dir../verilog/lint/`
185			`verilogSourcelibraryDir`
186
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