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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
dp  default
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sram_dp
    
  

 

 
 
 
 
 
 
 

       
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
             
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lintlint
              Verilog
                     
                            fs-lint
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
waddr
wire
in
ADDR-10

 
raddr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 

 
  
      fs-common
 
      
        
        ../verilog/sram_dp
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
   
      fs-sim
 
 
 
    
        
        ../verilog/common/sram_dp
        verilogSourcemodule
      
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
    
        
        ../verilog/common/sram_dp
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
   
      fs-lint
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
   
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`dp default`
16
17
18
19	134	jt_eaton
20	131	jt_eaton
21	134	jt_eaton
22			`gen_verilog`
23			`104.0`
24			`none`
25			`common`
26			`./tools/verilog/gen_verilog`
27
28
29			`destination`
30			`sram_dp`
31
32
33
34	131	jt_eaton
35	134	jt_eaton
36	131	jt_eaton
37
38
39	134	jt_eaton
40
41
42
43	131	jt_eaton
44
45
46
47	134	jt_eaton
48			`verilog`
49
50
51			`spirit:library="Testbench"`
52			`spirit:name="toolflow"`
53			`spirit:version="verilog"/>`
54
55
56
57
58			`commoncommon`
59			`Verilog`
60
61
62			`fs-common`
63
64
65
66
67	131	jt_eaton
68			`sim:Simulation:`
69			`Verilog`
70
71			`fs-sim`
72
73
74
75
76			`syn:Synthesis:`
77			`Verilog`
78
79			`fs-syn`
80
81
82
83
84			`lintlint`
85			`Verilog`
86
87			`fs-lint`
88
89
90
91
92
93			`doc`
94
95
96			`spirit:library="Testbench"`
97			`spirit:name="toolflow"`
98			`spirit:version="documentation"/>`
99
100			`:Documentation:`
101			`Verilog`
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116			`clk`
117			`wire`
118			`in`
119
120
121			`cs`
122			`wire`
123			`in`
124
125
126			`wr`
127			`wire`
128			`in`
129
130
131			`rd`
132			`wire`
133			`in`
134
135
136
137			`waddr`
138			`wire`
139			`in`
140			`ADDR-10`
141
142
143			`raddr`
144			`wire`
145			`in`
146			`ADDR-10`
147
148
149
150			`wdata`
151			`wire`
152			`in`
153			`WIDTH-10`
154
155
156			`rdata`
157			`reg`
158			`out`
159			`WIDTH-10`
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175	134	jt_eaton
176			`fs-common`
177	131	jt_eaton
178	134	jt_eaton
179
180			`../verilog/sram_dp`
181			`verilogSourcefragment`
182
183	131	jt_eaton
184
185	134	jt_eaton
186
187			`../verilog/copyright`
188			`verilogSourceinclude`
189	131	jt_eaton
190
191
192
193	134	jt_eaton
194	131	jt_eaton
195
196
197	134	jt_eaton	`fs-sim`
198	131	jt_eaton
199
200	134	jt_eaton
201
202
203			`../verilog/common/sram_dp`
204			`verilogSourcemodule`
205
206
207
208	131	jt_eaton
209	134	jt_eaton	`dest_dir../views/sim/`
210	131	jt_eaton	`verilogSourcelibraryDir`
211
212
213
214
215	134	jt_eaton
216	131	jt_eaton
217
218	134	jt_eaton
219			`fs-syn`
220	131	jt_eaton
221
222	134	jt_eaton
223
224			`../verilog/common/sram_dp`
225			`verilogSourcemodule`
226
227	131	jt_eaton
228
229
230
231	134	jt_eaton	`dest_dir../views/syn/`
232	131	jt_eaton	`verilogSourcelibraryDir`
233
234
235
236
237
238
239
240	134	jt_eaton
241			`fs-lint`
242	131	jt_eaton
243	134	jt_eaton
244			`dest_dir../views/syn/`
245			`verilogSourcelibraryDir`
246
247	131	jt_eaton
248	134	jt_eaton
249	131	jt_eaton
250
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