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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
word  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 mem
  
  
  
  
  
    
 
      
        cs
        cs
        
      
 
      
        wr
        wr
        
      
 
      
        rd
        rd
        
      
 
      
        addr
        addr
        111
        
      
 
 
      
        wdata
        wdata
        150
        
      
 
 
      
        rdata
        rdata
        150
        
      
 
 
 
      
        be
        be
        10
        
      
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    
 
 

 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

ADDR0
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}

 

 
 
 
cs
wire
in

 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
150

 
be
wire
in
10

 
rdata
reg
out
150

 
 
 

 

 
 
 
 
 
 
 

 
 
 
 
   
      fs-sim
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
  mem
  8
   
     mem
     0x0000
      
       mem
     
   
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`word default`
16
17
18
19
20
21			`slave_clk`
22
23
24
25
26
27			`clk`
28			`clk`
29
30
31
32
33
34			`mem`
35
36
37
38
39
40
41
42
43			`cs`
44			`cs`
45
46
47
48
49			`wr`
50			`wr`
51
52
53
54
55			`rd`
56			`rd`
57
58
59
60
61			`addr`
62			`addr`
63			`111`
64
65
66
67
68
69			`wdata`
70			`wdata`
71			`150`
72
73
74
75
76
77			`rdata`
78			`rdata`
79			`150`
80
81
82
83
84
85
86			`be`
87			`be`
88			`10`
89
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115			`sim:Simulation:`
116			`Verilog`
117
118
119			`fs-sim`
120
121
122
123
124			`syn:Synthesis:`
125			`Verilog`
126
127
128			`fs-syn`
129
130
131
132
133
134			`lintlint`
135			`Verilog`
136
137
138			`fs-lint`
139
140
141
142
143
144
145
146
147			`doc`
148
149
150			`spirit:library="Testbench"`
151			`spirit:name="toolflow"`
152			`spirit:version="documentation"/>`
153
154			`:Documentation:`
155			`Verilog`
156
157
158
159
160
161
162
163
164
165
166			`ADDR0`
167			`WORDS0`
168			`WRITETHRU0`
169			`DEFAULT{WIDTH{1'bx}}`
170
171
172
173
174
175
176			`cs`
177			`wire`
178			`in`
179
180
181			`addr`
182			`wire`
183			`in`
184			`ADDR-10`
185
186
187
188			`wdata`
189			`wire`
190			`in`
191			`150`
192
193
194			`be`
195			`wire`
196			`in`
197			`10`
198
199
200			`rdata`
201			`reg`
202			`out`
203			`150`
204
205
206
207
208
209
210
211
212
213
214
215
216
217
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219
220
221
222
223
224			`fs-sim`
225
226
227
228
229			`dest_dir../verilog/`
230			`verilogSourcelibraryDir`
231
232
233
234
235
236
237
238
239			`fs-syn`
240
241
242
243
244			`dest_dir../verilog/`
245			`verilogSourcelibraryDir`
246
247
248
249
250
251
252
253
254
255
256			`fs-lint`
257
258
259
260			`dest_dir../verilog/lint/`
261			`verilogSourcelibraryDir`
262
263
264
265
266
267
268
269
270
271
272
273
274
275
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277
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283			`mem`
284			`8`
285
286			`mem`
287			`0x0000`
288
289			`mem`
290
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