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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
word  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 mem
  
  
  
  
  
    
 
      
        cs
        cs
        
      
 
      
        wr
        wr
        
      
 
      
        rd
        rd
        
      
 
      
        addr
        addr
        111
        
      
 
 
      
        wdata
        wdata
        150
        
      
 
 
      
        rdata
        rdata
        150
        
      
 
 
 
      
        be
        be
        10
        
      
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    
 
 

 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sram_word
    
  

 

 
 
 
 
 

       
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
             
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

 
 
 
cs
wire
in

 
addr
wire
in
ADDR1

 
 
wdata
wire
in
150

 
be
wire
in
10

 
rdata
reg
out
150

 
 
 

 

 
 
 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/sram_word
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
   
      fs-sim
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
   
        
        ../verilog/common/sram_word
        verilogSourcemodule
      
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
        
        ../verilog/common/sram_word
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
  mem
  8
   
     mem
     0x0000
      
       mem
     
   
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`word default`
16
17
18
19
20
21			`slave_clk`
22
23
24
25
26
27			`clk`
28			`clk`
29
30
31
32
33
34			`mem`
35
36
37
38
39
40
41
42
43			`cs`
44			`cs`
45
46
47
48
49			`wr`
50			`wr`
51
52
53
54
55			`rd`
56			`rd`
57
58
59
60
61			`addr`
62			`addr`
63			`111`
64
65
66
67
68
69			`wdata`
70			`wdata`
71			`150`
72
73
74
75
76
77			`rdata`
78			`rdata`
79			`150`
80
81
82
83
84
85
86			`be`
87			`be`
88			`10`
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111	134	jt_eaton
112
113
114
115			`gen_verilog`
116			`104.0`
117			`none`
118			`common`
119			`./tools/verilog/gen_verilog`
120
121
122			`destination`
123			`sram_word`
124
125
126
127
128
129
130
131
132
133
134	131	jt_eaton
135
136
137	134	jt_eaton
138			`verilog`
139
140
141			`spirit:library="Testbench"`
142			`spirit:name="toolflow"`
143			`spirit:version="verilog"/>`
144
145
146
147
148			`commoncommon`
149			`Verilog`
150
151
152			`fs-common`
153
154
155
156
157
158	131	jt_eaton
159			`sim:Simulation:`
160			`Verilog`
161
162
163			`fs-sim`
164
165
166
167
168			`syn:Synthesis:`
169			`Verilog`
170
171
172			`fs-syn`
173
174
175
176
177
178			`lintlint`
179			`Verilog`
180
181
182			`fs-lint`
183
184
185
186
187
188
189
190
191			`doc`
192
193
194			`spirit:library="Testbench"`
195			`spirit:name="toolflow"`
196			`spirit:version="documentation"/>`
197
198			`:Documentation:`
199			`Verilog`
200
201
202
203
204
205
206
207
208
209
210
211
212
213			`cs`
214			`wire`
215			`in`
216
217
218			`addr`
219			`wire`
220			`in`
221	134	jt_eaton	`ADDR1`
222	131	jt_eaton
223
224
225			`wdata`
226			`wire`
227			`in`
228			`150`
229
230
231			`be`
232			`wire`
233			`in`
234			`10`
235
236
237			`rdata`
238			`reg`
239			`out`
240			`150`
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258	134	jt_eaton
259			`fs-common`
260	131	jt_eaton
261	134	jt_eaton
262
263			`../verilog/sram_word`
264			`verilogSourcefragment`
265
266	131	jt_eaton
267	134	jt_eaton
268
269
270
271
272
273
274	131	jt_eaton
275			`fs-sim`
276
277
278	134	jt_eaton
279
280			`../verilog/copyright`
281			`verilogSourceinclude`
282
283	131	jt_eaton
284	134	jt_eaton
285
286
287			`../verilog/common/sram_word`
288			`verilogSourcemodule`
289
290
291
292	131	jt_eaton
293	134	jt_eaton	`dest_dir../views/sim/`
294	131	jt_eaton	`verilogSourcelibraryDir`
295
296
297
298
299
300
301
302
303			`fs-syn`
304
305	134	jt_eaton
306
307			`../verilog/copyright`
308			`verilogSourceinclude`
309
310	131	jt_eaton
311
312	134	jt_eaton
313
314
315			`../verilog/common/sram_word`
316			`verilogSourcemodule`
317
318
319
320
321	131	jt_eaton
322	134	jt_eaton	`dest_dir../views/syn/`
323	131	jt_eaton	`verilogSourcelibraryDir`
324
325
326
327
328
329
330
331
332
333
334			`fs-lint`
335
336
337
338	134	jt_eaton	`dest_dir../views/syn/`
339	131	jt_eaton	`verilogSourcelibraryDir`
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361			`mem`
362			`8`
363
364			`mem`
365			`0x0000`
366
367			`mem`
368
369
370
371
372
373
374
375
376
377
378