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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [verilog/] [sync_with_reset] - Blame information for rev 134

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reg [WIDTH - 1:0] sync_data [DEPTH:0];
 
 
always @(*)
  begin
    sync_data[0] = data_in;
  end
 
 
 
integer i;
always @(posedge clk or negedge reset_n)
  if (~reset_n)
     begin
     for (i = 1 ; i <= DEPTH ; i = i + 1)      sync_data[i] <= RST_VAL;
     end
 
  else
     begin
     for (i = 1 ; i <= DEPTH ; i = i + 1)      sync_data[i] <= sync_data[i-1];
     end
 
assign data_out = sync_data[DEPTH];
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`reg [WIDTH - 1:0] sync_data [DEPTH:0];`
2
3
4			`always @(*)`
5			`begin`
6			`sync_data[0] = data_in;`
7			`end`
8
9
10
11			`integer i;`
12			`always @(posedge clk or negedge reset_n)`
13			`if (~reset_n)`
14			`begin`
15			`for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= RST_VAL;`
16			`end`
17
18			`else`
19			`begin`
20			`for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1];`
21			`end`
22
23			`assign data_out = sync_data[DEPTH];`
24

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [verilog/] [sync_with_reset] - Blame information for rev 134