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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
def  default
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sync_def
    
  

 
 
 
 

 
 
 
 
 
 
 

 
 
              
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
      
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
              
 
 
 

WIDTH1
DEPTH2

 

 
clk
wire
in

 
 
data_in
wire
in
WIDTH-10

 
data_out
wire
out
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 

 
 
 
 
 
   
      fs-common
 
      
        
        ../verilog/sync_def
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/sync_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/sync_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`def default`
16
17
18
19
20
21	134	jt_eaton
22	131	jt_eaton
23
24
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26	134	jt_eaton
27			`gen_verilog`
28			`104.0`
29			`none`
30			`common`
31			`./tools/verilog/gen_verilog`
32
33
34			`destination`
35			`sync_def`
36
37
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51	131	jt_eaton
52
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56	134	jt_eaton
57			`verilog`
58
59
60			`spirit:library="Testbench"`
61			`spirit:name="toolflow"`
62			`spirit:version="verilog"/>`
63
64
65
66
67
68
69			`commoncommon`
70			`Verilog`
71
72
73			`fs-common`
74
75
76
77
78
79
80			`sim:Simulation:`
81			`Verilog`
82
83
84			`fs-sim`
85
86
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89			`syn:Synthesis:`
90			`Verilog`
91
92
93			`fs-syn`
94
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101
102	131	jt_eaton
103			`doc`
104
105
106			`spirit:library="Testbench"`
107			`spirit:name="toolflow"`
108			`spirit:version="documentation"/>`
109
110			`:Documentation:`
111			`Verilog`
112
113
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122
123			`WIDTH1`
124			`DEPTH2`
125
126
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128
129			`clk`
130			`wire`
131			`in`
132
133
134
135			`data_in`
136			`wire`
137			`in`
138			`WIDTH-10`
139
140
141			`data_out`
142			`wire`
143			`out`
144			`WIDTH-10`
145
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161	134	jt_eaton
162
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165	131	jt_eaton
166	134	jt_eaton	`fs-common`
167
168
169
170			`../verilog/sync_def`
171			`verilogSourcefragment`
172
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186	131	jt_eaton	`fs-sim`
187
188	134	jt_eaton
189
190
191			`../verilog/copyright`
192			`verilogSourceinclude`
193
194
195
196
197
198
199			`../verilog/common/sync_def`
200			`verilogSourcemodule`
201
202
203
204	131	jt_eaton
205
206			`dest_dir`
207	134	jt_eaton	`../views/sim/`
208	131	jt_eaton	`verilogSourcelibraryDir`
209
210
211
212
213
214
215			`fs-syn`
216
217	134	jt_eaton
218	131	jt_eaton
219	134	jt_eaton
220			`../verilog/copyright`
221			`verilogSourceinclude`
222
223
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226
227			`../verilog/common/sync_def`
228			`verilogSourcemodule`
229
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234	131	jt_eaton	`dest_dir`
235	134	jt_eaton	`../views/syn/`
236	131	jt_eaton	`verilogSourcelibraryDir`
237
238
239
240
241
242
243
244
245			`fs-lint`
246
247
248			`dest_dir`
249	134	jt_eaton	`../views/syn/`
250	131	jt_eaton	`verilogSourcelibraryDir`
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