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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_hysteresis.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
with_hysteresis  default
 
 
 
 

 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
              
 
 

WIDTH1
DEBOUNCE_SIZE4
DEBOUNCE_DELAY4'b1111

 

 
clk
wire
in

 
reset
wire
in

 
data_in
wire
in
WIDTH-10

 
data_out
reg
out
WIDTH-10

 
data_rise
reg
out
WIDTH-10

 
data_fall
reg
out
WIDTH-10

 

 

 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`with_hysteresis default`
16
17
18
19
20
21
22
23
24
25
26			`sim:Simulation:`
27			`Verilog`
28
29
30			`fs-sim`
31
32
33
34
35			`syn:Synthesis:`
36			`Verilog`
37
38
39			`fs-syn`
40
41
42
43
44
45
46			`doc`
47
48
49			`spirit:library="Testbench"`
50			`spirit:name="toolflow"`
51			`spirit:version="documentation"/>`
52
53			`:Documentation:`
54			`Verilog`
55
56
57
58
59
60
61
62
63
64
65			`WIDTH1`
66			`DEBOUNCE_SIZE4`
67			`DEBOUNCE_DELAY4'b1111`
68
69
70
71
72			`clk`
73			`wire`
74			`in`
75
76
77			`reset`
78			`wire`
79			`in`
80
81
82			`data_in`
83			`wire`
84			`in`
85			`WIDTH-10`
86
87
88			`data_out`
89			`reg`
90			`out`
91			`WIDTH-10`
92
93
94			`data_rise`
95			`reg`
96			`out`
97			`WIDTH-10`
98
99
100			`data_fall`
101			`reg`
102			`out`
103			`WIDTH-10`
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118			`fs-sim`
119
120
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122			`dest_dir`
123			`../verilog/`
124			`verilogSourcelibraryDir`
125
126
127
128
129
130
131			`fs-syn`
132
133
134			`dest_dir`
135			`../verilog/`
136			`verilogSourcelibraryDir`
137
138
139
140
141
142
143			`fs-lint`
144
145
146			`dest_dir`
147			`../verilog/`
148			`verilogSourcelibraryDir`
149
150
151
152
153
154
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_hysteresis.xml] - Blame information for rev 131