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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_hysteresis.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
with_hysteresis  default
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sync_with_hysteresis
    
  

 
 
 
 

 
 
 
 
 

 
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
              
 
 

WIDTH1
DEBOUNCE_SIZE4
DEBOUNCE_DELAY4'b1111

 

 
clk
wire
in

 
reset
wire
in

 
data_in
wire
in
WIDTH-10

 
data_out
reg
out
WIDTH-10

 
data_rise
reg
out
WIDTH-10

 
data_fall
reg
out
WIDTH-10

 

 

 
 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/sync_with_hysteresis
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/sync_with_hysteresis
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/sync_with_hysteresis
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
   
 
 
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_hysteresis.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`with_hysteresis default`
16
17
18
19
20	134	jt_eaton
21
22
23
24
25
26			`gen_verilog`
27			`104.0`
28			`none`
29			`common`
30			`./tools/verilog/gen_verilog`
31
32
33			`destination`
34			`sync_with_hysteresis`
35
36
37
38
39
40
41
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45
46
47
48	131	jt_eaton
49
50
51
52	134	jt_eaton
53			`verilog`
54
55
56			`spirit:library="Testbench"`
57			`spirit:name="toolflow"`
58			`spirit:version="verilog"/>`
59
60
61	131	jt_eaton
62	134	jt_eaton
63
64	131	jt_eaton
65	134	jt_eaton	`commoncommon`
66			`Verilog`
67
68
69			`fs-common`
70
71
72
73
74
75
76	131	jt_eaton	`sim:Simulation:`
77			`Verilog`
78
79
80			`fs-sim`
81
82
83
84
85			`syn:Synthesis:`
86			`Verilog`
87
88
89			`fs-syn`
90
91
92
93
94
95			`doc`
96
97
98			`spirit:library="Testbench"`
99			`spirit:name="toolflow"`
100			`spirit:version="documentation"/>`
101
102			`:Documentation:`
103			`Verilog`
104
105
106
107
108
109
110
111
112
113
114			`WIDTH1`
115			`DEBOUNCE_SIZE4`
116			`DEBOUNCE_DELAY4'b1111`
117
118
119
120
121			`clk`
122			`wire`
123			`in`
124
125
126			`reset`
127			`wire`
128			`in`
129
130
131			`data_in`
132			`wire`
133			`in`
134			`WIDTH-10`
135
136
137			`data_out`
138			`reg`
139			`out`
140			`WIDTH-10`
141
142
143			`data_rise`
144			`reg`
145			`out`
146			`WIDTH-10`
147
148
149			`data_fall`
150			`reg`
151			`out`
152			`WIDTH-10`
153
154
155
156
157
158
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160
161
162
163
164
165
166	134	jt_eaton
167	131	jt_eaton
168	134	jt_eaton	`fs-common`
169
170
171
172			`../verilog/sync_with_hysteresis`
173			`verilogSourcefragment`
174
175
176
177
178
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180
181
182
183
184	131	jt_eaton	`fs-sim`
185
186
187	134	jt_eaton
188			`../verilog/copyright`
189			`verilogSourceinclude`
190
191
192
193
194
195			`../verilog/common/sync_with_hysteresis`
196			`verilogSourcemodule`
197
198
199
200
201	131	jt_eaton	`dest_dir`
202	134	jt_eaton	`../views/sim/`
203	131	jt_eaton	`verilogSourcelibraryDir`
204
205
206
207
208
209
210			`fs-syn`
211
212	134	jt_eaton
213	131	jt_eaton
214	134	jt_eaton
215			`../verilog/copyright`
216			`verilogSourceinclude`
217
218
219
220
221
222			`../verilog/common/sync_with_hysteresis`
223			`verilogSourcemodule`
224
225
226
227	131	jt_eaton	`dest_dir`
228	134	jt_eaton	`../views/syn/`
229	131	jt_eaton	`verilogSourcelibraryDir`
230
231
232
233
234
235	134	jt_eaton
236
237	131	jt_eaton
238			`fs-lint`
239
240
241			`dest_dir`
242	134	jt_eaton	`../views/syn/`
243	131	jt_eaton	`verilogSourcelibraryDir`
244
245
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