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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
with_reset  default
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      sync_with_reset
    
  

 
 
 
 

 
 
 

 
   
 
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
 
       
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
    
 

WIDTH1
DEPTH2

 

 
clk
wire
in

 
reset_n
wire
in

 
 
data_in
wire
in
WIDTH-10

 
data_out
wire
out
WIDTH-10

 
 
 
 

 

 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sync_with_reset
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/sync_with_reset
        verilogSourcemodule
      
 
      
      dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/sync_with_reset
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
      
      dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`with_reset default`
16
17	134	jt_eaton
18
19
20
21
22
23
24
25
26			`gen_verilog`
27			`104.0`
28			`none`
29			`common`
30			`./tools/verilog/gen_verilog`
31
32
33			`destination`
34			`sync_with_reset`
35
36
37
38
39
40
41
42
43
44
45
46	131	jt_eaton
47
48
49
50
51	134	jt_eaton
52			`verilog`
53
54
55			`spirit:library="Testbench"`
56			`spirit:name="toolflow"`
57			`spirit:version="verilog"/>`
58
59
60
61
62
63
64
65
66
67			`commoncommon`
68			`Verilog`
69
70
71			`fs-common`
72
73
74
75
76
77
78			`sim:Simulation:`
79			`Verilog`
80
81
82			`fs-sim`
83
84
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86
87			`syn:Synthesis:`
88			`Verilog`
89
90
91			`fs-syn`
92
93
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96
97
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100
101	131	jt_eaton
102			`doc`
103
104
105			`spirit:library="Testbench"`
106			`spirit:name="toolflow"`
107			`spirit:version="documentation"/>`
108
109			`:Documentation:`
110			`Verilog`
111
112
113
114
115
116
117
118
119			`WIDTH1`
120			`DEPTH2`
121
122
123
124
125			`clk`
126			`wire`
127			`in`
128
129
130			`reset_n`
131			`wire`
132			`in`
133
134
135
136			`data_in`
137			`wire`
138			`in`
139			`WIDTH-10`
140
141
142			`data_out`
143			`wire`
144			`out`
145			`WIDTH-10`
146
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158
159
160	134	jt_eaton
161
162	131	jt_eaton
163	134	jt_eaton	`fs-common`
164
165
166
167			`../verilog/sync_with_reset`
168			`verilogSourcefragment`
169
170
171
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174
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178
179
180	131	jt_eaton	`fs-sim`
181
182
183
184	134	jt_eaton
185			`../verilog/copyright`
186			`verilogSourceinclude`
187
188
189
190
191
192			`../verilog/common/sync_with_reset`
193			`verilogSourcemodule`
194
195
196
197	131	jt_eaton	`dest_dir`
198	134	jt_eaton	`../views/sim/`
199	131	jt_eaton	`verilogSource`
200			`libraryDir`
201
202
203
204
205
206
207			`fs-syn`
208
209
210	134	jt_eaton
211			`../verilog/copyright`
212			`verilogSourceinclude`
213
214
215
216
217
218			`../verilog/common/sync_with_reset`
219			`verilogSourcemodule`
220
221
222
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224			`dest_dir`
225			`../views/syn/`
226	131	jt_eaton	`verilogSource`
227			`libraryDir`
228
229
230
231
232
233
234
235
236			`fs-lint`
237
238
239			`dest_dir`
240	134	jt_eaton	`../views/syn/`
241	131	jt_eaton	`verilogSource`
242			`libraryDir`
243
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