OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [fund_reset_fig1.sch] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 120 jt_eaton
v 20110115 2
2
C 56000 51800 1 0 0 reg_rst.sym
3
{
4
T 57800 53600 5 10 0 0 0 0 1
5
device=REGISTER_RST
6
T 57300 53800 5 10 1 1 0 6 1
7
refdes=U?
8
}
9
B 56000 48800 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
10
T 62400 49000 9 10 1 0 0 0 2
11
ACTIVE LOW
12
RESET
13
B 53200 41500 21200 13100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
14
C 54600 45600 1 0 0 high-1.sym
15
{
16
T 54900 45900 5 10 0 1 0 0 1
17
device=HIGH
18
T 54800 45800 5 10 1 1 0 0 1
19
refdes=H?
20
}
21
C 56100 43400 1 0 0 low-1.sym
22
{
23
T 56500 43400 5 10 0 1 0 0 1
24
device=LOW
25
T 56400 43600 5 10 1 1 0 0 1
26
refdes=G?
27
}
28
C 53800 49900 1 0 0 pullup-1.sym
29
{
30
T 54000 50000 5 10 1 1 0 0 1
31
refdes=H?
32
}
33
C 53800 50700 1 0 0 pulldown-1.sym
34
{
35
T 54000 50800 5 10 1 1 0 0 1
36
refdes=G?
37
}
38
C 54400 51500 1 0 0 ipad-1.sym
39
{
40
T 54484 51721 5 10 0 1 0 0 1
41
device=IPAD
42
T 54400 51800 5 10 1 1 0 0 1
43
refdes=TRST_n
44
}
45
N 53900 51000 53900 51600 4
46
N 53900 51600 54400 51600 4
47
N 55300 51600 56800 51600 4
48
N 56800 51600 56800 51800 4
49
C 54500 49500 1 0 0 ipad-1.sym
50
{
51
T 54584 49721 5 10 0 1 0 0 1
52
device=IPAD
53
T 54500 49800 5 10 1 1 0 0 1
54
refdes=CLK_RST_n
55
}
56
N 55400 49600 56000 49600 4
57
N 53900 49200 53900 49900 4
58
N 53900 49600 54500 49600 4
59
T 56100 49300 9 10 1 0 0 0 3
60
Metastable
61
      filter
62
        inv
63
C 56500 43700 1 90 0 asic-cap-2.sym
64
{
65
T 56100 44700 5 8 0 0 90 0 1
66
device=CAPACITOR
67
T 56100 43800 5 10 1 1 90 0 1
68
refdes=C?
69
T 56100 44300 5 10 1 1 90 0 1
70
value=1n
71
}
72
C 54100 48300 1 90 0 asic-cap-2.sym
73
{
74
T 53700 49300 5 8 0 0 90 0 1
75
device=CAPACITOR
76
T 53700 48400 5 10 1 1 90 0 1
77
refdes=C?
78
T 53700 48900 5 10 1 1 90 0 1
79
value=1n
80
}
81
C 53700 48000 1 0 0 low-1.sym
82
{
83
T 54100 48000 5 10 0 1 0 0 1
84
device=LOW
85
T 54000 48200 5 10 1 1 0 0 1
86
refdes=G?
87
}
88
C 56200 45300 1 0 0 pullup-1.sym
89
{
90
T 56400 45400 5 10 1 1 0 0 1
91
refdes=H?
92
}
93
N 56300 44600 56300 45300 4
94
N 56300 45000 57200 45000 4
95
C 57200 44900 1 0 0 ipad-1.sym
96
{
97
T 57284 45121 5 10 0 1 0 0 1
98
device=IPAD
99
T 57200 45200 5 10 1 1 0 0 1
100
refdes=PWR_ON
101
}
102
C 58200 49600 1 0 0 or2-1.sym
103
{
104
T 58600 49500 5 10 1 1 0 2 1
105
refdes=U?
106
T 58600 49700 5 8 0 0 0 0 1
107
device=or
108
}
109
N 58200 49700 57300 49700 4
110
N 57600 53400 58200 53400 4
111
N 58200 53400 58200 50100 4
112
C 54500 43700 1 0 0 low-1.sym
113
{
114
T 54900 43700 5 10 0 1 0 0 1
115
device=LOW
116
T 54800 43900 5 10 1 1 0 0 1
117
refdes=G?
118
}
119
B 54100 44000 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
120
T 54400 44800 9 10 1 0 0 0 2
121
  Power
122
Monitor
123
N 56300 45000 55400 45000 4
124
B 58400 44200 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
125
T 58500 44700 9 10 1 0 0 0 3
126
Metastable
127
      filter
128
        inv
129
N 60300 49900 59500 49900 4
130
N 60300 49500 59900 49500 4
131
N 59900 49500 59900 45000 4
132
N 59900 45000 59700 45000 4
133
N 59900 49900 59900 53600 4
134
N 59900 53600 62200 53600 4
135
T 60800 53700 9 20 1 0 0 0 1
136
clkdiv_reset
137
C 60300 49400 1 0 0 nor2-1.sym
138
{
139
T 60700 49300 5 10 1 1 0 2 1
140
refdes=U?
141
T 60700 49500 5 8 0 0 0 0 1
142
device=nor
143
}
144
C 62800 49800 1 0 0 reg_rst.sym
145
{
146
T 64600 51600 5 10 0 0 0 0 1
147
device=REGISTER_RST
148
T 64100 51800 5 10 1 1 0 6 1
149
refdes=U?
150
}
151
C 64800 49800 1 0 0 reg_rst.sym
152
{
153
T 66600 51600 5 10 0 0 0 0 1
154
device=REGISTER_RST
155
T 66100 51800 5 10 1 1 0 6 1
156
refdes=U?
157
}
158
C 66700 49800 1 0 0 reg_rst.sym
159
{
160
T 68500 51600 5 10 0 0 0 0 1
161
device=REGISTER_RST
162
T 68000 51800 5 10 1 1 0 6 1
163
refdes=U?
164
}
165
C 68500 49800 1 0 0 reg_rst.sym
166
{
167
T 70300 51600 5 10 0 0 0 0 1
168
device=REGISTER_RST
169
T 69800 51800 5 10 1 1 0 6 1
170
refdes=U?
171
}
172
C 70400 48900 1 0 0 and2-1.sym
173
{
174
T 70800 48800 5 10 1 1 0 2 1
175
refdes=U?
176
T 70800 49000 5 8 0 0 0 0 1
177
device=and
178
}
179
C 71700 47600 1 0 0 reg_rst.sym
180
{
181
T 73500 49400 5 10 0 0 0 0 1
182
device=REGISTER_RST
183
T 73000 49600 5 10 1 1 0 6 1
184
refdes=U?
185
}
186
C 70400 46700 1 0 0 and2-1.sym
187
{
188
T 70800 46600 5 10 1 1 0 2 1
189
refdes=U?
190
T 70800 46800 5 8 0 0 0 0 1
191
device=and
192
}
193
C 71700 45400 1 0 0 reg_rst.sym
194
{
195
T 73500 47200 5 10 0 0 0 0 1
196
device=REGISTER_RST
197
T 73000 47400 5 10 1 1 0 6 1
198
refdes=U?
199
}
200
V 62000 49700 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
201
T 61800 49600 9 10 1 0 0 0 1
202
DFT
203
N 69300 49800 69300 49700 4
204
N 69300 49700 62400 49700 4
205
N 63600 49800 63600 49700 4
206
N 65600 49800 65600 49700 4
207
N 64800 51400 64400 51400 4
208
N 66700 51400 66400 51400 4
209
N 68500 51400 68300 51400 4
210
N 70100 47200 70100 51400 4
211
N 70100 49400 70400 49400 4
212
N 70400 47200 70100 47200 4
213
N 70400 49000 69200 49000 4
214
N 70400 46800 69200 46800 4
215
N 72500 47600 63600 47600 4
216
N 63600 45400 63600 49700 4
217
N 72500 45400 63600 45400 4
218
C 62700 51400 1 0 0 high-1.sym
219
{
220
T 63000 51700 5 10 0 1 0 0 1
221
device=HIGH
222
T 62700 51900 5 10 1 1 0 0 1
223
refdes=H?
224
}
225
C 67600 47400 1 0 0 reg.sym
226
{
227
T 69400 49200 5 10 0 0 0 0 1
228
device=REGISTER
229
T 68900 49400 5 10 1 1 0 6 1
230
refdes=U?
231
}
232
C 67600 45200 1 0 0 reg.sym
233
{
234
T 69400 47000 5 10 0 0 0 0 1
235
device=REGISTER
236
T 68900 47200 5 10 1 1 0 6 1
237
refdes=U?
238
}
239
N 67500 49800 67500 49700 4
240
T 72800 44900 9 10 1 0 0 0 3
241
ACTIVE LOW
242
RESETS TO
243
COMPONENTS
244
N 73300 49200 74100 49200 4
245
N 73300 47000 74100 47000 4
246
T 62900 52300 9 25 1 0 0 0 1
247
Synchronous Reset Distribution Tree
248
T 67400 44300 9 25 1 0 0 0 2
249
Soft Reset
250
 Sources
251
T 53400 52600 9 25 1 0 0 0 2
252
JTAG RPC
253
CONTROL
254
T 54900 47800 9 25 1 0 0 0 2
255
SIM/TEST
256
   RESET
257
T 64500 42100 9 40 1 0 0 0 1
258
Modern ASIC Reset System
259
C 58100 42900 1 0 1 out_port.sym
260
{
261
T 57798 43118 5 10 0 1 0 6 1
262
device=OPAD
263
T 57200 43200 5 10 1 1 0 0 1
264
refdes=PWR_ON
265
}
266
N 57000 45000 57000 43000 4
267
N 57000 43000 57200 43000 4
268
B 58400 42400 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
269
N 58100 43000 58400 43000 4
270
T 58600 43100 9 10 1 0 0 0 1
271
WatchDog
272
N 58100 45000 58400 45000 4
273
T 53600 42000 9 25 1 0 0 0 2
274
PCA PWR
275
 RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.