OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [reset_fig2.sch] - Blame information for rev 81

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 jt_eaton
v 20100214 2
2
C 58200 44800 1 0 0 frame_800x600.sym
3
C 59100 46000 1 0 0 reg_rst.sym
4
{
5
T 60900 47800 5 10 0 0 0 0 1
6
device=REGISTER_RST
7
T 60400 48000 5 10 1 1 0 6 1
8
refdes=U?
9
}
10
C 64900 49100 1 0 0 reg_rst.sym
11
{
12
T 66700 50900 5 10 0 0 0 0 1
13
device=REGISTER_RST
14
T 66200 51100 5 10 1 1 0 6 1
15
refdes=U?
16
}
17
C 63600 47300 1 0 0 and2-1.sym
18
{
19
T 64000 47200 5 10 1 1 0 2 1
20
refdes=U?
21
T 64000 47400 5 8 0 0 0 0 1
22
device=and
23
}
24
T 63700 46300 9 10 1 0 0 0 3
25
ASYNCHRONOUS
26
 DFT CONTROL
27
       LOGIC
28
C 62300 47500 1 0 0 or2-1.sym
29
{
30
T 62700 47400 5 10 1 1 0 2 1
31
refdes=U?
32
T 62700 47600 5 8 0 0 0 0 1
33
device=or
34
}
35
N 60700 47600 62300 47600 4
36
N 63600 47400 63400 47400 4
37
N 63400 47400 63400 45700 4
38
N 58700 45700 63400 45700 4
39
N 59900 45700 59900 46000 4
40
N 64900 47600 65700 47600 4
41
N 65700 47600 65700 49100 4
42
N 62300 48000 62300 49000 4
43
N 62300 49000 58700 49000 4
44
T 58800 49100 9 10 1 0 0 0 1
45
ATG_ASYNCDISABLE
46
T 58700 45800 9 10 1 0 0 0 1
47
RESET_N
48
B 62000 46900 3200 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
49
T 60600 47800 9 10 1 0 0 0 2
50
ACTIVE LOW
51
RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.