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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig1.sch] - Blame information for rev 134

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Line No. Rev Author Line
1 27 jt_eaton 
v 20100214 2
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C 50500 14600 1 0 0 frame_800x600.sym
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B 54300 15300 1200 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 52800 15300 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 51000 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 54700 16100 9 10 1 0 0 0 1
7 
DUT
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T 52900 15700 9 10 1 0 0 0 3
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 BFM
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MODEL
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T 51000 15800 9 10 1 0 0 0 2
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 TEST_DEFINE
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B 56300 15300 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 57500 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56400 15700 9 10 1 0 0 0 3
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 BFM
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MODEL
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T 57500 15800 9 10 1 0 0 0 2
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 TEST_DEFINE
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L 52400 16100 52800 16100 3 0 0 0 -1 -1
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L 52400 16000 52800 16000 3 0 0 0 -1 -1
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L 52800 16000 52700 15900 3 0 0 0 -1 -1
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L 52800 16100 52700 16200 3 0 0 0 -1 -1
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L 52400 16100 52500 16200 3 0 0 0 -1 -1
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L 52400 16000 52500 15900 3 0 0 0 -1 -1
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L 57100 16100 57500 16100 3 0 0 0 -1 -1
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L 57100 16000 57500 16000 3 0 0 0 -1 -1
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L 57500 16000 57400 15900 3 0 0 0 -1 -1
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L 57500 16100 57400 16200 3 0 0 0 -1 -1
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L 57100 16100 57200 16200 3 0 0 0 -1 -1
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L 57100 16000 57200 15900 3 0 0 0 -1 -1
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L 53600 16100 54300 16100 3 0 0 0 -1 -1
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L 53600 16000 54300 16000 3 0 0 0 -1 -1
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L 55500 16100 56300 16100 3 0 0 0 -1 -1
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L 55500 16000 56300 16000 3 0 0 0 -1 -1
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L 53600 16100 53700 16200 3 0 0 0 -1 -1
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L 53600 16000 53700 15900 3 0 0 0 -1 -1
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L 54300 16100 54200 16200 3 0 0 0 -1 -1
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L 54300 16000 54200 15900 3 0 0 0 -1 -1
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L 55500 16100 55600 16200 3 0 0 0 -1 -1
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L 55500 16000 55600 15900 3 0 0 0 -1 -1
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L 56300 16100 56200 16200 3 0 0 0 -1 -1
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L 56300 16000 56200 15900 3 0 0 0 -1 -1
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B 50700 14800 8500 2600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51200 17100 9 10 1 0 0 0 1
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TEST_CASE
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V 54700 19700 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 56400 20100 2200 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56900 20300 9 10 1 0 0 0 1
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LOG FILE
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B 56400 19100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56500 19300 9 10 1 0 0 0 1
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VALUE CHANGE DUMP  FILE
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L 55613 20072 56400 20300 3 0 0 0 -1 -1
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L 55653 19452 56400 19300 3 0 0 0 -1 -1
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L 54700 18700 54700 17400 3 0 0 0 -1 -1
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L 54700 18700 54600 18600 3 0 0 0 -1 -1
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L 54700 18700 54800 18600 3 0 0 0 -1 -1
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T 54200 19600 9 10 1 0 0 0 2
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  VERILOG
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SIMULATOR
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L 56400 20300 56283 20335 3 0 0 0 -1 -1
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L 56400 20300 56300 20200 3 0 0 0 -1 -1
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L 56400 19300 56300 19400 3 0 0 0 -1 -1
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L 56400 19300 56274 19243 3 0 0 0 -1 -1
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T 51300 20500 9 10 1 0 0 0 2
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  COMMAND
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LINE OPTIONS
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T 51400 19600 9 10 1 0 0 0 2
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FIRMWARE
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BIT IMAGE
76 39 jt_eaton 
T 51400 17800 9 10 1 0 0 0 2
77 28 jt_eaton 
EXPECTED
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VALUES
79 39 jt_eaton 
B 51200 20300 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
80 
B 51200 19400 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
81 
B 51200 18500 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
82 
L 52700 20800 53821 20187 3 0 0 0 -1 -1
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L 52700 19800 53694 19722 3 0 0 0 -1 -1
84 
L 52700 19000 53757 19362 3 0 0 0 -1 -1
85 
L 53766 19368 53633 19412 3 0 0 0 -1 -1
86 
L 53761 19363 53687 19263 3 0 0 0 -1 -1
87 
L 53816 20196 53747 20331 3 0 0 0 -1 -1
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L 53821 20177 53672 20162 3 0 0 0 -1 -1
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L 53701 19722 53561 19840 3 0 0 0 -1 -1
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L 53694 19715 53554 19641 3 0 0 0 -1 -1
91 28 jt_eaton 
B 56400 18100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 55469 19065 56400 18300 3 0 0 0 -1 -1
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L 56400 18300 56313 18439 3 0 0 0 -1 -1
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L 56400 18300 56254 18325 3 0 0 0 -1 -1
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T 56500 18300 9 10 1 0 0 0 1
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RECORDED VALUES
97 39 jt_eaton 
B 51200 17600 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51400 18700 9 10 1 0 0 0 2
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INPUT
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DATA
101 39 jt_eaton 
L 52700 18000 53950 19050 3 0 0 0 -1 -1
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L 53933 19058 53816 19050 3 0 0 0 -1 -1
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L 53948 19053 53916 18906 3 0 0 0 -1 -1

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