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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig1.sch] - Blame information for rev 27

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Line No. Rev Author Line
1 27 jt_eaton 
v 20100214 2
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C 50500 14600 1 0 0 frame_800x600.sym
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T 54700 16100 9 10 1 0 0 0 1
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DUT
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 BFM
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MODEL
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 TEST_DEFINE
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T 56400 15700 9 10 1 0 0 0 3
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 BFM
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MODEL
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 TEST_DEFINE
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B 50700 14800 8500 2600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51200 17100 9 10 1 0 0 0 1
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TEST_CASE
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T 56900 20300 9 10 1 0 0 0 1
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LOG FILE
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VALUE CHANGE DUMP  FILE
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L 54700 18700 54800 18600 3 0 0 0 -1 -1
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T 54200 19600 9 10 1 0 0 0 2
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  VERILOG
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SIMULATOR
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T 51500 20100 9 10 1 0 0 0 2
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  COMMAND
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LINE OPTIONS
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FIRMWARE
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BIT IMAGE
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FIRMWARE
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BIT IMAGE
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