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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig1.sch] - Blame information for rev 28

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Line No. Rev Author Line
1 27 jt_eaton 
v 20100214 2
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C 50500 14600 1 0 0 frame_800x600.sym
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B 51000 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 54700 16100 9 10 1 0 0 0 1
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DUT
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 BFM
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MODEL
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 TEST_DEFINE
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B 57500 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56400 15700 9 10 1 0 0 0 3
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 BFM
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MODEL
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 TEST_DEFINE
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L 52400 16100 52500 16200 3 0 0 0 -1 -1
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L 57100 16100 57500 16100 3 0 0 0 -1 -1
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L 57100 16100 57200 16200 3 0 0 0 -1 -1
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L 54300 16000 54200 15900 3 0 0 0 -1 -1
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L 55500 16000 55600 15900 3 0 0 0 -1 -1
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L 56300 16000 56200 15900 3 0 0 0 -1 -1
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B 50700 14800 8500 2600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51200 17100 9 10 1 0 0 0 1
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TEST_CASE
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V 54700 19700 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 56400 20100 2200 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56900 20300 9 10 1 0 0 0 1
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LOG FILE
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T 56500 19300 9 10 1 0 0 0 1
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VALUE CHANGE DUMP  FILE
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L 55700 19400 56400 19300 3 0 0 0 -1 -1
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L 54700 18700 54700 17400 3 0 0 0 -1 -1
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L 54700 18700 54600 18600 3 0 0 0 -1 -1
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L 54700 18700 54800 18600 3 0 0 0 -1 -1
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T 54200 19600 9 10 1 0 0 0 2
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  VERILOG
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SIMULATOR
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L 56400 19300 56300 19400 3 0 0 0 -1 -1
69 28 jt_eaton 
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T 51300 20600 9 10 1 0 0 0 2
71 27 jt_eaton 
  COMMAND
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LINE OPTIONS
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FIRMWARE
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BIT IMAGE
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T 51400 18900 9 10 1 0 0 0 2
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EXPECTED
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VALUES
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B 51200 20400 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 51200 19600 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 51200 18700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 52700 20800 53800 20100 3 0 0 0 -1 -1
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L 52700 20000 53700 19500 3 0 0 0 -1 -1
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L 52700 19000 54000 19000 3 0 0 0 -1 -1
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L 54000 19000 53772 19084 3 0 0 0 -1 -1
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L 54000 19000 53811 18890 3 0 0 0 -1 -1
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L 55400 19000 56400 18300 3 0 0 0 -1 -1
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L 56400 18300 56253 18287 3 0 0 0 -1 -1
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T 56500 18300 9 10 1 0 0 0 1
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RECORDED VALUES
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B 51200 17700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51400 17900 9 10 1 0 0 0 2
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INPUT
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DATA
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L 52700 18000 54284 18789 3 0 0 0 -1 -1
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L 54300 18800 54100 18800 3 0 0 0 -1 -1
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L 54300 18800 54210 18637 3 0 0 0 -1 -1

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