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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig2.sch] - Blame information for rev 120

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Line No. Rev Author Line
1 27 jt_eaton 
v 20100214 2
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C 50500 14600 1 0 0 frame_800x600.sym
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B 53500 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 52300 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 50600 16900 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 53600 18800 9 10 1 0 0 0 1
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DUT
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 BFM
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MODEL
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 TEST_DEFINE
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T 50700 18300 9 10 1 0 0 0 1
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CMP_A
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CMP_A
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B 55700 16900 700 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 56800 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 58000 16900 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 56900 17300 9 10 1 0 0 0 3
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 BFM
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MODEL
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 TEST_DEFINE
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CMP_C
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CMP_C
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B 53400 16400 3100 2800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 51100 19500 9 10 1 0 0 0 1
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TEST_CASE
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B 54600 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 54700 18100 9 10 1 0 0 0 1
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CMP_B
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L 54300 18000 54600 18000 3 0 0 0 -1 -1
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L 55400 18000 55700 18000 3 0 0 0 -1 -1
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L 55400 17400 55700 17400 3 0 0 0 -1 -1

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