1 |
28 |
jt_eaton |
v 20100214 2
|
2 |
|
|
C 48900 14100 1 0 0 frame_800x600.sym
|
3 |
|
|
B 52000 17400 800 2300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
4 |
|
|
B 50100 18100 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
5 |
|
|
T 52100 18500 9 10 1 0 0 0 3
|
6 |
|
|
BFM
|
7 |
|
|
MODEL
|
8 |
|
|
|
9 |
|
|
T 50100 18600 9 10 1 0 0 0 2
|
10 |
|
|
TEST_DEFINE
|
11 |
|
|
|
12 |
|
|
L 51500 18900 52000 18900 3 0 0 0 -1 -1
|
13 |
|
|
L 51500 18800 52000 18800 3 0 0 0 -1 -1
|
14 |
|
|
L 52000 18800 51900 18700 3 0 0 0 -1 -1
|
15 |
|
|
L 52000 18900 51900 19000 3 0 0 0 -1 -1
|
16 |
|
|
L 52800 19500 53100 19500 3 0 0 0 -1 -1
|
17 |
|
|
L 52800 19400 53100 19400 3 0 0 0 -1 -1
|
18 |
|
|
T 53200 19600 9 10 1 0 0 0 1
|
19 |
|
|
TIMED_DRIVER
|
20 |
|
|
B 53100 18900 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
21 |
|
|
B 55500 17000 1700 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
22 |
|
|
L 54900 17700 55000 17800 3 0 0 0 -1 -1
|
23 |
|
|
L 54900 17600 55000 17500 3 0 0 0 -1 -1
|
24 |
|
|
T 56100 18700 9 16 1 0 0 0 1
|
25 |
|
|
DUT
|
26 |
|
|
T 49200 20300 9 20 1 0 0 0 1
|
27 |
|
|
GATE SIMS
|
28 |
|
|
L 53100 19400 53000 19300 3 0 0 0 -1 -1
|
29 |
|
|
L 53100 19500 53000 19600 3 0 0 0 -1 -1
|
30 |
|
|
L 54900 19500 55500 19500 3 0 0 0 -1 -1
|
31 |
|
|
L 54900 19400 55500 19400 3 0 0 0 -1 -1
|
32 |
|
|
L 55500 19400 55400 19300 3 0 0 0 -1 -1
|
33 |
|
|
L 55500 19500 55400 19600 3 0 0 0 -1 -1
|
34 |
|
|
L 52800 18000 53100 18000 3 0 0 0 -1 -1
|
35 |
|
|
L 52800 17900 53100 17900 3 0 0 0 -1 -1
|
36 |
|
|
B 53100 17100 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
37 |
|
|
L 54900 17700 55500 17700 3 0 0 0 -1 -1
|
38 |
|
|
L 54900 17600 55500 17600 3 0 0 0 -1 -1
|
39 |
|
|
T 53200 17800 9 10 1 0 0 0 1
|
40 |
|
|
TIMED_TESTER
|
41 |
|
|
L 51500 18900 51600 19000 3 0 0 0 -1 -1
|
42 |
|
|
L 51500 18800 51600 18700 3 0 0 0 -1 -1
|
43 |
|
|
L 53100 17900 53000 17800 3 0 0 0 -1 -1
|
44 |
|
|
L 53100 18000 53000 18100 3 0 0 0 -1 -1
|
45 |
|
|
B 50100 14900 1300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
46 |
|
|
T 50100 15400 9 10 1 0 0 0 2
|
47 |
|
|
CLOCK_GEN
|
48 |
|
|
|
49 |
|
|
B 51400 15400 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
50 |
|
|
T 51500 15400 9 10 1 0 0 0 2
|
51 |
|
|
TIMING_GEN
|
52 |
|
|
|
53 |
|
|
B 51400 14900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
54 |
|
|
T 51500 14900 9 10 1 0 0 0 2
|
55 |
|
|
TIMING_GEN
|
56 |
|
|
|
57 |
|
|
B 51400 15900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
58 |
|
|
T 51500 15900 9 10 1 0 0 0 2
|
59 |
|
|
TIMING_GEN
|
60 |
|
|
|
61 |
|
|
T 53000 16100 9 10 1 0 0 0 1
|
62 |
|
|
CLK_TGEN
|
63 |
|
|
T 53000 15600 9 10 1 0 0 0 1
|
64 |
|
|
IN_TGEN
|
65 |
|
|
T 53000 15100 9 10 1 0 0 0 1
|
66 |
|
|
OUT_TGEN
|
67 |
|
|
L 53100 17200 51200 17200 3 0 0 0 -1 -1
|
68 |
|
|
L 51200 17200 51400 17300 3 0 0 0 -1 -1
|
69 |
|
|
L 51200 17200 51400 17100 3 0 0 0 -1 -1
|
70 |
|
|
T 50300 17100 9 10 1 0 0 0 1
|
71 |
|
|
FAILURE
|
72 |
|
|
L 52800 17600 52900 17700 3 0 0 0 -1 -1
|
73 |
|
|
L 52800 17500 52900 17400 3 0 0 0 -1 -1
|
74 |
|
|
L 52800 17600 53100 17600 3 0 0 0 -1 -1
|
75 |
|
|
L 52800 17500 53100 17500 3 0 0 0 -1 -1
|
76 |
|
|
T 52500 19400 9 10 1 0 0 0 1
|
77 |
|
|
out
|
78 |
|
|
T 52200 17900 9 10 1 0 0 0 1
|
79 |
|
|
expect
|
80 |
|
|
T 52200 17500 9 10 1 0 0 0 1
|
81 |
|
|
actual
|
82 |
|
|
T 53200 16700 9 10 1 0 0 0 1
|
83 |
|
|
mask
|
84 |
|
|
L 53400 16900 53400 17100 3 0 0 0 -1 -1
|
85 |
|
|
L 53400 17100 53300 17000 3 0 0 0 -1 -1
|
86 |
|
|
L 53400 17100 53500 17000 3 0 0 0 -1 -1
|
87 |
|
|
L 54500 16900 54500 17100 3 0 0 0 -1 -1
|
88 |
|
|
L 54500 17100 54400 17000 3 0 0 0 -1 -1
|
89 |
|
|
L 54500 17100 54600 17000 3 0 0 0 -1 -1
|
90 |
|
|
T 54300 16700 9 10 1 0 0 0 1
|
91 |
|
|
in_tgen
|
92 |
|
|
L 54500 18700 54500 18900 3 0 0 0 -1 -1
|
93 |
|
|
L 54500 18900 54400 18800 3 0 0 0 -1 -1
|
94 |
|
|
L 54500 18900 54600 18800 3 0 0 0 -1 -1
|
95 |
|
|
T 54300 18500 9 10 1 0 0 0 1
|
96 |
|
|
out_tgen
|