OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig6.sch] - Blame information for rev 116

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 jt_eaton 
v 20100214 2
2 
C 57800 33700 1 0 0 frame_800x600.sym
3 
B 61400 33900 2000 5500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
4 
B 58400 36700 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
5 
T 58500 37300 9 10 1 0 0 0 1
6 
REG
7 
L 59000 37100 60100 37100 3 0 0 0 -1 -1
8 
T 61500 39500 9 10 1 0 0 0 2
9 
GATES  COMP
10 
DUT
11 
B 57900 39400 1400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
12 
T 58000 39800 9 10 1 0 0 0 1
13 
CLOCK_GEN
14 
T 58100 37600 9 10 1 0 0 0 1
15 
SIG_1_DRV
16 
B 58400 35300 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
17 
L 59000 35700 60000 35700 3 0 0 0 -1 -1
18 
T 58500 35900 9 10 1 0 0 0 1
19 
REG
20 
T 58100 36200 9 10 1 0 0 0 1
21 
SIG_2_DRV
22 
B 58400 34100 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
23 
L 59000 34500 60000 34500 3 0 0 0 -1 -1
24 
T 58500 34700 9 10 1 0 0 0 1
25 
REG
26 
T 58100 35000 9 10 1 0 0 0 1
27 
SIG_3_DRV
28 
T 61400 37000 9 10 1 0 0 0 1
29 
SIG_1
30 
T 61400 35600 9 10 1 0 0 0 1
31 
SIG_2
32 
T 61400 34400 9 10 1 0 0 0 1
33 
SIG_3
34 
B 64800 38800 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
35 
L 63400 38100 64500 38100 3 0 0 0 -1 -1
36 
T 64900 39400 9 10 1 0 0 0 1
37 
REG
38 
T 64500 39700 9 10 1 0 0 0 1
39 
SIG_4_EXP
40 
B 64800 36500 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
41 
T 64900 37100 9 10 1 0 0 0 1
42 
REG
43 
T 64500 36200 9 10 1 0 0 0 1
44 
SIG_4_MASK
45 
B 64500 37700 1300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
46 
T 64600 38000 9 10 1 0 0 0 1
47 
COMPARE
48 
T 66200 38000 9 10 1 0 0 0 1
49 
FAIL
50 
L 65800 38100 66100 38100 3 0 0 0 -1 -1
51 
L 66100 38100 66000 38200 3 0 0 0 -1 -1
52 
L 66100 38100 66000 38000 3 0 0 0 -1 -1
53 
L 65100 37300 65100 37700 3 0 0 0 -1 -1
54 
L 65100 37700 65000 37600 3 0 0 0 -1 -1
55 
L 65100 37700 65200 37600 3 0 0 0 -1 -1
56 
L 65100 38800 65100 38500 3 0 0 0 -1 -1
57 
L 65100 38500 65000 38600 3 0 0 0 -1 -1
58 
L 65100 38500 65200 38600 3 0 0 0 -1 -1
59 
T 62800 38000 9 10 1 0 0 0 1
60 
SIG_4
61 
T 61500 38800 9 10 1 0 0 0 1
62 
CLK
63 
T 61500 38000 9 10 1 0 0 0 1
64 
RESET
65 
T 58000 39100 9 10 1 0 0 0 1
66 
CLK_TGEN
67 
T 58000 38800 9 10 1 0 0 0 1
68 
IN_TGEN
69 
T 58000 38500 9 10 1 0 0 0 1
70 
OUT_TGEN
71 
B 57900 39000 1400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
72 
B 57900 38700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
73 
B 57900 38400 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
74 
B 60100 38600 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
75 
T 60200 38700 9 10 1 0 0 0 2
76 
TESTER
77 
DRIVER
78 
B 60100 37800 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
79 
T 60200 37900 9 10 1 0 0 0 2
80 
TESTER
81 
DRIVER
82 
B 60100 36800 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
83 
T 60200 36900 9 10 1 0 0 0 2
84 
TESTER
85 
DRIVER
86 
B 60000 35400 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
87 
T 60100 35500 9 10 1 0 0 0 2
88 
TESTER
89 
DRIVER
90 
B 60000 34200 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
91 
T 60100 34300 9 10 1 0 0 0 2
92 
TESTER
93 
DRIVER
94 
L 61100 34500 61400 34500 3 0 0 0 -1 -1
95 
L 61100 35700 61400 35700 3 0 0 0 -1 -1
96 
L 61200 37100 61400 37100 3 0 0 0 -1 -1
97 
L 61200 38100 61400 38100 3 0 0 0 -1 -1
98 
L 61200 38900 61400 38900 3 0 0 0 -1 -1
99 
L 60100 38100 59600 38100 3 0 0 0 -1 -1
100 
L 59600 38100 59600 39600 3 0 0 0 -1 -1
101 
L 59600 39600 59300 39600 3 0 0 0 -1 -1
102 
T 59400 39700 9 10 1 0 0 0 1
103 
RESET
104 
T 59800 38900 9 10 1 0 0 0 1
105 
1
106 
L 59900 38900 60100 38900 3 0 0 0 -1 -1
107 
T 60100 33900 9 10 1 0 0 0 1
108 
IN_TGEN
109 
T 60100 39200 9 10 1 0 0 0 1
110 
CLK_TGEN
111 
T 63500 37800 9 10 1 0 0 0 1
112 
OUT_TGEN

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.