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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html>
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<head>
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  <meta http-equiv="CONTENT-TYPE" content="text/html; charset=UTF-8">
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  <title>signal,port and pad naming guidelines</title>
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</head>
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<body dir="ltr" lang="en-US">
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<div id="toc__header" dir="ltr">
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<p><br>
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<br>
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</p>
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</div>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<p><br>
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<br>
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</p>
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<p>As Digital&nbsp; designs and design teams continue to grow it is
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mandatory
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that all rtl code must follow an established name space guideline. The
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days when designers could simply pull names out of thin air are fast
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disappearing. Naming guidelines have&nbsp; three functions. First they
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ensure that no two designers select the same name for different objects
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and have a name collision. The second function is to ensure that the
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chosen names are meaningful to all of the design team. It is quite
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common for designers to select names
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that only make sense to themselves and no one else on the team. The
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third function
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is to ensure that all rtl code follows a consistent format so that it
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may be parsed
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by various eda tools.
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</p>
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<h3 class="western"><br>
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</h3>
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<h3 class="western"><br>
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</h3>
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<h3 class="western"><br>
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</h3>
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<h3 class="western">Signal ,Port and Pad Names<br>
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</h3>
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<p>Signals define the nodes inside of&nbsp; a component and each node
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must have a unique name. That signal name becomes the port name when a
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node is ported up the hierarchy. The port names become the pad names at
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the top level.&nbsp; All of these exist in the same name space along
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with other items such as instance names. Managing this name space is
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crucial.<br>
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</p>
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<p><br>
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There are two distinct groups that use these names. The IC design team
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is one group and it will use all three. The other group consists
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of&nbsp; System designers,PCB designers, Board Test engineers etc.<br>
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They only access the chip via the pad names and never see the internal
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ones.&nbsp; These two groups often have incompatible objectives. The IC
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design team is dealing with millions of names and needs a naming scheme
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that produces long descriptive names that won't collide and conveys
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information about the signals function. <br>
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</p>
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<p>The rest of the world is only dealing with a few hundred or thousand
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names. They also have their own naming requirements as well. These
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typically
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are:<br>
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</p>
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<p><br>
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</p>
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<ul>
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  <li>Short Names that fit on a schematic graphic symbol.&nbsp; If you
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have 99 short names and 1 long one then you have a long column and
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wasted white space on your schematic.</li>
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</ul>
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<br>
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<ul>
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  <li>Capital Letters.&nbsp;&nbsp; They make a packed schematic
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readable. You don't want your board designers squinting at a sheet
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trying to guess if it's a
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1 or a l.</li>
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</ul>
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<br>
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<ul>
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  <li>ATE naming requirements.&nbsp; Do you know what the IEEE 1149.1
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pad naming rules are? If not then you better not try to pick any pad
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names.</li>
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</ul>
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<br>
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<br>
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The guideline for selecting pad names is that the IC design team should
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not attempt to pick pad names based on the internal signal names.&nbsp;
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They should first meet all of the PCA customers requirements without
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regard to what names are chosen for the internal signals.&nbsp; Name
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collisions are avoided by ensuring that ALL pad names start with a
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capital letter and that all internal names&nbsp; start with a small
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one. <br>
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<br>
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<br>
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<br>
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<br>
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For internal signal and port names you must first find the four pieces
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of information that will uniquely identify every signal in the design.
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These are:<br>
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<br>
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<br>
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<ul>
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  <li>Interface Name&nbsp;&nbsp; &nbsp; You don't want 5 different ways
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to spell clock in a design.&nbsp; Each&nbsp; team must&nbsp; agree
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on&nbsp; common signal names and everyone must follow the rules. These
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are called standard interfaces. The team must create a document that
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lists all the standard interfaces&nbsp; and their names. It is
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ESSENTIAL that once a standard is chosen then all signals covered by
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that standards MUST follow the naming rules and the no signals that are
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not covered by the standard are allowed to use its name.<br>
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  </li>
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</ul>
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<br>
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<ul>
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  <li>Sub_member &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; If the standard
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interface has more than one signal&nbsp; then you must also define the
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names for each sub_member as part of the standard <br>
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  </li>
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</ul>
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<br>
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<br>
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<ul>
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  <li>Ad
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hoc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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If
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a signal is not defined by a standard interface then an ad hoc
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signal can be created based on the designers insight. If a module has 2
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or more signals with the same standard interface then a ad hoc field is
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needed to distinguish between them.</li>
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</ul>
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<br>
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<ul>
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  <li>Driving Instance&nbsp;&nbsp;&nbsp; This is the instance name that
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is driving the signal. Wired or tristate logic is not allowed. There
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will&nbsp; be one and only one driver per node.</li>
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</ul>
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<br>
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<br>
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<br>
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You can create signal names by simply gathering akk this information
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and
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concatenating it into&nbsp; a valid signal name. While you can use all
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four fields,it is acceptable to
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drop any field(s) if they are not needed to <br>
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uniquely identify a node. For example a IC design may have a signal
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named "clk". Clk is the
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standard interface name for a clock signal so we know that it is a
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clock. The clock interface has two sub_members - rising edge and
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falling edge.&nbsp; If you have N sub_members then you only have to
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identify N-1 of them. In this case the standard chooses _n for falling
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edge clocks and nothing for rising edge. clk is a rising edge clock. An
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ad hoc field is needed if the design has more than one clock and we
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have several - 2x, 4x 1.5 x etc. But again we only have to add this to
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all but one of the clocks. clk is a 1x clock. This design only has one
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clock generator so we don't need to add the driving instance.&nbsp; If
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a second clock generator is added then all of those clocks must include
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the driving instance in their name.<br>
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<br>
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<br>
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Besides defining all of the standard interfaces the design team must
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also define a field separator such as _ (underscore) as the way to
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separate the different fields that are combined to make a signal or
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port name.&nbsp; But the most important decision of all is the order
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that the fields are assembled to make up a name. This is like the Big
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Endian/Little Endian issue. They both have their strengths and
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weaknesses and it really doesn't matter which one you pick. BUT it is
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essential that the design team picks one and everybody does it that
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way. <br>
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<br>
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Signal and port names are even worse because with four fields you can
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have 24 possible signal names for each node.&nbsp; Unless everyone on
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the design team adheres to one order then it will be chaos when you try
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to architect and synthesize a design.<br>
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<br>
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<br>
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<br>
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<br>
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The recommended order for fields in a signal/port name is<br>
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<br>
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<br>
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<br>
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&nbsp;&nbsp; Driving_instance_(sep)_Ad
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hoc_(sep)_Interface_(sep)_Sub_member<br>
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<br>
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<br>
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<br>
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This ordering gives us the ability to have our signal names follow
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their function as the signals pass up and down the hierarchy. It also
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gives us an easy rule to follow when we need to pick a signal name. All
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that you need to do is find the instance name of the module that is
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driving that signal and combine it with the port name from that
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module.&nbsp; Since instance names are unique inside a design and port
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names are unique inside of a module then this rule guarantees that no
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other signal will use that name.<br>
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<br>
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By following this rule a signal name will grow as it progresses up the
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hierarchy.&nbsp; At each new level&nbsp; a new instance name&nbsp; is
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stuck on&nbsp; the front&nbsp; end and&nbsp; the&nbsp; instance name
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from the lower level&nbsp; becomes part of the ad hoc field.&nbsp; Each
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name contains a history&nbsp; of how it was created and what it does.<br>
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<br>
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<br>
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There are some special cases that can occur and these rules should be
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followed:<br>
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<br>
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<br>
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<ul>
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  <li>There is one sub_member that can be used on a&nbsp; ad hoc signal
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that is not defined as a standard interface. That sub_member is active
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low (_n).</li>
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</ul>
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<br>
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<ul>
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  <li>If a standard interface includes a signal that is itself defined
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as another&nbsp; standard interface then the interface name of the
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child becomes the sub member name for the parent. This usually occurs
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when a clock or reset is included in a bus interface. This ensures that
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when parsing the signal name it will match on both interfaces. If there
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are multiples of this interface then a ad hoc field must be perpended
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to the sub_member interface.</li>
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</ul>
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<br>
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<ul>
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  <li>If the driving instance is not known such as a module where the
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signal is an input port then the instance and port of a receiving
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instance may be used instead.</li>
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</ul>
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<br>
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<br>
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<br>
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Again remember that any field may be dropped if it is not needed to
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uniquely identify the node<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
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 src="../png/naming_guide_1.png"><br>
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<p><br>
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<br>
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<br>
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Here is an example of how this works in a real design. A router IC has
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24 instances of a ethernet interface. Each instance controls a transmit
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sram buffer and a receive sram buffer. There are four instances in a
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bank and the bank is instantiated six times. The&nbsp; receive write
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data&nbsp; for the&nbsp; third interface in the second bank
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originates&nbsp; in a register bank deep inside a submodule. The name
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of this register is sram_wdata and that was chosen because the sram bus
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is a standard interface and wdata is the sub_member for the wdata. As
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it passes through the hierarchy the driving instance name is prepended
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on the front. It always parses as a sram wdata signal but the ad hoc
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field keeps growing.</p>
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<p><br>
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If the clock signal is also included in the sram interface then it's
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name would be:</p>
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<p>&nbsp;<br>
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</p>
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<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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bank_2_eth_3_sram_clk<br>
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<br>
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</p>
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<p>It would parse as both a clock signal and a sram signal. If this
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were a dual port sram then the signal would be:</p>
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<p><br>
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</p>
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<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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bank_2_eth_3_sram_a_clk&nbsp;&nbsp;
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<br>
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</p>
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<p><br>
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</p>
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<p>Notice that there is an ad hoc field both before and after the sram
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interface name and it still parses as both a clock and a sram signal.<br>
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</p>
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<p><br>
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</p>
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<p>If you want to synthesize the bank of 4 controllers then you will
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need to set an output delay on the sram outputs as a placeholder for
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the setup and routing delays in the full chip. To do this you need the
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full instance name of the source registers as seen from the top level.
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Assuming you use the standard _reg convention it would be:<br>
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</p>
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<p><br>
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&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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eth_3/rx/sram_wdata_reg<br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<br>
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<p><br>
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</p>
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<h2>Standard Interfaces<br>
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</h2>
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<p></p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<h3 class="western">Clock <br>
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</h3>
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<p><br>
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A clock is a signal that drives the clock port of a flipflop.<br>
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</p>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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 cellpadding="4" cellspacing="4">
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  <tbody>
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    <tr>
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      <td style="vertical-align: top;">Interface<br>
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      </td>
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      <td style="vertical-align: top;">Clock<br>
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      </td>
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      <td style="vertical-align: top;">Name<br>
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      </td>
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      <td style="vertical-align: top;">Sub <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">CLK<br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">Rising Edge<br>
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      </td>
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      <td style="vertical-align: top;">CLK<br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>
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      </td>
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      <td style="vertical-align: top;">Falling Edge<br>
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      </td>
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      <td style="vertical-align: top;">CLK<br>
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      </td>
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      <td style="vertical-align: top;">_N<br>
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      </td>
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    </tr>
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  </tbody>
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</table>
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<br>
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<br>
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<br>
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<h3 class="western">Reset <br>
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</h3>
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<p><br>
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A reset is a signal forces nodes into a known safe state<br>
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</p>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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 cellpadding="4" cellspacing="4">
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  <tbody>
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    <tr>
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      <td style="vertical-align: top;">Interface<br>
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      </td>
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      <td style="vertical-align: top;">Reset<br>
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      </td>
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      <td style="vertical-align: top;">Name<br>
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      </td>
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      <td style="vertical-align: top;">Sub <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">RESET<br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">Active high sync<br>
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      </td>
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      <td style="vertical-align: top;">RESET<br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>
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      </td>
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      <td style="vertical-align: top;">Active Low async<br>
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      </td>
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      <td style="vertical-align: top;">RESET<br>
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      </td>
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      <td style="vertical-align: top;">_N<br>
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      </td>
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    </tr>
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  </tbody>
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</table>
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<br>
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<br>
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<br>
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<h3 class="western">Pads <br>
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</h3>
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<p><br>
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Pads are the connections made between the pad_ring and the core.<br>
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</p>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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 cellpadding="4" cellspacing="4">
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  <tbody>
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    <tr>
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      <td style="vertical-align: top;">Interface<br>
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      </td>
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      <td style="vertical-align: top;">Pads<br>
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      </td>
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      <td style="vertical-align: top;">Name<br>
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      </td>
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      <td style="vertical-align: top;">Sub <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">PAD<br>
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      </td>
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      <td style="vertical-align: top;"> <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
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      </td>
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      <td style="vertical-align: top;">output<br>
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      </td>
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      <td style="vertical-align: top;">PAD<br>
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      </td>
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      <td style="vertical-align: top;">_OUT <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>
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      </td>
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      <td style="vertical-align: top;">Input<br>
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      </td>
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      <td style="vertical-align: top;">PAD<br>
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      </td>
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      <td style="vertical-align: top;">_IN<br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>
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      </td>
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      <td style="vertical-align: top;">Enable<br>
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      </td>
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      <td style="vertical-align: top;">PAD<br>
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      </td>
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      <td style="vertical-align: top;">_OE<br>
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      </td>
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    </tr>
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  </tbody>
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</table>
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<br>
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<br>
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<br>
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<h3 class="western">Sram <br>
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</h3>
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<p><br>
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Sram signals connect between the core and an instantiated memory cell.<br>
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</p>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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 cellpadding="4" cellspacing="4">
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  <tbody>
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    <tr>
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      <td style="vertical-align: top;">Interface<br>
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      </td>
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      <td style="vertical-align: top;">SRAM<br>
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      </td>
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      <td style="vertical-align: top;">Name<br>
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      </td>
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      <td style="vertical-align: top;">Sub <br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>
555 
      </td>
556 
      <td style="vertical-align: top;"> <br>
557 
      </td>
558 
      <td style="vertical-align: top;">SRAM<br>
559 
      </td>
560 
      <td style="vertical-align: top;"> <br>
561 
      </td>
562 19 jt_eaton 
    </tr>
563 
    <tr>
564 80 jt_eaton 
      <td style="vertical-align: top;"> <br>
565 
      </td>
566 
      <td style="vertical-align: top;">RW Address<br>
567 
      </td>
568 
      <td style="vertical-align: top;">SRAM<br>
569 
      </td>
570 
      <td style="vertical-align: top;">_ADDR <br>
571 
      </td>
572 19 jt_eaton 
    </tr>
573 
    <tr>
574 80 jt_eaton 
      <td style="vertical-align: top;"> <br>
575 
      </td>
576 
      <td style="vertical-align: top;">Read Address<br>
577 
      </td>
578 
      <td style="vertical-align: top;">SRAM<br>
579 
      </td>
580 
      <td style="vertical-align: top;">_RADDR <br>
581 
      </td>
582 19 jt_eaton 
    </tr>
583 
    <tr>
584 80 jt_eaton 
      <td style="vertical-align: top;"> <br>
585 
      </td>
586 
      <td style="vertical-align: top;">Write Address<br>
587 
      </td>
588 
      <td style="vertical-align: top;">SRAM<br>
589 
      </td>
590 
      <td style="vertical-align: top;">_WADDR <br>
591 
      </td>
592 19 jt_eaton 
    </tr>
593 
    <tr>
594 80 jt_eaton 
      <td style="vertical-align: top;"><br>
595 
      </td>
596 
      <td style="vertical-align: top;">Write Data<br>
597 
      </td>
598 
      <td style="vertical-align: top;">SRAM<br>
599 
      </td>
600 
      <td style="vertical-align: top;">_WDATA<br>
601 
      </td>
602 19 jt_eaton 
    </tr>
603 
    <tr>
604 80 jt_eaton 
      <td style="vertical-align: top;"><br>
605 
      </td>
606 
      <td style="vertical-align: top;">Read Data<br>
607 
      </td>
608 
      <td style="vertical-align: top;">SRAM<br>
609 
      </td>
610 
      <td style="vertical-align: top;">_RDATA<br>
611 
      </td>
612 19 jt_eaton 
    </tr>
613 
    <tr>
614 80 jt_eaton 
      <td style="vertical-align: top;"><br>
615 
      </td>
616 
      <td style="vertical-align: top;">Ram Select<br>
617 
      </td>
618 
      <td style="vertical-align: top;">SRAM<br>
619 
      </td>
620 
      <td style="vertical-align: top;">_CS<br>
621 
      </td>
622 19 jt_eaton 
    </tr>
623 
    <tr>
624 80 jt_eaton 
      <td style="vertical-align: top;"><br>
625 
      </td>
626 
      <td style="vertical-align: top;">Write Enable<br>
627 
      </td>
628 
      <td style="vertical-align: top;">SRAM<br>
629 
      </td>
630 
      <td style="vertical-align: top;">_WR<br>
631 
      </td>
632 19 jt_eaton 
    </tr>
633 
    <tr>
634 80 jt_eaton 
      <td style="vertical-align: top;"><br>
635 
      </td>
636 
      <td style="vertical-align: top;">Read Enable<br>
637 
      </td>
638 
      <td style="vertical-align: top;">SRAM<br>
639 
      </td>
640 
      <td style="vertical-align: top;">_RD<br>
641 
      </td>
642 19 jt_eaton 
    </tr>
643 
    <tr>
644 80 jt_eaton 
      <td style="vertical-align: top;"><br>
645 
      </td>
646 
      <td style="vertical-align: top;">Bit Write Enable<br>
647 
      </td>
648 
      <td style="vertical-align: top;">SRAM<br>
649 
      </td>
650 
      <td style="vertical-align: top;">_BE<br>
651 
      </td>
652 19 jt_eaton 
    </tr>
653 
    <tr>
654 80 jt_eaton 
      <td style="vertical-align: top;"><br>
655 
      </td>
656 
      <td style="vertical-align: top;">Clock<br>
657 
      </td>
658 
      <td style="vertical-align: top;">SRAM<br>
659 
      </td>
660 
      <td style="vertical-align: top;">_CLK<br>
661 
      </td>
662 19 jt_eaton 
    </tr>
663 
  </tbody>
664 
</table>
665 
<br>
666 
<br>
667 
<br>
668 80 jt_eaton 
<h3 class="western">Wishbone Bus <br>
669 
</h3>
670 19 jt_eaton 
<p><br>
671 
The wishbone bus provides microprocessor interconnection .<br>
672 
</p>
673 
<br>
674 80 jt_eaton 
<table style="text-align: left; width: 500px; height: 120px;" border="8"
675 
 cellpadding="4" cellspacing="4">
676 19 jt_eaton 
  <tbody>
677 
    <tr>
678 80 jt_eaton 
      <td style="vertical-align: top;">Interface<br>
679 
      </td>
680 
      <td style="vertical-align: top;">Wishbone<br>
681 
      </td>
682 
      <td style="vertical-align: top;">Name<br>
683 
      </td>
684 
      <td style="vertical-align: top;">Sub <br>
685 
      </td>
686 19 jt_eaton 
    </tr>
687 
    <tr>
688 80 jt_eaton 
      <td style="vertical-align: top;"> <br>
689 
      </td>
690 
      <td style="vertical-align: top;">Address<br>
691 
      </td>
692 
      <td style="vertical-align: top;">WB<br>
693 
      </td>
694 
      <td style="vertical-align: top;">_ADR<br>
695 
      </td>
696 19 jt_eaton 
    </tr>
697 
    <tr>
698 80 jt_eaton 
      <td style="vertical-align: top;"> <br>
699 
      </td>
700 
      <td style="vertical-align: top;">Write Data<br>
701 
      </td>
702 
      <td style="vertical-align: top;">WB<br>
703 
      </td>
704 
      <td style="vertical-align: top;"> _WDAT<br>
705 
      </td>
706 19 jt_eaton 
    </tr>
707 
    <tr>
708 80 jt_eaton 
      <td style="vertical-align: top;"><br>
709 
      </td>
710 
      <td style="vertical-align: top;">Read Data<br>
711 
      </td>
712 
      <td style="vertical-align: top;">WB<br>
713 
      </td>
714 
      <td style="vertical-align: top;">_RDAT<br>
715 
      </td>
716 19 jt_eaton 
    </tr>
717 
    <tr>
718 80 jt_eaton 
      <td style="vertical-align: top;"><br>
719 
      </td>
720 
      <td style="vertical-align: top;">Write Enable<br>
721 
      </td>
722 
      <td style="vertical-align: top;">WB<br>
723 
      </td>
724 
      <td style="vertical-align: top;">_WE<br>
725 
      </td>
726 19 jt_eaton 
    </tr>
727 
    <tr>
728 80 jt_eaton 
      <td style="vertical-align: top;"><br>
729 
      </td>
730 
      <td style="vertical-align: top;">Byte Select<br>
731 
      </td>
732 
      <td style="vertical-align: top;">WB<br>
733 
      </td>
734 
      <td style="vertical-align: top;">_SEL<br>
735 
      </td>
736 19 jt_eaton 
    </tr>
737 
    <tr>
738 80 jt_eaton 
      <td style="vertical-align: top;"><br>
739 
      </td>
740 
      <td style="vertical-align: top;">Cycle<br>
741 
      </td>
742 
      <td style="vertical-align: top;">WB<br>
743 
      </td>
744 
      <td style="vertical-align: top;">_CYC<br>
745 
      </td>
746 19 jt_eaton 
    </tr>
747 
    <tr>
748 80 jt_eaton 
      <td style="vertical-align: top;"><br>
749 
      </td>
750 
      <td style="vertical-align: top;">Data Strobe<br>
751 
      </td>
752 
      <td style="vertical-align: top;">WB<br>
753 
      </td>
754 
      <td style="vertical-align: top;">_STB<br>
755 
      </td>
756 19 jt_eaton 
    </tr>
757 
    <tr>
758 80 jt_eaton 
      <td style="vertical-align: top;"><br>
759 
      </td>
760 
      <td style="vertical-align: top;">Acknowledge<br>
761 
      </td>
762 
      <td style="vertical-align: top;">WB<br>
763 
      </td>
764 
      <td style="vertical-align: top;">_ACK<br>
765 
      </td>
766 19 jt_eaton 
    </tr>
767 
    <tr>
768 80 jt_eaton 
      <td style="vertical-align: top;"><br>
769 
      </td>
770 
      <td style="vertical-align: top;">CTI<br>
771 
      </td>
772 
      <td style="vertical-align: top;">WB<br>
773 
      </td>
774 
      <td style="vertical-align: top;">_CTI<br>
775 
      </td>
776 19 jt_eaton 
    </tr>
777 
  </tbody>
778 
</table>
779 
<br>
780 
<br>
781 
<br>
782 
<p></p>
783 
<br>
784 
<br>
785 
<p><br>
786 
</p>
787 
<p><br>
788 
<br>
789 
</p>
790 
<p><br>
791 
<br>
792 
</p>
793 
<p><br>
794 
<br>
795 
</p>
796 
<p><br>
797 
<br>
798 
</p>
799 
<p><br>
800 
<br>
801 
</p>
802 
<p><br>
803 
<br>
804 
</p>
805 
<p><br>
806 
<br>
807 
</p>
808 
<p><br>
809 
<br>
810 
</p>
811 
<p><br>
812 
<br>
813 
</p>
814 
<p><br>
815 
<br>
816 
</p>
817 
<p><br>
818 
<br>
819 
</p>
820 
<p><br>
821 
<br>
822 
</p>
823 
<p><br>
824 
<br>
825 
</p>
826 
<p><br>
827 
<br>
828 
</p>
829 
<p><br>
830 
<br>
831 
</p>
832 
<p><br>
833 
<br>
834 
</p>
835 
<p><br>
836 
<br>
837 
</p>
838 
<p><br>
839 
<br>
840 
</p>
841 
<p><br>
842 
<br>
843 
</p>
844 
<p><br>
845 
<br>
846 
</p>
847 
<p><br>
848 
<br>
849 
</p>
850 
</body>
851 
</html>

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