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1 19 jt_eaton 
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  <title>signal,port and pad naming guidelines</title>
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</head>
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<body dir="ltr" lang="en-US">
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<div id="toc__header" dir="ltr">
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<p><br>
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<br>
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</p>
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</div>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<p><br>
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<br>
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</p>
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<p>As designs and design teams continue to grow in size it is mandatory
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that all rtl code must follow established name space guidelines. The
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days when designers could simply pull names out of thin air are faster
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disappearing. Naming guidelines have&nbsp; three functions. First they
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ensure that no two designers select the same name for different objects
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and have a name collision. The second function is to ensure that the
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chosen names are meaningful to all of the design team. It is quite
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common for designers to select names
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that only make sense to themselves and no one else on the team. The
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third function
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is to ensure that all rtl code follows a consistent format so that it
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may be parsed
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by various eda tools.
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</p>
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<h3 class="western"><br>
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</h3>
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<h3 class="western"><br>
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</h3>
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<h3 class="western"><br>
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</h3>
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<h3 class="western">Signal ,Port and Pad Names<br>
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</h3>
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<p>Signals define the nodes inside of&nbsp; a component and each node
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must have a unique name. That signal name becomes the port name when a
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node is ported up the hierarchy. The port names become the pad names at
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the top level.&nbsp; All of these exist in the same name space along
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with other items such as instance names. Managing this name space is
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crucial.<br>
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</p>
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<p><br>
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There are two distinct groups that use these names. The IC design team
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is one group and it will use all three. The other group consists
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of&nbsp; System designers,PCB designers, Board Test engineers etc.<br>
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They only access the chip via the pad names and never see the internal
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ones.&nbsp; These two groups have incompatible objectives. The IC
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design team is dealing with millions of names and needs a naming scheme
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that produces long descriptive names that won't collide and conveys
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information about the signals function. <br>
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</p>
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<p>The rest of the world is only dealing with a few hundred or thousand
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names. They also have their own naming requirements. These typically
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are:<br>
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</p>
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<p><br>
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</p>
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<ul>
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  <li>Short Names that fit on a schematic graphic symbol.&nbsp; If you
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have 99 short names and 1 long one then you have a long column and
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wasted white space on your schematic.</li>
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</ul>
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<br>
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<ul>
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  <li>Capital Letters.&nbsp;&nbsp; They make a packed schematic
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readable. You don't want your board designers trying to guess if it's a
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1 or a l.</li>
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</ul>
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<br>
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<ul>
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  <li>ATE naming requirements.&nbsp; Do you know what the IEEE 1149.1
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pad naming rules are? If not then you shouldn't be selecting pad names.</li>
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</ul>
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<br>
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<br>
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The guideline for selecting pad names is that the IC design team should
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not attempt to pick pad names based on the internal signal names.&nbsp;
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They should first meet all of the PCA customers requirements without
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regard to what names are chosen for the internal signals.&nbsp; Name
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collisions are avoided by ensuring that ALL pad names start with a
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capital letter and that all internal names&nbsp; start with a small
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one. <br>
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<br>
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<br>
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For internal signal and port names you must first find the four pieces
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of information that will uniquely identify every signal in the design.
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These are:<br>
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<br>
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<br>
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<ul>
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  <li>Interface Name&nbsp;&nbsp; &nbsp; You don't want 5 different ways
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to spell clock in a design.&nbsp; Each&nbsp; team must&nbsp; agree
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on&nbsp; common signal names and everyone must follow the rules. These
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are called standard interfaces. The team must create a document that
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lists all the standard interfaces&nbsp; and their names. It is
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ESSENTIAL that once a standard is chosen then all signals covered by
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that standards MUST follow the naming rules and the no signals that are
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not covered by the standard are allowed to use its name.<br>
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  </li>
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</ul>
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<br>
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<ul>
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  <li>Sub_member &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; If the standard
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interface has more than one signal&nbsp; then you must also define the
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names for each sub_member as part of the standard <br>
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  </li>
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</ul>
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<br>
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<br>
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<ul>
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  <li>ad
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hoc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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If a signal is not defined by a standard interface then an ad hoc
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signal can be created based on the designers insight. If a module has 2
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or more signals with the same standard interface then a ad hoc field is
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needed to distinguish between them.</li>
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</ul>
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<br>
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<ul>
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  <li>Driving Instance&nbsp;&nbsp;&nbsp; This is the instance name that
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is driving the signal. Wired or tristate logic is not allowed. There
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will&nbsp; be one and only one driver per node.</li>
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</ul>
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<br>
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<br>
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<br>
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You can create signal names by simply gathering this information and
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concatenating it into&nbsp; a name but it is perfectly acceptable to
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drop any field(s) if they are not needed to uniquely identify a node.<br>
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For example a IC design may have a signal named "clk". Clk is the
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standard interface name for a clock signal so we know that it is a
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clock. The clock interface has two sub_members - rising edge and
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falling edge.&nbsp; If you have N sub_members then you only have to
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identify N-1 of them. In this case the standard chooses _n for falling
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edge clocks and nothing for rising edge. clk is a rising edge clock. An
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ad hoc field is needed if the design has more than one clock and we
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have several - 2x, 4x 1.5 x etc. But again we only have to add this to
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all but one of the clocks. clk is a 1x clock. This design only has one
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clock generator so we don't need to add the driving instance.&nbsp; If
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a second clock generator is added then all of those clocks must include
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the driving instance in their name.<br>
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<br>
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<br>
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Besides defining all of the standard interfaces the design team must
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also define a field separator such as _ (underscore) as the way to
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separate the different fields that are combined to make a signal or
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port name.&nbsp; But the most important decision of all is the order
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that the fields are assembled to make up a name. This is like the Big
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Endian/Little Endian issue. They both have their strengths and
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weaknesses and it really doesn't matter which one you pick. BUT it is
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essential that the design team picks one and everybody does it that
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way. <br>
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<br>
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Signal and port names are even worse because with four fields you can
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have 24 possible signal names for each node.&nbsp; Unless everyone on
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the design team adheres to one order then it will be chaos when you try
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to architect and synthesize a design.<br>
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<br>
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<br>
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<br>
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<br>
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The recommended order for fields in a signal/port name is<br>
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<br>
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<br>
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<br>
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&nbsp;&nbsp; Driving_instance_(sep)_Ad
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hoc_(sep)_Interface_(sep)_Sub_member<br>
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<br>
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<br>
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<br>
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This ordering gives us the ability to have our signal names follow
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their function as the signals pass up and down the hierarchy. It also
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gives us an easy rule to follow when we need to pick a signal name. All
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that you need to do is find the instance name of the module that is
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driving that signal and combine it with the port name from that
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module.&nbsp; Since instance names are unique inside a design and port
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names are unique inside of a module then this rule guarantees that no
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other signal will use that name.<br>
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<br>
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By following this rule a signal name will grow as it progresses up the
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hierarchy.&nbsp; At each new level&nbsp; a new instance name&nbsp; is
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stuck on&nbsp; the front&nbsp; end and&nbsp; the&nbsp; instance name
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from the lower level&nbsp; becomes part of the ad hoc field.&nbsp; Each
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name contains a history&nbsp; of how it was created and what it does.<br>
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<br>
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<br>
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There are some special cases that can occur and these rules should be
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followed:<br>
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<br>
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<br>
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<ul>
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  <li>There is one sub_member that can be used on a&nbsp; ad hoc signal
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that is not defined as a standard interface. That sub_member is active
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low (_n).</li>
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</ul>
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<br>
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<ul>
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  <li>If a standard interface includes a signal that is itself defined
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as another&nbsp; standard interface then the interface name of the
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child becomes the sub member name for the parent. This usually occurs
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when a clock or reset is included in a bus interface. This ensures that
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when parsing the signal name it will match on both interfaces. If there
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are multiples of this interface then a ad hoc field must be perpended
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to the sub_member interface.</li>
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</ul>
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<br>
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<ul>
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  <li>If the driving instance is not known such as a module where the
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signal is an input port then the instance and port of a receiving
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instance may be used instead.</li>
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</ul>
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<br>
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<br>
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<br>
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Again remember that any field may be dropped if it is not needed to
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uniquely identify the node<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
241 20 jt_eaton 
 src="../png/naming_guide_1.png"><br>
242 19 jt_eaton 
<p><br>
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<br>
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<br>
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Here is an example of how this works in a real design. A router IC has
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24 instances of a ethernet interface. Each instance controls a transmit
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sram buffer and a receive sram buffer. There are four instances in a
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bank and the bank is instantiated six times. The&nbsp; receive write
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data&nbsp; for the&nbsp; third interface in the second bank
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originates&nbsp; in a register bank deep inside a submodule. The name
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of this register is sram_wdata and that was chosen because the sram bus
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is a standard interface and wdata is the sub_member for the wdata. As
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it passes through the hierarchy the driving instance name is prepended
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on the front. It always parses as a sram wdata signal but the ad hoc
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field keeps growing.</p>
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<p><br>
257 
If the clock signal is also included in the sram interface then it's
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name would be:</p>
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<p>&nbsp;<br>
260 
</p>
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<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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bank_2_eth_3_sram_clk<br>
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<br>
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</p>
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<p>It would parse as both a clock signal and a sram signal. If this
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were a dual port sram then the signal would be:</p>
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<p><br>
268 
</p>
269 
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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bank_2_eth_3_sram_a_clk&nbsp;&nbsp; <br>
271 
</p>
272 
<p><br>
273 
</p>
274 
<p>Notice that there is an ad hoc field both before and after the sram
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interface name and it still parses as both a clock and a sram signal.<br>
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</p>
277 
<p><br>
278 
</p>
279 
<p>If you want to synthesize the bank of 4 controllers then you will
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need to set an output delay on the sram outputs as a placeholder for
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the setup and routing delays in the full chip. To do this you need the
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full instance name of the source registers as seen from the top level.
283 
Assuming you use the standard _reg convention it would be:<br>
284 
</p>
285 
<p><br>
286 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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eth_3/rx/sram_wdata_reg<br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<br>
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<p><br>
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</p>
340 
<h2>Standard Interfaces<br>
341 
</h2>
342 
<p></p>
343 
<p><br>
344 
</p>
345 
<p><br>
346 
</p>
347 
<p><br>
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</p>
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<p><br>
350 
</p>
351 
 
352 
 
353 
<h3 class="western">Clock <br></h3>
354 
<p><br>
355 
A clock is a signal that drives the clock port of a flipflop.<br>
356 
</p>
357 
<br>
358 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
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  <tbody>
360 
    <tr>
361 
      <td style="vertical-align: top;">Interface<br>    </td>
362 
      <td style="vertical-align: top;">Clock<br>      </td>
363 
      <td style="vertical-align: top;">Name<br>      </td>
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      <td style="vertical-align: top;">Sub <br>    </td>
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    </tr>
366 
    <tr>
367 
      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;"> <br>    </td>
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      <td style="vertical-align: top;">CLK<br>      </td>
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      <td style="vertical-align: top;"> <br>      </td>
371 
    </tr>
372 
    <tr>
373 
      <td style="vertical-align: top;"> <br>      </td>
374 
      <td style="vertical-align: top;">Rising Edge<br>      </td>
375 
      <td style="vertical-align: top;">CLK<br>    </td>
376 
      <td style="vertical-align: top;">  <br>      </td>
377 
    </tr>
378 
    <tr>
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      <td style="vertical-align: top;"><br>      </td>
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      <td style="vertical-align: top;">Falling Edge<br>      </td>
381 
      <td style="vertical-align: top;">CLK<br>    </td>
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      <td style="vertical-align: top;">_N<br>      </td>
383 
    </tr>
384 
  </tbody>
385 
</table>
386 
<br>
387 
<br>
388 
<br>
389 
 
390 
 
391 
 
392 
<h3 class="western">Reset <br></h3>
393 
<p><br>
394 
A reset is a signal forces nodes into a known safe state<br>
395 
</p>
396 
<br>
397 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
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  <tbody>
399 
    <tr>
400 
      <td style="vertical-align: top;">Interface<br>    </td>
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      <td style="vertical-align: top;">Reset<br>      </td>
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      <td style="vertical-align: top;">Name<br>      </td>
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      <td style="vertical-align: top;">Sub <br>    </td>
404 
    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;"> <br>    </td>
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      <td style="vertical-align: top;">RESET<br>      </td>
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      <td style="vertical-align: top;"> <br>      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;">Active high sync<br>      </td>
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      <td style="vertical-align: top;">RESET<br>    </td>
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      <td style="vertical-align: top;">  <br>      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>      </td>
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      <td style="vertical-align: top;">Active Low async<br>      </td>
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      <td style="vertical-align: top;">RESET<br>    </td>
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      <td style="vertical-align: top;">_N<br>      </td>
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    </tr>
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  </tbody>
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</table>
425 
<br>
426 
<br>
427 
<br>
428 
 
429 
 
430 
 
431 
 
432 
 
433 
<h3 class="western">Pads <br></h3>
434 
<p><br>
435 
Pads are the connections made between the pad_ring and the core.<br>
436 
</p>
437 
<br>
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<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
439 
  <tbody>
440 
    <tr>
441 
      <td style="vertical-align: top;">Interface<br>    </td>
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      <td style="vertical-align: top;">Pads<br>      </td>
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      <td style="vertical-align: top;">Name<br>      </td>
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      <td style="vertical-align: top;">Sub <br>    </td>
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    </tr>
446 
    <tr>
447 
      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;"> <br>    </td>
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      <td style="vertical-align: top;">PAD<br>      </td>
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      <td style="vertical-align: top;"> <br>      </td>
451 
    </tr>
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    <tr>
453 
      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;">output<br>      </td>
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      <td style="vertical-align: top;">PAD<br>    </td>
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      <td style="vertical-align: top;">_OUT  <br>      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>      </td>
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      <td style="vertical-align: top;">Input<br>      </td>
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      <td style="vertical-align: top;">PAD<br>    </td>
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      <td style="vertical-align: top;">_IN<br>      </td>
463 
    </tr>
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    <tr>
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      <td style="vertical-align: top;"><br>      </td>
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      <td style="vertical-align: top;">Enable<br>      </td>
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      <td style="vertical-align: top;">PAD<br>    </td>
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      <td style="vertical-align: top;">_OE<br>      </td>
469 
    </tr>
470 
  </tbody>
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</table>
472 
<br>
473 
<br>
474 
<br>
475 
 
476 
 
477 
 
478 
<h3 class="western">Sram <br></h3>
479 
<p><br>
480 
Sram signals connect between the core and an instantiated memory cell.<br>
481 
</p>
482 
<br>
483 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
484 
  <tbody>
485 
    <tr>
486 
      <td style="vertical-align: top;">Interface<br>    </td>
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      <td style="vertical-align: top;">SRAM<br>      </td>
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      <td style="vertical-align: top;">Name<br>      </td>
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      <td style="vertical-align: top;">Sub <br>    </td>
490 
    </tr>
491 
    <tr>
492 
      <td style="vertical-align: top;"> <br>      </td>
493 
      <td style="vertical-align: top;"> <br>    </td>
494 
      <td style="vertical-align: top;">SRAM<br>      </td>
495 
      <td style="vertical-align: top;"> <br>      </td>
496 
    </tr>
497 
    <tr>
498 
      <td style="vertical-align: top;"> <br>      </td>
499 
      <td style="vertical-align: top;">RW Address<br>      </td>
500 
      <td style="vertical-align: top;">SRAM<br>    </td>
501 
      <td style="vertical-align: top;">_ADDR  <br>      </td>
502 
    </tr>
503 
    <tr>
504 
      <td style="vertical-align: top;"> <br>      </td>
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      <td style="vertical-align: top;">Read Address<br>      </td>
506 
      <td style="vertical-align: top;">SRAM<br>    </td>
507 
      <td style="vertical-align: top;">_RADDR  <br>      </td>
508 
    </tr>
509 
    <tr>
510 
      <td style="vertical-align: top;"> <br>      </td>
511 
      <td style="vertical-align: top;">Write Address<br>      </td>
512 
      <td style="vertical-align: top;">SRAM<br>    </td>
513 
      <td style="vertical-align: top;">_WADDR  <br>      </td>
514 
    </tr>
515 
    <tr>
516 
      <td style="vertical-align: top;"><br>      </td>
517 
      <td style="vertical-align: top;">Write Data<br>      </td>
518 
      <td style="vertical-align: top;">SRAM<br>    </td>
519 
      <td style="vertical-align: top;">_WDATA<br>      </td>
520 
    </tr>
521 
    <tr>
522 
      <td style="vertical-align: top;"><br>      </td>
523 
      <td style="vertical-align: top;">Read Data<br>      </td>
524 
      <td style="vertical-align: top;">SRAM<br>    </td>
525 
      <td style="vertical-align: top;">_RDATA<br>      </td>
526 
    </tr>
527 
 
528 
 
529 
 
530 
    <tr>
531 
      <td style="vertical-align: top;"><br>      </td>
532 
      <td style="vertical-align: top;">Ram Select<br>      </td>
533 
      <td style="vertical-align: top;">SRAM<br>    </td>
534 
      <td style="vertical-align: top;">_CS<br>      </td>
535 
    </tr>
536 
 
537 
 
538 
    <tr>
539 
      <td style="vertical-align: top;"><br>      </td>
540 
      <td style="vertical-align: top;">Write Enable<br>      </td>
541 
      <td style="vertical-align: top;">SRAM<br>    </td>
542 
      <td style="vertical-align: top;">_WR<br>      </td>
543 
    </tr>
544 
 
545 
 
546 
    <tr>
547 
      <td style="vertical-align: top;"><br>      </td>
548 
      <td style="vertical-align: top;">Read Enable<br>      </td>
549 
      <td style="vertical-align: top;">SRAM<br>    </td>
550 
      <td style="vertical-align: top;">_RD<br>      </td>
551 
    </tr>
552 
 
553 
    <tr>
554 
      <td style="vertical-align: top;"><br>      </td>
555 
      <td style="vertical-align: top;">Bit Write Enable<br>      </td>
556 
      <td style="vertical-align: top;">SRAM<br>    </td>
557 
      <td style="vertical-align: top;">_BE<br>      </td>
558 
    </tr>
559 
 
560 
    <tr>
561 
      <td style="vertical-align: top;"><br>      </td>
562 
      <td style="vertical-align: top;">Clock<br>      </td>
563 
      <td style="vertical-align: top;">SRAM<br>    </td>
564 
      <td style="vertical-align: top;">_CLK<br>      </td>
565 
    </tr>
566 
 
567 
 
568 
 
569 
  </tbody>
570 
</table>
571 
<br>
572 
<br>
573 
<br>
574 
 
575 
<h3 class="western">Wishbone Bus <br></h3>
576 
<p><br>
577 
The wishbone bus provides microprocessor interconnection .<br>
578 
</p>
579 
<br>
580 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
581 
  <tbody>
582 
    <tr>
583 
      <td style="vertical-align: top;">Interface<br>    </td>
584 
      <td style="vertical-align: top;">Wishbone<br>      </td>
585 
      <td style="vertical-align: top;">Name<br>      </td>
586 
      <td style="vertical-align: top;">Sub <br>    </td>
587 
    </tr>
588 
    <tr>
589 
      <td style="vertical-align: top;"> <br>      </td>
590 
      <td style="vertical-align: top;">Address<br>    </td>
591 
      <td style="vertical-align: top;">WB<br>      </td>
592 
      <td style="vertical-align: top;">_ADR<br>      </td>
593 
    </tr>
594 
    <tr>
595 
      <td style="vertical-align: top;"> <br>      </td>
596 
      <td style="vertical-align: top;">Write Data<br>      </td>
597 
      <td style="vertical-align: top;">WB<br>    </td>
598 
      <td style="vertical-align: top;"> _WDAT<br>      </td>
599 
    </tr>
600 
    <tr>
601 
      <td style="vertical-align: top;"><br>      </td>
602 
      <td style="vertical-align: top;">Read Data<br>      </td>
603 
      <td style="vertical-align: top;">WB<br>    </td>
604 
      <td style="vertical-align: top;">_RDAT<br>      </td>
605 
    </tr>
606 
    <tr>
607 
      <td style="vertical-align: top;"><br>      </td>
608 
      <td style="vertical-align: top;">Write Enable<br>      </td>
609 
      <td style="vertical-align: top;">WB<br>    </td>
610 
      <td style="vertical-align: top;">_WE<br>      </td>
611 
    </tr>
612 
    <tr>
613 
      <td style="vertical-align: top;"><br>      </td>
614 
      <td style="vertical-align: top;">Byte Select<br>      </td>
615 
      <td style="vertical-align: top;">WB<br>    </td>
616 
      <td style="vertical-align: top;">_SEL<br>      </td>
617 
    </tr>
618 
    <tr>
619 
      <td style="vertical-align: top;"><br>      </td>
620 
      <td style="vertical-align: top;">Cycle<br>      </td>
621 
      <td style="vertical-align: top;">WB<br>    </td>
622 
      <td style="vertical-align: top;">_CYC<br>      </td>
623 
    </tr>
624 
    <tr>
625 
      <td style="vertical-align: top;"><br>      </td>
626 
      <td style="vertical-align: top;">Data Strobe<br>      </td>
627 
      <td style="vertical-align: top;">WB<br>    </td>
628 
      <td style="vertical-align: top;">_STB<br>      </td>
629 
    </tr>
630 
    <tr>
631 
      <td style="vertical-align: top;"><br>      </td>
632 
      <td style="vertical-align: top;">Acknowledge<br>      </td>
633 
      <td style="vertical-align: top;">WB<br>    </td>
634 
      <td style="vertical-align: top;">_ACK<br>      </td>
635 
    </tr>
636 
    <tr>
637 
      <td style="vertical-align: top;"><br>      </td>
638 
      <td style="vertical-align: top;">CTI<br>      </td>
639 
      <td style="vertical-align: top;">WB<br>    </td>
640 
      <td style="vertical-align: top;">_CTI<br>      </td>
641 
    </tr>
642 
  </tbody>
643 
</table>
644 
<br>
645 
<br>
646 
<br>
647 
 
648 
 
649 
 
650 
 
651 
 
652 
 
653 
 
654 
 
655 
 
656 
 
657 
 
658 
 
659 
 
660 
 
661 
<p></p>
662 
<br>
663 
<br>
664 
<p><br>
665 
</p>
666 
<p><br>
667 
<br>
668 
</p>
669 
<p><br>
670 
<br>
671 
</p>
672 
<p><br>
673 
<br>
674 
</p>
675 
<p><br>
676 
<br>
677 
</p>
678 
<p><br>
679 
<br>
680 
</p>
681 
<p><br>
682 
<br>
683 
</p>
684 
<p><br>
685 
<br>
686 
</p>
687 
<p><br>
688 
<br>
689 
</p>
690 
<p><br>
691 
<br>
692 
</p>
693 
<p><br>
694 
<br>
695 
</p>
696 
<p><br>
697 
<br>
698 
</p>
699 
<p><br>
700 
<br>
701 
</p>
702 
<p><br>
703 
<br>
704 
</p>
705 
<p><br>
706 
<br>
707 
</p>
708 
<p><br>
709 
<br>
710 
</p>
711 
<p><br>
712 
<br>
713 
</p>
714 
<p><br>
715 
<br>
716 
</p>
717 
<p><br>
718 
<br>
719 
</p>
720 
<p><br>
721 
<br>
722 
</p>
723 
<p><br>
724 
<br>
725 
</p>
726 
<p><br>
727 
<br>
728 
</p>
729 
</body>
730 
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