OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [guides/] [guide_names.html] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jt_eaton 
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
2 
<html>
3 
<head>
4 
  <meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
5 
  <title>signal,port and pad naming guidelines</title>
6 
  <meta name="GENERATOR" content="OpenOffice.org 3.0  (Linux)">
7 
  <meta name="CREATED" content="0;0">
8 
  <meta name="CHANGED" content="20100309;9305300">
9 
  <meta name="KEYWORDS" content="start">
10 
  <meta name="Info 3" content="">
11 
  <meta name="Info 4" content="">
12 
  <meta name="date" content="2008-01-08T12:01:41-0500">
13 
  <meta name="robots" content="index,follow">
14 
  <style type="text/css">
15 
        <!--
16 
                H3.western { font-family: "Albany", sans-serif }
17 
                H3.cjk { font-family: "HG Mincho Light J" }
18 
                H3.ctl { font-family: "Arial Unicode MS" }
19 
        -->
20 
        </style>
21 
</head>
22 
<body dir="ltr" lang="en-US">
23 
<div id="toc__header" dir="ltr">
24 
<p><br>
25 
<br>
26 
</p>
27 
</div>
28 
<h1><a name="socgen_project"></a>SOCGEN Project</h1>
29 
<h2>Signal,Port and Pad Naming Guidelines</h2>
30 
<p><br>
31 
<br>
32 
</p>
33 
<p>As designs and design teams continue to grow in size it is mandatory
34 
that all rtl code must follow established name space guidelines. The
35 
days when designers could simply pull names out of thin air are faster
36 
disappearing. Naming guidelines have&nbsp; three functions. First they
37 
ensure that no two designers select the same name for different objects
38 
and have a name collision. The second function is to ensure that the
39 
chosen names are meaningful to all of the design team. It is quite
40 
common for designers to select names
41 
that only make sense to themselves and no one else on the team. The
42 
third function
43 
is to ensure that all rtl code follows a consistent format so that it
44 
may be parsed
45 
by various eda tools.
46 
</p>
47 
<h3 class="western"><br>
48 
</h3>
49 
<h3 class="western"><br>
50 
</h3>
51 
<h3 class="western"><br>
52 
</h3>
53 
<h3 class="western">Signal ,Port and Pad Names<br>
54 
</h3>
55 
<p>Signals define the nodes inside of&nbsp; a component and each node
56 
must have a unique name. That signal name becomes the port name when a
57 
node is ported up the hierarchy. The port names become the pad names at
58 
the top level.&nbsp; All of these exist in the same name space along
59 
with other items such as instance names. Managing this name space is
60 
crucial.<br>
61 
</p>
62 
<p><br>
63 
There are two distinct groups that use these names. The IC design team
64 
is one group and it will use all three. The other group consists
65 
of&nbsp; System designers,PCB designers, Board Test engineers etc.<br>
66 
They only access the chip via the pad names and never see the internal
67 
ones.&nbsp; These two groups have incompatible objectives. The IC
68 
design team is dealing with millions of names and needs a naming scheme
69 
that produces long descriptive names that won't collide and conveys
70 
information about the signals function. <br>
71 
</p>
72 
<p>The rest of the world is only dealing with a few hundred or thousand
73 
names. They also have their own naming requirements. These typically
74 
are:<br>
75 
</p>
76 
<p><br>
77 
</p>
78 
<ul>
79 
  <li>Short Names that fit on a schematic graphic symbol.&nbsp; If you
80 
have 99 short names and 1 long one then you have a long column and
81 
wasted white space on your schematic.</li>
82 
</ul>
83 
<br>
84 
<ul>
85 
  <li>Capital Letters.&nbsp;&nbsp; They make a packed schematic
86 
readable. You don't want your board designers trying to guess if it's a
87 
1 or a l.</li>
88 
</ul>
89 
<br>
90 
<ul>
91 
  <li>ATE naming requirements.&nbsp; Do you know what the IEEE 1149.1
92 
pad naming rules are? If not then you shouldn't be selecting pad names.</li>
93 
</ul>
94 
<br>
95 
<br>
96 
The guideline for selecting pad names is that the IC design team should
97 
not attempt to pick pad names based on the internal signal names.&nbsp;
98 
They should first meet all of the PCA customers requirements without
99 
regard to what names are chosen for the internal signals.&nbsp; Name
100 
collisions are avoided by ensuring that ALL pad names start with a
101 
capital letter and that all internal names&nbsp; start with a small
102 
one. <br>
103 
<br>
104 
<br>
105 
For internal signal and port names you must first find the four pieces
106 
of information that will uniquely identify every signal in the design.
107 
These are:<br>
108 
<br>
109 
<br>
110 
<ul>
111 
  <li>Interface Name&nbsp;&nbsp; &nbsp; You don't want 5 different ways
112 
to spell clock in a design.&nbsp; Each&nbsp; team must&nbsp; agree
113 
on&nbsp; common signal names and everyone must follow the rules. These
114 
are called standard interfaces. The team must create a document that
115 
lists all the standard interfaces&nbsp; and their names. It is
116 
ESSENTIAL that once a standard is chosen then all signals covered by
117 
that standards MUST follow the naming rules and the no signals that are
118 
not covered by the standard are allowed to use its name.<br>
119 
  </li>
120 
</ul>
121 
<br>
122 
<ul>
123 
  <li>Sub_member &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; If the standard
124 
interface has more than one signal&nbsp; then you must also define the
125 
names for each sub_member as part of the standard <br>
126 
  </li>
127 
</ul>
128 
<br>
129 
<br>
130 
<ul>
131 
  <li>ad
132 
hoc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
133 
If a signal is not defined by a standard interface then an ad hoc
134 
signal can be created based on the designers insight. If a module has 2
135 
or more signals with the same standard interface then a ad hoc field is
136 
needed to distinguish between them.</li>
137 
</ul>
138 
<br>
139 
<ul>
140 
  <li>Driving Instance&nbsp;&nbsp;&nbsp; This is the instance name that
141 
is driving the signal. Wired or tristate logic is not allowed. There
142 
will&nbsp; be one and only one driver per node.</li>
143 
</ul>
144 
<br>
145 
<br>
146 
<br>
147 
You can create signal names by simply gathering this information and
148 
concatenating it into&nbsp; a name but it is perfectly acceptable to
149 
drop any field(s) if they are not needed to uniquely identify a node.<br>
150 
For example a IC design may have a signal named "clk". Clk is the
151 
standard interface name for a clock signal so we know that it is a
152 
clock. The clock interface has two sub_members - rising edge and
153 
falling edge.&nbsp; If you have N sub_members then you only have to
154 
identify N-1 of them. In this case the standard chooses _n for falling
155 
edge clocks and nothing for rising edge. clk is a rising edge clock. An
156 
ad hoc field is needed if the design has more than one clock and we
157 
have several - 2x, 4x 1.5 x etc. But again we only have to add this to
158 
all but one of the clocks. clk is a 1x clock. This design only has one
159 
clock generator so we don't need to add the driving instance.&nbsp; If
160 
a second clock generator is added then all of those clocks must include
161 
the driving instance in their name.<br>
162 
<br>
163 
<br>
164 
Besides defining all of the standard interfaces the design team must
165 
also define a field separator such as _ (underscore) as the way to
166 
separate the different fields that are combined to make a signal or
167 
port name.&nbsp; But the most important decision of all is the order
168 
that the fields are assembled to make up a name. This is like the Big
169 
Endian/Little Endian issue. They both have their strengths and
170 
weaknesses and it really doesn't matter which one you pick. BUT it is
171 
essential that the design team picks one and everybody does it that
172 
way. <br>
173 
<br>
174 
Signal and port names are even worse because with four fields you can
175 
have 24 possible signal names for each node.&nbsp; Unless everyone on
176 
the design team adheres to one order then it will be chaos when you try
177 
to architect and synthesize a design.<br>
178 
<br>
179 
<br>
180 
<br>
181 
<br>
182 
The recommended order for fields in a signal/port name is<br>
183 
<br>
184 
<br>
185 
<br>
186 
&nbsp;&nbsp; Driving_instance_(sep)_Ad
187 
hoc_(sep)_Interface_(sep)_Sub_member<br>
188 
<br>
189 
<br>
190 
<br>
191 
This ordering gives us the ability to have our signal names follow
192 
their function as the signals pass up and down the hierarchy. It also
193 
gives us an easy rule to follow when we need to pick a signal name. All
194 
that you need to do is find the instance name of the module that is
195 
driving that signal and combine it with the port name from that
196 
module.&nbsp; Since instance names are unique inside a design and port
197 
names are unique inside of a module then this rule guarantees that no
198 
other signal will use that name.<br>
199 
<br>
200 
By following this rule a signal name will grow as it progresses up the
201 
hierarchy.&nbsp; At each new level&nbsp; a new instance name&nbsp; is
202 
stuck on&nbsp; the front&nbsp; end and&nbsp; the&nbsp; instance name
203 
from the lower level&nbsp; becomes part of the ad hoc field.&nbsp; Each
204 
name contains a history&nbsp; of how it was created and what it does.<br>
205 
<br>
206 
<br>
207 
There are some special cases that can occur and these rules should be
208 
followed:<br>
209 
<br>
210 
<br>
211 
<ul>
212 
  <li>There is one sub_member that can be used on a&nbsp; ad hoc signal
213 
that is not defined as a standard interface. That sub_member is active
214 
low (_n).</li>
215 
</ul>
216 
<br>
217 
<ul>
218 
  <li>If a standard interface includes a signal that is itself defined
219 
as another&nbsp; standard interface then the interface name of the
220 
child becomes the sub member name for the parent. This usually occurs
221 
when a clock or reset is included in a bus interface. This ensures that
222 
when parsing the signal name it will match on both interfaces. If there
223 
are multiples of this interface then a ad hoc field must be perpended
224 
to the sub_member interface.</li>
225 
</ul>
226 
<br>
227 
<ul>
228 
  <li>If the driving instance is not known such as a module where the
229 
signal is an input port then the instance and port of a receiving
230 
instance may be used instead.</li>
231 
</ul>
232 
<br>
233 
<br>
234 
<br>
235 
Again remember that any field may be dropped if it is not needed to
236 
uniquely identify the node<br>
237 
<br>
238 
<br>
239 
<br>
240 
<img style="width: 800px; height: 600px;" alt=""
241 20 jt_eaton 
 src="../png/naming_guide_1.png"><br>
242 19 jt_eaton 
<p><br>
243 
<br>
244 
<br>
245 
Here is an example of how this works in a real design. A router IC has
246 
24 instances of a ethernet interface. Each instance controls a transmit
247 
sram buffer and a receive sram buffer. There are four instances in a
248 
bank and the bank is instantiated six times. The&nbsp; receive write
249 
data&nbsp; for the&nbsp; third interface in the second bank
250 
originates&nbsp; in a register bank deep inside a submodule. The name
251 
of this register is sram_wdata and that was chosen because the sram bus
252 
is a standard interface and wdata is the sub_member for the wdata. As
253 
it passes through the hierarchy the driving instance name is prepended
254 
on the front. It always parses as a sram wdata signal but the ad hoc
255 
field keeps growing.</p>
256 
<p><br>
257 
If the clock signal is also included in the sram interface then it's
258 
name would be:</p>
259 
<p>&nbsp;<br>
260 
</p>
261 
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
262 
bank_2_eth_3_sram_clk<br>
263 
<br>
264 
</p>
265 
<p>It would parse as both a clock signal and a sram signal. If this
266 
were a dual port sram then the signal would be:</p>
267 
<p><br>
268 
</p>
269 
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
270 
bank_2_eth_3_sram_a_clk&nbsp;&nbsp; <br>
271 
</p>
272 
<p><br>
273 
</p>
274 
<p>Notice that there is an ad hoc field both before and after the sram
275 
interface name and it still parses as both a clock and a sram signal.<br>
276 
</p>
277 
<p><br>
278 
</p>
279 
<p>If you want to synthesize the bank of 4 controllers then you will
280 
need to set an output delay on the sram outputs as a placeholder for
281 
the setup and routing delays in the full chip. To do this you need the
282 
full instance name of the source registers as seen from the top level.
283 
Assuming you use the standard _reg convention it would be:<br>
284 
</p>
285 
<p><br>
286 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
287 
eth_3/rx/sram_wdata_reg<br>
288 
</p>
289 
<p><br>
290 
</p>
291 
<p><br>
292 
</p>
293 
<p><br>
294 
</p>
295 
<p><br>
296 
<br>
297 
</p>
298 
<p><br>
299 
<br>
300 
</p>
301 
<p><br>
302 
<br>
303 
</p>
304 
<p><br>
305 
<br>
306 
</p>
307 
<p><br>
308 
<br>
309 
</p>
310 
<p><br>
311 
<br>
312 
</p>
313 
<p><br>
314 
<br>
315 
</p>
316 
<p><br>
317 
<br>
318 
</p>
319 
<p><br>
320 
<br>
321 
</p>
322 
<p><br>
323 
<br>
324 
</p>
325 
<p><br>
326 
<br>
327 
</p>
328 
<p><br>
329 
<br>
330 
</p>
331 
<p><br>
332 
<br>
333 
</p>
334 
<p><br>
335 
<br>
336 
</p>
337 
<br>
338 
<p><br>
339 
</p>
340 
<h2>Standard Interfaces<br>
341 
</h2>
342 
<p></p>
343 
<p><br>
344 
</p>
345 
<p><br>
346 
</p>
347 
<p><br>
348 
</p>
349 
<p><br>
350 
</p>
351 
 
352 
 
353 
<h3 class="western">Clock <br></h3>
354 
<p><br>
355 
A clock is a signal that drives the clock port of a flipflop.<br>
356 
</p>
357 
<br>
358 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
359 
  <tbody>
360 
    <tr>
361 
      <td style="vertical-align: top;">Interface<br>    </td>
362 
      <td style="vertical-align: top;">Clock<br>      </td>
363 
      <td style="vertical-align: top;">Name<br>      </td>
364 
      <td style="vertical-align: top;">Sub <br>    </td>
365 
    </tr>
366 
    <tr>
367 
      <td style="vertical-align: top;"> <br>      </td>
368 
      <td style="vertical-align: top;"> <br>    </td>
369 
      <td style="vertical-align: top;">CLK<br>      </td>
370 
      <td style="vertical-align: top;"> <br>      </td>
371 
    </tr>
372 
    <tr>
373 
      <td style="vertical-align: top;"> <br>      </td>
374 
      <td style="vertical-align: top;">Rising Edge<br>      </td>
375 
      <td style="vertical-align: top;">CLK<br>    </td>
376 
      <td style="vertical-align: top;">  <br>      </td>
377 
    </tr>
378 
    <tr>
379 
      <td style="vertical-align: top;"><br>      </td>
380 
      <td style="vertical-align: top;">Falling Edge<br>      </td>
381 
      <td style="vertical-align: top;">CLK<br>    </td>
382 
      <td style="vertical-align: top;">_N<br>      </td>
383 
    </tr>
384 
  </tbody>
385 
</table>
386 
<br>
387 
<br>
388 
<br>
389 
 
390 
 
391 
 
392 
<h3 class="western">Reset <br></h3>
393 
<p><br>
394 
A reset is a signal forces nodes into a known safe state<br>
395 
</p>
396 
<br>
397 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
398 
  <tbody>
399 
    <tr>
400 
      <td style="vertical-align: top;">Interface<br>    </td>
401 
      <td style="vertical-align: top;">Reset<br>      </td>
402 
      <td style="vertical-align: top;">Name<br>      </td>
403 
      <td style="vertical-align: top;">Sub <br>    </td>
404 
    </tr>
405 
    <tr>
406 
      <td style="vertical-align: top;"> <br>      </td>
407 
      <td style="vertical-align: top;"> <br>    </td>
408 
      <td style="vertical-align: top;">RESET<br>      </td>
409 
      <td style="vertical-align: top;"> <br>      </td>
410 
    </tr>
411 
    <tr>
412 
      <td style="vertical-align: top;"> <br>      </td>
413 
      <td style="vertical-align: top;">Active high sync<br>      </td>
414 
      <td style="vertical-align: top;">RESET<br>    </td>
415 
      <td style="vertical-align: top;">  <br>      </td>
416 
    </tr>
417 
    <tr>
418 
      <td style="vertical-align: top;"><br>      </td>
419 
      <td style="vertical-align: top;">Active Low async<br>      </td>
420 
      <td style="vertical-align: top;">RESET<br>    </td>
421 
      <td style="vertical-align: top;">_N<br>      </td>
422 
    </tr>
423 
  </tbody>
424 
</table>
425 
<br>
426 
<br>
427 
<br>
428 
 
429 
 
430 
 
431 
 
432 
 
433 
<h3 class="western">Pads <br></h3>
434 
<p><br>
435 
Pads are the connections made between the pad_ring and the core.<br>
436 
</p>
437 
<br>
438 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
439 
  <tbody>
440 
    <tr>
441 
      <td style="vertical-align: top;">Interface<br>    </td>
442 
      <td style="vertical-align: top;">Pads<br>      </td>
443 
      <td style="vertical-align: top;">Name<br>      </td>
444 
      <td style="vertical-align: top;">Sub <br>    </td>
445 
    </tr>
446 
    <tr>
447 
      <td style="vertical-align: top;"> <br>      </td>
448 
      <td style="vertical-align: top;"> <br>    </td>
449 
      <td style="vertical-align: top;">PAD<br>      </td>
450 
      <td style="vertical-align: top;"> <br>      </td>
451 
    </tr>
452 
    <tr>
453 
      <td style="vertical-align: top;"> <br>      </td>
454 
      <td style="vertical-align: top;">output<br>      </td>
455 
      <td style="vertical-align: top;">PAD<br>    </td>
456 
      <td style="vertical-align: top;">_OUT  <br>      </td>
457 
    </tr>
458 
    <tr>
459 
      <td style="vertical-align: top;"><br>      </td>
460 
      <td style="vertical-align: top;">Input<br>      </td>
461 
      <td style="vertical-align: top;">PAD<br>    </td>
462 
      <td style="vertical-align: top;">_IN<br>      </td>
463 
    </tr>
464 
    <tr>
465 
      <td style="vertical-align: top;"><br>      </td>
466 
      <td style="vertical-align: top;">Enable<br>      </td>
467 
      <td style="vertical-align: top;">PAD<br>    </td>
468 
      <td style="vertical-align: top;">_OE<br>      </td>
469 
    </tr>
470 
  </tbody>
471 
</table>
472 
<br>
473 
<br>
474 
<br>
475 
 
476 
 
477 
 
478 
<h3 class="western">Sram <br></h3>
479 
<p><br>
480 
Sram signals connect between the core and an instantiated memory cell.<br>
481 
</p>
482 
<br>
483 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
484 
  <tbody>
485 
    <tr>
486 
      <td style="vertical-align: top;">Interface<br>    </td>
487 
      <td style="vertical-align: top;">SRAM<br>      </td>
488 
      <td style="vertical-align: top;">Name<br>      </td>
489 
      <td style="vertical-align: top;">Sub <br>    </td>
490 
    </tr>
491 
    <tr>
492 
      <td style="vertical-align: top;"> <br>      </td>
493 
      <td style="vertical-align: top;"> <br>    </td>
494 
      <td style="vertical-align: top;">SRAM<br>      </td>
495 
      <td style="vertical-align: top;"> <br>      </td>
496 
    </tr>
497 
    <tr>
498 
      <td style="vertical-align: top;"> <br>      </td>
499 
      <td style="vertical-align: top;">RW Address<br>      </td>
500 
      <td style="vertical-align: top;">SRAM<br>    </td>
501 
      <td style="vertical-align: top;">_ADDR  <br>      </td>
502 
    </tr>
503 
    <tr>
504 
      <td style="vertical-align: top;"> <br>      </td>
505 
      <td style="vertical-align: top;">Read Address<br>      </td>
506 
      <td style="vertical-align: top;">SRAM<br>    </td>
507 
      <td style="vertical-align: top;">_RADDR  <br>      </td>
508 
    </tr>
509 
    <tr>
510 
      <td style="vertical-align: top;"> <br>      </td>
511 
      <td style="vertical-align: top;">Write Address<br>      </td>
512 
      <td style="vertical-align: top;">SRAM<br>    </td>
513 
      <td style="vertical-align: top;">_WADDR  <br>      </td>
514 
    </tr>
515 
    <tr>
516 
      <td style="vertical-align: top;"><br>      </td>
517 
      <td style="vertical-align: top;">Write Data<br>      </td>
518 
      <td style="vertical-align: top;">SRAM<br>    </td>
519 
      <td style="vertical-align: top;">_WDATA<br>      </td>
520 
    </tr>
521 
    <tr>
522 
      <td style="vertical-align: top;"><br>      </td>
523 
      <td style="vertical-align: top;">Read Data<br>      </td>
524 
      <td style="vertical-align: top;">SRAM<br>    </td>
525 
      <td style="vertical-align: top;">_RDATA<br>      </td>
526 
    </tr>
527 
 
528 
 
529 
 
530 
    <tr>
531 
      <td style="vertical-align: top;"><br>      </td>
532 
      <td style="vertical-align: top;">Ram Select<br>      </td>
533 
      <td style="vertical-align: top;">SRAM<br>    </td>
534 
      <td style="vertical-align: top;">_CS<br>      </td>
535 
    </tr>
536 
 
537 
 
538 
    <tr>
539 
      <td style="vertical-align: top;"><br>      </td>
540 
      <td style="vertical-align: top;">Write Enable<br>      </td>
541 
      <td style="vertical-align: top;">SRAM<br>    </td>
542 
      <td style="vertical-align: top;">_WR<br>      </td>
543 
    </tr>
544 
 
545 
 
546 
    <tr>
547 
      <td style="vertical-align: top;"><br>      </td>
548 
      <td style="vertical-align: top;">Read Enable<br>      </td>
549 
      <td style="vertical-align: top;">SRAM<br>    </td>
550 
      <td style="vertical-align: top;">_RD<br>      </td>
551 
    </tr>
552 
 
553 
    <tr>
554 
      <td style="vertical-align: top;"><br>      </td>
555 
      <td style="vertical-align: top;">Bit Write Enable<br>      </td>
556 
      <td style="vertical-align: top;">SRAM<br>    </td>
557 
      <td style="vertical-align: top;">_BE<br>      </td>
558 
    </tr>
559 
 
560 
    <tr>
561 
      <td style="vertical-align: top;"><br>      </td>
562 
      <td style="vertical-align: top;">Clock<br>      </td>
563 
      <td style="vertical-align: top;">SRAM<br>    </td>
564 
      <td style="vertical-align: top;">_CLK<br>      </td>
565 
    </tr>
566 
 
567 
 
568 
 
569 
  </tbody>
570 
</table>
571 
<br>
572 
<br>
573 
<br>
574 
 
575 
<h3 class="western">Wishbone Bus <br></h3>
576 
<p><br>
577 
The wishbone bus provides microprocessor interconnection .<br>
578 
</p>
579 
<br>
580 
<table style="text-align: left; width: 500px; height: 120px;"  border="8" cellpadding="4" cellspacing="4">
581 
  <tbody>
582 
    <tr>
583 
      <td style="vertical-align: top;">Interface<br>    </td>
584 
      <td style="vertical-align: top;">Wishbone<br>      </td>
585 
      <td style="vertical-align: top;">Name<br>      </td>
586 
      <td style="vertical-align: top;">Sub <br>    </td>
587 
    </tr>
588 
    <tr>
589 
      <td style="vertical-align: top;"> <br>      </td>
590 
      <td style="vertical-align: top;">Address<br>    </td>
591 
      <td style="vertical-align: top;">WB<br>      </td>
592 
      <td style="vertical-align: top;">_ADR<br>      </td>
593 
    </tr>
594 
    <tr>
595 
      <td style="vertical-align: top;"> <br>      </td>
596 
      <td style="vertical-align: top;">Write Data<br>      </td>
597 
      <td style="vertical-align: top;">WB<br>    </td>
598 
      <td style="vertical-align: top;"> _WDAT<br>      </td>
599 
    </tr>
600 
    <tr>
601 
      <td style="vertical-align: top;"><br>      </td>
602 
      <td style="vertical-align: top;">Read Data<br>      </td>
603 
      <td style="vertical-align: top;">WB<br>    </td>
604 
      <td style="vertical-align: top;">_RDAT<br>      </td>
605 
    </tr>
606 
    <tr>
607 
      <td style="vertical-align: top;"><br>      </td>
608 
      <td style="vertical-align: top;">Write Enable<br>      </td>
609 
      <td style="vertical-align: top;">WB<br>    </td>
610 
      <td style="vertical-align: top;">_WE<br>      </td>
611 
    </tr>
612 
    <tr>
613 
      <td style="vertical-align: top;"><br>      </td>
614 
      <td style="vertical-align: top;">Byte Select<br>      </td>
615 
      <td style="vertical-align: top;">WB<br>    </td>
616 
      <td style="vertical-align: top;">_SEL<br>      </td>
617 
    </tr>
618 
    <tr>
619 
      <td style="vertical-align: top;"><br>      </td>
620 
      <td style="vertical-align: top;">Cycle<br>      </td>
621 
      <td style="vertical-align: top;">WB<br>    </td>
622 
      <td style="vertical-align: top;">_CYC<br>      </td>
623 
    </tr>
624 
    <tr>
625 
      <td style="vertical-align: top;"><br>      </td>
626 
      <td style="vertical-align: top;">Data Strobe<br>      </td>
627 
      <td style="vertical-align: top;">WB<br>    </td>
628 
      <td style="vertical-align: top;">_STB<br>      </td>
629 
    </tr>
630 
    <tr>
631 
      <td style="vertical-align: top;"><br>      </td>
632 
      <td style="vertical-align: top;">Acknowledge<br>      </td>
633 
      <td style="vertical-align: top;">WB<br>    </td>
634 
      <td style="vertical-align: top;">_ACK<br>      </td>
635 
    </tr>
636 
    <tr>
637 
      <td style="vertical-align: top;"><br>      </td>
638 
      <td style="vertical-align: top;">CTI<br>      </td>
639 
      <td style="vertical-align: top;">WB<br>    </td>
640 
      <td style="vertical-align: top;">_CTI<br>      </td>
641 
    </tr>
642 
  </tbody>
643 
</table>
644 
<br>
645 
<br>
646 
<br>
647 
 
648 
 
649 
 
650 
 
651 
 
652 
 
653 
 
654 
 
655 
 
656 
 
657 
 
658 
 
659 
 
660 
 
661 
<p></p>
662 
<br>
663 
<br>
664 
<p><br>
665 
</p>
666 
<p><br>
667 
<br>
668 
</p>
669 
<p><br>
670 
<br>
671 
</p>
672 
<p><br>
673 
<br>
674 
</p>
675 
<p><br>
676 
<br>
677 
</p>
678 
<p><br>
679 
<br>
680 
</p>
681 
<p><br>
682 
<br>
683 
</p>
684 
<p><br>
685 
<br>
686 
</p>
687 
<p><br>
688 
<br>
689 
</p>
690 
<p><br>
691 
<br>
692 
</p>
693 
<p><br>
694 
<br>
695 
</p>
696 
<p><br>
697 
<br>
698 
</p>
699 
<p><br>
700 
<br>
701 
</p>
702 
<p><br>
703 
<br>
704 
</p>
705 
<p><br>
706 
<br>
707 
</p>
708 
<p><br>
709 
<br>
710 
</p>
711 
<p><br>
712 
<br>
713 
</p>
714 
<p><br>
715 
<br>
716 
</p>
717 
<p><br>
718 
<br>
719 
</p>
720 
<p><br>
721 
<br>
722 
</p>
723 
<p><br>
724 
<br>
725 
</p>
726 
<p><br>
727 
<br>
728 
</p>
729 
</body>
730 
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.