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  <title>Reset System Design</title>
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<div id="toc__header" dir="ltr">
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<p><br>
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</p>
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</div>
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<h1><a name="socgen_project"></a>Design considerations for Reset
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Systems<br>
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</h1>
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<p><br>
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<br>
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</p>
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<p>In a world as fast moving as the semiconductor industry&nbsp; it is
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essential that all designers continuously update their knowledge as the
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technology changes. It is very easy to become complacent and then
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suddenly discover that the techniques that have served you for many
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years no longer work.&nbsp; <br>
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<br>
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</p>
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<p>This paper was written to explore some of the mistakes that reset
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system designers have made over the years and why they are no longer
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true.<br>
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</p>
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<h3 class="western"><br>
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</h3>
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<h3 class="western"></h3>
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<h3 class="western">Do we really need a reset system? <br>
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</h3>
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<p>Actually you don't. It is a good design practice to ensure that
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there are no dead end states in your logic and that any state will
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eventually lead into a valid operating mode. For many years designs
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were simple and robust enough that they would function even if they
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were enabled without a reset. Then along came embedded processors and
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the world became much more complex. I have seen some pretty audacious
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attempts to create a watchdog&nbsp; to detect and restart a lost system
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but the best that they can do is to improve the odds that the system
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will recover. None of them were 100%.<br>
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</p>
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<p>It is possible that you do not need to reset all the storage
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elements in a design. In many cases the data is reloaded shortly before
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it is needed and it doesn't care what it was before that time. Some
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designers will leave certain storage elements off of the power on reset
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because it has no effect on the operation.<br>
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</p>
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<p>BUT.<br>
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</p>
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<p>There was a mathematician named Fermat who came up with a theorem
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that eventually became known as Fermat's last theorem. It was a simple
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little equation that worked in every test case that&nbsp; they threw at
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it and they threw a lot of test cases at it. But it took over 350 years
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before someone could prove that it would really work in all cases.</p>
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<p><br>
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If you allow your designers the option to leave storage elements off
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the power on reset system then they will come up with these wonderful
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little designs that appear to work and they will work in any test case
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that you throw at it. But it will take you FOREVER to fully verify that
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it will work in all cases.<br>
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</p>
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<p>You do not need a power on reset system for your logic to work. You
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need it&nbsp; in order to verify that your logic works.&nbsp; It takes
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longer to verify a design than it does to create it and not providing a
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100% known start up condition will make the verification effort that
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much harder. All storage elements must be on a reset if only for test
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and verification purposes. If you have logic that must function during
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a power up reset then put it on a special reset that is only active in
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test mode.<br>
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</p>
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<br>
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<h3 class="western">All components must come out of reset on exactly
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the same clock<br>
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</h3>
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That's true, or at least it was back in the 60's.&nbsp; Back then every
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component would come out of reset and start "componenting". The reset
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system acted like a conductor&nbsp; so that everybody started on the
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same beat. Those types of systems are rare today. Most major chips have
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one or more microprocessors in side so components come out of reset
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only to sit there waiting for the cpu to configure them and get them
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started.&nbsp; It doesn't matter what cycle you come out of reset on as
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long as you are up and ready&nbsp; before someone else asks you to do
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something. <br>
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<br>
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This has led to two prong approach to reset system design.&nbsp; The
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majority of the chip is on a large slow reset distribution&nbsp;
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tree&nbsp; that doesn't even try&nbsp; to get&nbsp; everybody reset on
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the&nbsp; same cycle.&nbsp; Then you have a second&nbsp; smaller and
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faster tree that only resets the cpu and anything else that can&nbsp;
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initiate activity.&nbsp; The fast reset is delayed long enough to
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ensure that the slow reset is finished before starting the cpu. In
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modern designs this can be a significant number of clock cycles. I have
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seen repairable memories where you had to hold off starting the cpu for
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3000 clocks to ensure that any repair would be finished before the cpu
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started.<br>
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<br>
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<br>
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<h3 class="western">You must design an asynchronous reset system<br>
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</h3>
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Absolutely. Most of the time your mission mode requirements will
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dictate that the power on reset system works even in the absence of
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clock. If it doesn't then the test engineer will require that all pads
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must respond to an async reset in case a board is built missing it's
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clock. Asynchronous reset design is essential.&nbsp; A power up monitor
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will drive the reset input&nbsp; active&nbsp; as the power is ramping
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up. You will not have a clock at this time so the reset system must be
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able to work without one.<br>
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<br>
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<br>
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<br>
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<h3 class="western">You must design your logic using synchronous design
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methods<br>
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</h3>
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Absolutely. Today's chips are huge. The only way that you can close
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timing on a large design is if everyone follows strict synchronous
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design rules.&nbsp; The mistake that many of todays designers make is
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that they think that because they have to design an asynchronous reset
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system that they get an exemption from following the rules for
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synchronous design.&nbsp; Sorry guys, it not one or the other its BOTH.
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You have to design a asynchronous reset system but you cannot use any
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flip flops with an asynchronous reset port.<br>
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<br>
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The funny thing is that synchronous design methodology is quite
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capable&nbsp; of&nbsp; creating an asynchronous reset&nbsp; system and
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will actually&nbsp; give you&nbsp; a smaller and faster design that
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either of the traditional&nbsp; async only or sync only solutions.<br>
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<br>
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<br>
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<h3 class="western">Don't worry about making the reset system
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testable.The test engineer has a tool that will fix any problem in the
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back end<br>
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</h3>
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That used to be true. The first thing a vendor does when they get a net
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list is to run a full drc that looks for dft issues. If anybody has any
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signals crossing between&nbsp; the async reset port on a flipflop and
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either a D or a Q port then it flags it as a violation. So you can
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either send it back to the customer and wait a week for them to find
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it, fix it, and re-synthesizes or you can eco in a test mux at the flop
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and have it fixed in 5 minutes. Everyone took the easy way out.<br>
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<br>
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But then along came Logic equivalence checking (LEC).&nbsp; The final
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routed net list will be sent back and compared with the customers
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golden net list and all of these ecos will show up&nbsp; in the report.
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Now somebody has check out each and every item in the report&nbsp;
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before you can release the masks. It now&nbsp; becomes easier for the
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customer to find and fix these errors before synthesis than it is to
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deal with thousands of lec errors.<br>
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<br>
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Besides with the newer processes the days when you could eco in a small
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tweak on a routed net list and not have it break something are fast
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disappearing.&nbsp; You will eco the rtl code and then re-synthesis and
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reroute.<br>
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<br>
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<br>
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<br>
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&nbsp;<br>
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<br>
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<h3 class="western">You must use a sync_reset pragma if you design a
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synchronous reset system<br>
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</h3>
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I cringe whenever I hear someone&nbsp; say this. If you do a
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synchronous reset design then you will find that your gate simulations
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will not run. Many of your flipflops will never reset to a known value.
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They will get a valid clock and the reset in the block will be valid
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but synthesis will have combined the reset logic in with the mission
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mode logic and it will be distributed throughout the logic cone feeding
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the D input. It also uses the flops current state in order to compute
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the next state.&nbsp; It creates a situation where if the flop has a 0
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or 1 in it then the logic will compute the next state as 0 when reset
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is active. However if the flop is unknown as it is at power up then
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verilog is unable to figure out the correct next state and it remains
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at x.<br>
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<br>
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This is a simulation only issue as flops in real silicon will always
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resolve to a valid state.<br>
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<br>
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Tool vendors created the sync_reset pragma so that you could tell the
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tool not to combine the reset logic with the mission mode logic. You
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place it at the very tip of the logic cone and it will remain there in
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gates.<br>
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<br>
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So whats wrong with that?<br>
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<br>
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The synthesis tool will make a list of all signals that enter the logic
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cone along with the relative time it enters before the next clock
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edge.&nbsp; If it finds a early arriving signal entering the cone
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closer to the tip than a late arriving one&nbsp; then it&nbsp; will try
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to remap the logic&nbsp;&nbsp; and swap them so that the late
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arrival&nbsp; can&nbsp;&nbsp; move closer to tip.&nbsp; Ideally the
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latest signals are moved towards the tip and the early ones are moved
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to the rear. <br>
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<br>
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The reset from a properly designed distribution tree and the feedback
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signal from the flop that you are working on will always be two of the
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earliest signals. They will get pushed up away from the tip of the cone
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simply to make room for the mission critical late signals. This is a
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good thing, you want this to happen. <br>
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<br>
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The problem is that designers think that they must prove that the reset
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system works in gate sims. Verilog is a great tool when every node is
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in a known state but it is lousy when dealing with unknowns. There are
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times like this when it is possible to resolve a X into a known
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value&nbsp; and it can't. There are also times when it will resolve an
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X to a known value when it shouldn't. The only way to use verilog is to
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start with everything in a known state and stop it when anything goes
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X.&nbsp; That means there's a problem and nothing downstream from that
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X
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can be trusted.<br>
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<br>
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<br>
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You do not prove your reset system design in gates sims. You prove the
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design in rtl sims and use LEC to prove that gates matches the design
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that works.&nbsp; Then you use initial statements to force all flops to
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a known state at start up and use gates sims to prove that everything
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else works. Verilog gates is the wrong tool to use to verify the reset
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system.<br>
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<br>
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You never use the sync_reset pragma unless you really like big slow
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designs.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">Doing a synchronous reset design adds logic in the
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D pathway and will slow down the design<br>
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</h3>
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<br>
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Wrong. Adding logic in the critical path will slow down the design.
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Adding it into a non-critical path simply reduces slack in that path.
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If you put the reset logic at the very tip of the logic cone then you
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are adding it into the critical path and the synthesis tool will move
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it up the cone&nbsp; until&nbsp; it is in a&nbsp; safe location.<br>
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<br>
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Adding a synchronous reset system doesn't really add much logic to the
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design. The tools will first locate any mission mode logic that also
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forces the flop into the reset state and it will piggyback the reset
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system with that logic. You don't add gates , you bump a gate up to add
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an extra input.<br>
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<br>
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<br>
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<br>
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<h3 class="western">A component must perform&nbsp; reset in one clock
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cycle<br>
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</h3>
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The power on reset is really a slow operation.&nbsp; A typical system
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could see:<br>
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<br>
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<ul>
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  <li>Ramp time for power rails</li>
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  <li>clock start up time</li>
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  <li>pll lock time</li>
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</ul>
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You are looking at activity that is measured in the milliseconds on a
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system clock that is measured in the nanoseconds. Performing a reset in
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one clock cycle&nbsp; requires adding logic to every single flipflop<br>
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to provide nanosecond resolution to an event that is measured in
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microseconds. A designer should only add reset logic as a last
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resort. The preferred method is to use the existing mission mode logic
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to perform the reset. If you have a computational block with a fifty
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stage deep pipeline then reset should force it's inputs to 0 and open
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all the gates so that every flipflop will be flushed out in 50 clocks.
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Better yet would be to have the block feeding your input force it's
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output to all 0's during reset.<br>
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<br>
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Every design should spec a multicycle reset and give the designers the
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freedom to reset any way they want as long as it's finished by the end
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of the reset pulse.<br>
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<br>
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<br>
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<br>
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<div id="toc__header" dir="ltr">
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<p><br>
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</p>
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</div>
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<h1><a name="socgen_project"></a>How to design the Reset System<br>
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</h1>
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<br>
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<br>
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<h3 class="western">1) Write a mission statement<br>
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</h3>
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The first step in any design task is to write a statement that sums up
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what the thing you are designing&nbsp; will do.&nbsp; This is important
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because everything after this point must be traceable back to this
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statement.&nbsp; The statement will&nbsp; tell you&nbsp; what&nbsp;
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steps you must follow. Anything that you cannot trace back to something
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in the mission statement is not part of the design<br>
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<br>
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<br>
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The mission statement for the reset system is:<br>
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<br>
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<br>
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<br>
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The reset system will force all the nodes in a system or subsystem into
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a known good state while&nbsp; a reset trigger is active.<br>
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<br>
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<br>
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<br>
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<h3 class="western">2) Define the reset triggers<br>
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</h3>
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We must now make a list of all the events that will cause us to reset
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all or part of the system. Our list is:<br>
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<br>
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<ul>
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  <li>The design has a power monitor chip that provides a low signal
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when the supply rails have&nbsp; not been above the limit for a long
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enough period of time</li>
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</ul>
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<ul>
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  <li>The design has a soft reset block that can reset any sub block if
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its reset flop is set to 1.</li>
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</ul>
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<ul>
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  <li>The clocks must run during reset but the divider has a special
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reset input for simulation and testing</li>
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</ul>
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<ul>
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  <li>The design has ieee 1149.1 test logic with a active low trst* pin.</li>
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</ul>
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<ul>
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  <li>The reset signal&nbsp; has a metastable filter to sync it with
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the clock.<br>
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  </li>
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</ul>
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The last is important because some designers will forget that the
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filtered output is actually it's own separate reset domain<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">3) Define a known good state<br>
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</h3>
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We&nbsp; now look at every storage element in the design and define a
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safe state for each&nbsp; element of either 1 or 0. Don't cares are not
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allowed. If you cannot pick a value then one will be assigned for you.
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This task is best performed after the system and board designers have
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defined the known good state for the PCA.&nbsp; They will define the
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state for all of the pads, the ic design team must define the states
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for all internal nodes.<br>
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<br>
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<h3 class="western">4) Assign storage elements to triggers<br>
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</h3>
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Once we have a list of all storage element we list any and all triggers
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that will force them into a safe mode.<br>
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A typical list would list all the flipflops in timer module u12.r567
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would be reset by:<br>
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<br>
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<ul>
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  <li>an active high on soft reset bit #23</li>
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</ul>
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<ul>
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  <li>an active low on the power monitor input</li>
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</ul>
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<ul>
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  <li>an active low on the simulation/test reset</li>
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</ul>
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<ul>
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  <li>an active low on the output of the metastable filter</li>
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</ul>
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<br>
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The jtag reset is not included because it doesn't reset the
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timer.&nbsp;
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Once this step is complete it will provide a map for the reset
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distribution tree that you will need. The best way to distribute the
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reset over a large design is to use what is called a "synchronous reset
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tree".<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">5) Select between synchronous or asynchronous reset
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system<br>
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</h3>
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At this point it is easy to see if we need a synchronous or
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asynchronous reset system. If your trigger is asynchronous then you
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must design a asynchronous reset system. If the trigger can occur
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without a clock then you must be able to reset the system without a
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clock.<br>
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<br>
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If the trigger is synchronous then you may design a synchronous reset
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system or you may also choose to design a asynchronous one.&nbsp; The
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async one will enter reset one&nbsp; cycle&nbsp; before the sync one
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but they will both exit on&nbsp; at the same&nbsp; time. <br>
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<br>
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<br>
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<br>
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<h3 class="western">6) Select reset style for each flip/flop<br>
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</h3>
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We now need to select a reset "Style" for each flip/flop from the four
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possible reset styles.<br>
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<br>
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<br>
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<ul>
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  <li>Synchronous</li>
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  <li>Synchronous with output override</li>
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  <li>Asynchronous</li>
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  <li>Both Synchronous and Asynchronous</li>
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</ul>
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<br>
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If the reset system is synchronous then you may choose any of the four
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styles. If it is asynchronous then you cannot use the synchronous style.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
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 src="../png/reset_fig1.png"><br>
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<br>
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<br>
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<br>
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<h3 class="western">7) Apply DFT fixes to all asynchronous ports<br>
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</h3>
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All paths from the Q output of a flip/flop to the asynchronous
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reset/preset port of a flip/flop must be disabled during scan testing.
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The use of a test mux to do this is not recommended because anytime you
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use a test mux you are not testing the circuit as it is used in mission
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mode. There will always be at least one point of failure inside the
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test mux where scan tests will pass but the IC will not function.<br>
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<br>
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The recommended method is to gate off the synchronous path with a atg
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test signal and then recombine it with an asynchronous reset so that
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the async reset it self is still testable. The lib module
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cde_asyncdisable is available for this purpose. DO NOT CREATE YOUR OWN
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TEST LOGIC.&nbsp; Checking the rtl code to ensure that all asynchronous
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resets are testable requires a fairly sophisticated and expensive tool.
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Checking the rtl to ensure that all asynchronous resets are properly
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connected to a cde_asyncdisable module takes a simple perl script.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
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 src="../png/reset_fig2.png"><br>
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<h3 class="western">8) Seperate Synchronous and&nbsp; Asynchronous
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resets<br>
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</h3>
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Asynchronous
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resets connect to the asynchronouse reset/preset ports of a flip/flop.
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Synchronous resets connect through the logic cone to the D flip/flop
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port. They are the logicaly the same signal in mission mode but must be
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sperate&nbsp; during scan testing. It is very easy to make a mistake in
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rtl coding.&nbsp; The recomendation is the use active low signals for
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all asynchronous resets and active high signals for all synchronous
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ones.<br>
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