| 1 |
2 |
jt_eaton |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
| 2 |
|
|
<HTML>
|
| 3 |
|
|
<HEAD>
|
| 4 |
|
|
<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
|
| 5 |
|
|
<TITLE>socgen project manifesto</TITLE>
|
| 6 |
|
|
<META NAME="GENERATOR" CONTENT="OpenOffice.org 3.0 (Linux)">
|
| 7 |
|
|
<META NAME="CREATED" CONTENT="0;0">
|
| 8 |
|
|
<META NAME="CHANGED" CONTENT="20100309;9291800">
|
| 9 |
|
|
<META NAME="KEYWORDS" CONTENT="manifesto">
|
| 10 |
|
|
<META NAME="Info 3" CONTENT="">
|
| 11 |
|
|
<META NAME="Info 4" CONTENT="">
|
| 12 |
|
|
<META NAME="date" CONTENT="2008-01-08T12:01:41-0500">
|
| 13 |
|
|
<META NAME="robots" CONTENT="index,follow">
|
| 14 |
|
|
</HEAD>
|
| 15 |
|
|
<BODY LANG="en-US" DIR="LTR">
|
| 16 |
|
|
<DIV ID="toc__header" DIR="LTR">
|
| 17 |
|
|
<P><BR><BR>
|
| 18 |
|
|
</P>
|
| 19 |
|
|
</DIV>
|
| 20 |
|
|
<H1><A NAME="socgen_project"></A>SOCGEN Project</H1>
|
| 21 |
|
|
<H2><A NAME="manifesto"></A>Manifesto</H2>
|
| 22 |
|
|
<P>The semiconductor industry is in the process of undergoing a
|
| 23 |
|
|
complete metamorphosis that will change forever the way digital
|
| 24 |
|
|
electronic products are designed. The last time this occurred was
|
| 25 |
|
|
back in the 1990's when schematic capture was a popular tool for
|
| 26 |
|
|
designing ICs. But designs grew to the point where you couldn't plop
|
| 27 |
|
|
down a gate and and connect it fast enough to create and verify a net
|
| 28 |
|
|
list in a reasonable amount of time. So schematic capture has been
|
| 29 |
|
|
replaced in all but the simplest designs with a HDL/SYNTHESIS flow.</P>
|
| 30 |
|
|
<P>That happened about 15 years ago and despite constant predictions
|
| 31 |
|
|
of the demise of Moore's Observation we now find ourselves back in
|
| 32 |
|
|
the same situation, You cannot type fast enough to create and verify
|
| 33 |
|
|
a net list in a reasonable amount of time.</P>
|
| 34 |
|
|
<P>The solution that is now emerging to meet this growing demand is
|
| 35 |
|
|
Design For Reuse(DFR). This methodology recognizes that the vast
|
| 36 |
|
|
majority of design work is simply a rehash of work that someone else
|
| 37 |
|
|
has already done. If you could reuse and leverage preexisting code
|
| 38 |
|
|
then the amount of new design work needed drops off dramatically.</P>
|
| 39 |
|
|
<P>The SOCGEN project was created to provide a free open-sourced
|
| 40 |
|
|
Design for Reuse tool set for asic and fpga developers. It will also
|
| 41 |
|
|
provide industry standard best practice guidelines that show how to
|
| 42 |
|
|
create a reusable design as well as a series of IP modules and
|
| 43 |
|
|
designs to demonstrate the proper way to make a design.</P>
|
| 44 |
|
|
<P>Everything in the SOCGEN project is released under GPL3 as free
|
| 45 |
|
|
and open source. SOCGEN will partner with other opensource or
|
| 46 |
|
|
free-to-use tools to form a complete embedded systems tool chain that
|
| 47 |
|
|
includes IC design, PCB design, Firmware development and real time
|
| 48 |
|
|
debugging.
|
| 49 |
|
|
</P>
|
| 50 |
|
|
<P><BR><BR>
|
| 51 |
|
|
</P>
|
| 52 |
|
|
<P><BR><BR>
|
| 53 |
|
|
</P>
|
| 54 |
|
|
<P><BR><BR>
|
| 55 |
|
|
</P>
|
| 56 |
|
|
<P><BR><BR>
|
| 57 |
|
|
</P>
|
| 58 |
|
|
<P><BR><BR>
|
| 59 |
|
|
</P>
|
| 60 |
|
|
<P><BR><BR>
|
| 61 |
|
|
</P>
|
| 62 |
|
|
<P><BR><BR>
|
| 63 |
|
|
</P>
|
| 64 |
|
|
<H2><A NAME="guidelines"></A>Why am I doing this?</H2>
|
| 65 |
|
|
<P>Theres an old saying that everyone has at least one good novel in
|
| 66 |
|
|
them. For an engineer it's at least one good open source project. I
|
| 67 |
|
|
spent my career as a electrical engineer working for Hewlett-Packard.
|
| 68 |
|
|
Nothing in my years in R+D could prepare me for what we had to do to
|
| 69 |
|
|
create deep submicron asic designs. The chip sizes and complexities
|
| 70 |
|
|
grew every year and it was a struggle to keep up with all the new
|
| 71 |
|
|
processes. But I had spent several years working as a production
|
| 72 |
|
|
engineer mostly bringing new products up the production ramp and the
|
| 73 |
|
|
techniques used in manufacturing were exactly what were needed to
|
| 74 |
|
|
design DeepSubMicron asics.</P>
|
| 75 |
|
|
<P>R+D engineers tend to work like ye olde Yankee craftsmen. They go
|
| 76 |
|
|
into their shops and spend a lot of time handcrafting a design and it
|
| 77 |
|
|
is beautiful when finished. But it also takes a lot of time and the
|
| 78 |
|
|
demand is such that you will soon need every adult male in New
|
| 79 |
|
|
England working in the shops to meet production quotas. It's time to
|
| 80 |
|
|
part with the traditional ways and create a high volume manufacturing
|
| 81 |
|
|
line for asics.That is the goal of Design for Reuse.</P>
|
| 82 |
|
|
<P>I was fortunate to work at HP in a design group that was doing
|
| 83 |
|
|
bleeding edge development of design for reuse techniques. The Inkjet
|
| 84 |
|
|
Peripheral group had a IC design team that spanned four divisions and
|
| 85 |
|
|
a support operation. We did 2-4 asic designs a year and did this year
|
| 86 |
|
|
after year after year. We designed families of chips doing one for
|
| 87 |
|
|
low-end, high volume , one for high end, high performance and if the
|
| 88 |
|
|
vintage chart called for it , one in the middle.</P>
|
| 89 |
|
|
<P>We designed platform asics. There were to many products to do one
|
| 90 |
|
|
chip per product so the chip that went into an All-In_One printer
|
| 91 |
|
|
scanner could also go into a Photo printer or a stand alone printer.
|
| 92 |
|
|
The extra silicon needed to support unused functions was nothing
|
| 93 |
|
|
compared to the cost savings from combining product volumes into a
|
| 94 |
|
|
single part. Pin's on the other hand were precious. The pins needed
|
| 95 |
|
|
to drive the scanner interface were multiplexed with the Photo card
|
| 96 |
|
|
pins as well as GPIO pins. The code would configure the chip for
|
| 97 |
|
|
whatever product it happened to find itself in.</P>
|
| 98 |
|
|
<P>We also did multi-Vendor designs. Our volumes were to high to only
|
| 99 |
|
|
have a single source. Plus we wanted the pricing that came from
|
| 100 |
|
|
having multiple sources. One year we did a family of three asics with
|
| 101 |
|
|
three different vendors plus a fourth chip that was the low end
|
| 102 |
|
|
design second sourced from two of the vendors. On top of all this we
|
| 103 |
|
|
breadboarded all three designs in a FPGA system.</P>
|
| 104 |
|
|
<P>I learned a lot about how to share and reuse IP and delivering a
|
| 105 |
|
|
working net list on schedule. We were well ahead of the rest of the
|
| 106 |
|
|
industry.</P>
|
| 107 |
|
|
<P>The recession ended my career after 28 years and 10 months. I was
|
| 108 |
|
|
57 and trying to figure out what I wanted to do now that I had grown
|
| 109 |
|
|
up. When I started my career an asic mask set cost about $50,000. At
|
| 110 |
|
|
the end of it they were quoting about $1,200,000. Asic design starts
|
| 111 |
|
|
had been dropping year over year even before the recession. Fewer and
|
| 112 |
|
|
fewer companies could afford to do asics. Staying with asics meant
|
| 113 |
|
|
moving.</P>
|
| 114 |
|
|
<P>FPGA's one the other and were booming. Larger chips were opening
|
| 115 |
|
|
up new areas where fpga only products were feasible and becoming more
|
| 116 |
|
|
common. I also could see that FPGAs were following the same growth
|
| 117 |
|
|
curve that asics took 20 years ago and that fpga designers were
|
| 118 |
|
|
making the same tool mistakes that asic designers made. Some fpga
|
| 119 |
|
|
designers still use schematic capture.</P>
|
| 120 |
|
|
<P>This became my mission. To create the tool set needed to generate
|
| 121 |
|
|
System_on_Chip net lists for FPGA and asic designers. I know there
|
| 122 |
|
|
are a lot of big guns in the EDA industry also trying to do this but
|
| 123 |
|
|
I have some advantages. First of all I'm not in it for the money. The
|
| 124 |
|
|
tools that I have tried out all have to squeeze in enough features to
|
| 125 |
|
|
justify their price tags. They become bloated. Design for Reuse is
|
| 126 |
|
|
not a complicated problem. The tool that we used at HP to preform
|
| 127 |
|
|
most of the work was a simple macro preprocessor module that we
|
| 128 |
|
|
downloaded from CPAN.
|
| 129 |
|
|
</P>
|
| 130 |
|
|
<P>Second of all ,most of the commercial design for reuse tools
|
| 131 |
|
|
didn't work. I would sit through the dog and pony shows telling me
|
| 132 |
|
|
how these tools would do the job. Then we would start telling them
|
| 133 |
|
|
about our design environment and their eyes would start glazing over.
|
| 134 |
|
|
Their tools work fine if you have one design team in one location
|
| 135 |
|
|
doing one chip with one vendor but anything beyond that is iffy.</P>
|
| 136 |
|
|
<P>Last of all they were addressing the wrong problem. They were
|
| 137 |
|
|
trying to reuse IP that was never designed to be reused. That hard.
|
| 138 |
|
|
SOCGEN tells you how to design IP so that it is reusable. That makes
|
| 139 |
|
|
a big difference.</P>
|
| 140 |
|
|
<P>SOCGEN is a living project. I will be adding to it on a continuous
|
| 141 |
|
|
basis from here on out. My legal constraints with HP have ended so I
|
| 142 |
|
|
am sole owner of all the work that I create. I will not be adding any
|
| 143 |
|
|
code here that was developed at HP. I now realize that we made a
|
| 144 |
|
|
fundamental mistake in our tool set. We started by creating stand
|
| 145 |
|
|
alone tools that ran under gmake and started working from the fringes
|
| 146 |
|
|
of the design into the core. That was wrong. We should have started
|
| 147 |
|
|
at the core and worked our way out to the fringes. The first SOCGEN
|
| 148 |
|
|
tools will take that approach.</P>
|
| 149 |
|
|
<P>SOCGEN will also partner with and use other open source EDA tools
|
| 150 |
|
|
when convenient. gEDA has a well developed PCB design flow and I
|
| 151 |
|
|
intend to use gschem as part of my tool flow to feed parts to the
|
| 152 |
|
|
PCB. Schematic capture is a useful tool. It's just that you do not
|
| 153 |
|
|
want to be plopping down gates and connecting wires. You want to be
|
| 154 |
|
|
plopping down components and connecting interfaces.
|
| 155 |
|
|
</P>
|
| 156 |
|
|
<P>Till Later</P>
|
| 157 |
|
|
<P><BR><BR>
|
| 158 |
|
|
</P>
|
| 159 |
|
|
<P>John Eaton</P>
|
| 160 |
|
|
<P><BR><BR>
|
| 161 |
|
|
</P>
|
| 162 |
|
|
<P><BR><BR>
|
| 163 |
|
|
</P>
|
| 164 |
|
|
</BODY>
|
| 165 |
|
|
</HTML>
|
