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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<title>socgen_prj_description</title>
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<meta name="CHANGED" content="20100309;9110600">
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<meta name="CLASSIFICATION" content="socgen project description">
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<meta name="DESCRIPTION"
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content="socgen is a laboratory for the development of a opensource design for reuse toolset">
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<meta name="KEYWORDS" content="eda design for reuse opensource tools">
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<meta name="Info 3" content="">
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<meta name="date" content="2010-01-08T12:01:41-0500">
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<body dir="LTR" lang="en-US">
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<div id="toc__header" dir="LTR">
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<p><br>
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</p>
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</div>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h2>Design for Reuse</h2>
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<p>The SOCGEN project is a laboratory for developing and
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demonstrating the methods and processes needed to create and reuse
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digital components. The goal of the project is to create a open
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source set of eda tools that will enable a designer to configure and
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assemble a complete System_on_a_chip (SOC) in a quick, easy and error
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free manner.</p>
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<p>I am hosting this project on Opencores due to the availability of
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free opensourced ip modules and a user community that is in dire need
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of a good design for reuse solution. I will be taking various
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opencores modules and reworking them into the socgen repository.
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Design for reuse is all about efficiency. Any code can be reused if
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you devote enough time and energy to it but paying attention to the
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details can make a huge difference in how easy it is to reuse a
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module. Any one is welcome to use these versions of the modules and
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the scripts that I am creating. Feedback is always welcome.</p>
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<p>The entire industry is about to experience a change in the way
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that chips are designed that will be as dramatic as it was back in
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the early 90's. Before that point the most common tool for design
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entry was schematic capture. But designs had grown to the point where
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that was far to inefficient and it was replaced with a rtl to
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synthesis process.</p>
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<p>That happened 20 years ago and chips have continued to grow to the
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point where you can no longer design and verify the rtl code in a
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reasonable time. </p>
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<p>My approach to this problem is to introduce modern hi volume
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production line theory into the IC design process. The designs are
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too complex to simply get a group together and hand craft rtl code.
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Socgen will develop the tools and processes needed to assemble cores
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together in quick and predictable manner.</p>
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<p> </p>
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<p>A good deal of this effort involves understanding database design
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and usage. Most designers simply construct their databases based
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only on their immediate and past needs. Socgen will provide a
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repository of various projects that have been converted to show how
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small changes in where you store files can make a big difference in
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how easily those files can be reused.</p>
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<p><br>
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<br>
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</p>
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<p>All socgen tools and components are released under LGPL. Any other
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opencores projects used in the repository will retain their original
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license.</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<h2>Definitions<br>
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</h2>
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<p>COMPONENT The basic design building block<br>
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</p>
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<p>LIBRARY<br>
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</p>
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<p>TARGET<br>
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</p>
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<p>COLLECTOR<br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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<br>
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</p>
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<p><br>
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</p>
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<p><br>
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<br>
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</p>
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<p>Socgen will provide:</p>
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<ol>
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<li>
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<p>Installation instructions for any and all external tools needed</p>
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</li>
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<li>
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<p>Proper data base design and management tools and techniques</p>
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</li>
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<li>
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<p>Proper design verification</p>
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</li>
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<li>
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<p>All modules will be proven in silicon</p>
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</li>
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</ol>
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<p><br>
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<br>
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</p>
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<p>Socgen is a work in process so expect to see frequent changes. All
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socgen tools are run under Makefiles and I will try to keep the top
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level commands constant.</p>
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<p><br>
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<br>
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</p>
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<p>Till Later</p>
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<br>
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</p>
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<p>John Eaton</p>
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</body>
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