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[/] [socgen/] [trunk/] [tools/] [bin/] [ver2gedasch] - Blame information for rev 128

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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;
 
#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*  convert verilog file(s)ports  to a geda schematic                 */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010>                     */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/
 
#  ToDo:
#  parse reg from output bus name
#  parse bus and change pin type to bus
 
use Verilog::Netlist;
 
# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
                    "-y","verilog",
               );
 
 
@files            = @ARGV;
 
 
# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
 
foreach $file (@files) {
                        print "Parsing   $file\n";
                        $nl->read_file (filename=>$file);
}
 
 
 
 
 
 
 
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();
 
 
foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
 
 
 
sub make_sch {
        my $mod = shift;
        my $mod_name  = $mod->name;
 
        my $in_count   = 0;
        my $out_count  = 0;
        my $in_length  = 0;
        my $out_length = 0;
 
        my $color =  5;
        my $size  = 10;
 
 
        open(FILE,">sch/${mod_name}.sch") or die "No sch directory";
 
        foreach my $sig ($mod->ports_sorted) {
 
            my $dir       =  $sig->direction;
            my $data_type =  $sig->data_type;
            my $sig_name  =  $sig->name;
            $data_type  =~ s/reg //;
            $data_type  =~ s/reg//;
 
 
 
 
 
 
            if($data_type)
              {
              $pin_name = "$sig_name"."$data_type";
              if("in" eq  $dir)
                {
                push(@invads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length) { $in_length =  length($pin_name)};
                }
              if("out" eq  $dir)
                {
                push(@outvads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
              if("inout" eq  $dir)
                {
                push(@inoutvads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
 
              }
            else
              {
              $pin_name = $sig_name;
              if("in" eq  $dir)
                {
                push(@inpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
              if("out" eq  $dir)
                {
                push(@outpads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
              if("inout" eq  $dir)
                {
                push(@inoutpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
              }
 
 
           };
 
 
        }
 
        my $max_pins;
 
        if($in_count > $out_count) {$max_pins = $in_count ;} else  {$max_pins = $out_count ;}
 
        my $in_edg  = ($in_length)*10*$size +200;
        my $in_pad  = ($in_length)*10*$size +200;
        my $out_edg = ($in_length +$out_length)*10*$size +2500;
        my $out_pad = ($in_length +$out_length)*10*$size +1500;
 
        printf FILE ("v 20100214 1\n");
 
        printf  ("%s\n", $mod->name);
 
         my $pin_y = 300;
 
         while( $name =pop(@invads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 in_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@inpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 in_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
         while( $name =pop(@inoutvads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 io_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@inoutpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 io_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
 
         $pin_y = 300;
 
         while( $name =pop(@outvads))
          {
           printf FILE ("C $out_pad $pin_y  1 0  0 out_port_v.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@outpads))
          {
           printf FILE ("C $out_pad $pin_y  1 0 0 out_port.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
 
 
 
        foreach my $cell ($mod->cells_sorted) {
            close(FILE);
            make_sch ($cell->submod, $cell->name) if $cell->submod;
        }
    }
 
 
 
 
 
 
 
1;
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] [ver2gedasch] - Blame information for rev 128

Line No.	Rev	Author	Line
1	20	jt_eaton	eval 'exec `which perl` -S $0 ${1+"$@"}'
2			`if 0;`
3
4			`#/**********************************************************************/`
5			`#/* */`
6			`#/* ------- */`
7			`#/* / SOC \ */`
8			`#/* / GEN \ */`
9			`#/* / TOOL \ */`
10			`#/* ============== */`
11			`#/* \| \| */`
12			`#/* \|____________\| */`
13			`#/* */`
14			`#/* convert verilog file(s)ports to a geda schematic */`
15			`#/* */`
16			`#/* */`
17			`#/* Author(s): */`
18			`#/* - John Eaton, jt_eaton@opencores.org */`
19			`#/* */`
20			`#/**********************************************************************/`
21			`#/* */`
22			`#/* Copyright (C) <2010> */`
23			`#/* */`
24			`#/* This source file may be used and distributed without */`
25			`#/* restriction provided that this copyright statement is not */`
26			`#/* removed from the file and that any derivative work contains */`
27			`#/* the original copyright notice and the associated disclaimer. */`
28			`#/* */`
29			`#/* This source file is free software; you can redistribute it */`
30			`#/* and/or modify it under the terms of the GNU Lesser General */`
31			`#/* Public License as published by the Free Software Foundation; */`
32			`#/* either version 2.1 of the License, or (at your option) any */`
33			`#/* later version. */`
34			`#/* */`
35			`#/* This source is distributed in the hope that it will be */`
36			`#/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
37			`#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
38			`#/* PURPOSE. See the GNU Lesser General Public License for more */`
39			`#/* details. */`
40			`#/* */`
41			`#/* You should have received a copy of the GNU Lesser General */`
42			`#/* Public License along with this source; if not, download it */`
43			`#/* from http://www.opencores.org/lgpl.shtml */`
44			`#/* */`
45			`#/**********************************************************************/`
46
47			`# ToDo:`
48			`# parse reg from output bus name`
49			`# parse bus and change pin type to bus`
50
51			`use Verilog::Netlist;`
52
53			`# Setup options so files can be found`
54			`use Verilog::Getopt;`
55			`my $opt = new Verilog::Getopt;`
56			`$opt->parameter( "+incdir+verilog",`
57			`"-y","verilog",`
58			`);`
59
60
61			`@files = @ARGV;`
62
63
64			`# Prepare netlist`
65			`my $nl = new Verilog::Netlist (options => $opt,);`
66
67			`foreach $file (@files) {`
68			`print "Parsing $file\n";`
69			`$nl->read_file (filename=>$file);`
70			`}`
71
72
73
74
75
76
77
78			`# Read in any sub-modules`
79			`$nl->link();`
80			`$nl->exit_if_error();`
81
82
83			`foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}`
84
85
86
87			`sub make_sch {`
88			`my $mod = shift;`
89			`my $mod_name = $mod->name;`
90
91			`my $in_count = 0;`
92			`my $out_count = 0;`
93			`my $in_length = 0;`
94			`my $out_length = 0;`
95
96			`my $color = 5;`
97			`my $size = 10;`
98
99
100			`open(FILE,">sch/${mod_name}.sch") or die "No sch directory";`
101
102			`foreach my $sig ($mod->ports_sorted) {`
103
104			`my $dir = $sig->direction;`
105			`my $data_type = $sig->data_type;`
106			`my $sig_name = $sig->name;`
107			`$data_type =~ s/reg //;`
108			`$data_type =~ s/reg//;`
109
110
111
112
113
114
115			`if($data_type)`
116			`{`
117			`$pin_name = "$sig_name"."$data_type";`
118			`if("in" eq $dir)`
119			`{`
120			`push(@invads,$pin_name);`
121			`$in_count = $in_count+1;`
122			`if( length($pin_name) > $in_length) { $in_length = length($pin_name)};`
123			`}`
124			`if("out" eq $dir)`
125			`{`
126			`push(@outvads,$pin_name);`
127			`$out_count = $out_count+1;`
128			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
129			`}`
130			`if("inout" eq $dir)`
131			`{`
132			`push(@inoutvads,$pin_name);`
133			`$in_count = $in_count+1;`
134			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
135			`}`
136
137			`}`
138			`else`
139			`{`
140			`$pin_name = $sig_name;`
141			`if("in" eq $dir)`
142			`{`
143			`push(@inpads,$pin_name);`
144			`$in_count = $in_count+1;`
145			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
146			`}`
147			`if("out" eq $dir)`
148			`{`
149			`push(@outpads,$pin_name);`
150			`$out_count = $out_count+1;`
151			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
152			`}`
153
154			`if("inout" eq $dir)`
155			`{`
156			`push(@inoutpads,$pin_name);`
157			`$in_count = $in_count+1;`
158			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
159			`}`
160
161
162			`};`
163
164
165			`}`
166
167			`my $max_pins;`
168
169			`if($in_count > $out_count) {$max_pins = $in_count ;} else {$max_pins = $out_count ;}`
170
171			`my $in_edg = ($in_length)10$size +200;`
172			`my $in_pad = ($in_length)10$size +200;`
173			`my $out_edg = ($in_length +$out_length)10$size +2500;`
174			`my $out_pad = ($in_length +$out_length)10$size +1500;`
175
176			`printf FILE ("v 20100214 1\n");`
177
178			`printf ("%s\n", $mod->name);`
179
180			`my $pin_y = 300;`
181
182			`while( $name =pop(@invads))`
183			`{`
184			`printf FILE ("C $in_pad $pin_y 1 0 0 in_port_v.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);`
185			`$pin_y = $pin_y +400;`
186			`}`
187
188
189			`while( $name =pop(@inpads))`
190			`{`
191			`printf FILE ("C $in_pad $pin_y 1 0 0 in_port.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);`
192			`$pin_y = $pin_y +400;`
193			`}`
194
195
196
197			`while( $name =pop(@inoutvads))`
198			`{`
199			`printf FILE ("C $in_pad $pin_y 1 0 0 io_port_v.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);`
200			`$pin_y = $pin_y +400;`
201			`}`
202
203
204			`while( $name =pop(@inoutpads))`
205			`{`
206			`printf FILE ("C $in_pad $pin_y 1 0 0 io_port.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);`
207			`$pin_y = $pin_y +400;`
208			`}`
209
210
211
212
213			`$pin_y = 300;`
214
215			`while( $name =pop(@outvads))`
216			`{`
217			`printf FILE ("C $out_pad $pin_y 1 0 0 out_port_v.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);`
218			`$pin_y = $pin_y +400;`
219			`}`
220
221
222			`while( $name =pop(@outpads))`
223			`{`
224			`printf FILE ("C $out_pad $pin_y 1 0 0 out_port.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);`
225			`$pin_y = $pin_y +400;`
226			`}`
227
228
229
230
231
232
233			`foreach my $cell ($mod->cells_sorted) {`
234			`close(FILE);`
235			`make_sch ($cell->submod, $cell->name) if $cell->submod;`
236			`}`
237			`}`
238
239
240
241
242
243
244
245			`1;`
246
247
248
249
250
251
252