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[/] [socgen/] [trunk/] [tools/] [bin/] [ver2gedasym] - Blame information for rev 114

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Line No. Rev Author Line
1 20 jt_eaton
eval 'exec `which perl` -S $0 ${1+"$@"}'
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   if 0;
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#/**********************************************************************/
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#/*                                                                    */
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#/*             -------                                                */
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#/*            /   SOC  \                                              */
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#/*           /    GEN   \                                             */
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#/*          /    TOOL    \                                            */
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#/*          ==============                                            */
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#/*          |            |                                            */
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#/*          |____________|                                            */
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#/*                                                                    */
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#/*  convert verilog file(s) to a geda symbol                          */
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#/*                                                                    */
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#/*                                                                    */
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#/*  Author(s):                                                        */
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#/*      - John Eaton, jt_eaton@opencores.org                          */
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#/*                                                                    */
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#/**********************************************************************/
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#/*                                                                    */
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#/*    Copyright (C) <2010>                     */
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#/*                                                                    */
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#/*  This source file may be used and distributed without              */
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#/*  restriction provided that this copyright statement is not         */
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#/*  removed from the file and that any derivative work contains       */
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#/*  the original copyright notice and the associated disclaimer.      */
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#/*                                                                    */
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#/*  This source file is free software; you can redistribute it        */
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#/*  and/or modify it under the terms of the GNU Lesser General        */
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#/*  Public License as published by the Free Software Foundation;      */
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#/*  either version 2.1 of the License, or (at your option) any        */
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#/*  later version.                                                    */
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#/*                                                                    */
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#/*  This source is distributed in the hope that it will be            */
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#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
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#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
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#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
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#/*  details.                                                          */
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#/*                                                                    */
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#/*  You should have received a copy of the GNU Lesser General         */
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#/*  Public License along with this source; if not, download it        */
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#/*  from http://www.opencores.org/lgpl.shtml                          */
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#/*                                                                    */
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#/**********************************************************************/
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#  ToDo:
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#  parse reg from output bus name
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#  parse bus and change pin type to bus
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use Verilog::Netlist;
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# Setup options so files can be found
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use Verilog::Getopt;
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my $opt = new Verilog::Getopt;
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$opt->parameter( "+incdir+verilog",
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                    "-y","verilog",
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               );
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@files            = @ARGV;
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# Prepare netlist
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my $nl = new Verilog::Netlist (options => $opt,);
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foreach $file (@files) {
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                        print "Parsing   $file\n";
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                        $nl->read_file (filename=>$file);
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}
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# Read in any sub-modules
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$nl->link();
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$nl->exit_if_error();
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foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
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sub make_sch {
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        my $mod = shift;
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        my $mod_name  = $mod->name;
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        my $in_count   = 0;
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        my $out_count  = 0;
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        my $in_length  = 0;
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        my $out_length = 0;
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        my $color =  5;
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        my $size  = 10;
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        open(FILE,">sym/${mod_name}.sym") or die "No sym directory";
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        foreach my $sig ($mod->ports_sorted) {
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            my $dir       =  $sig->direction;
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            my $data_type =  $sig->data_type;
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            my $sig_name  =  $sig->name;
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            $data_type  =~ s/reg //;
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            $data_type  =~ s/reg//;
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            if($data_type)
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              {
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              $pin_name = "$sig_name"."$data_type";
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              if("in" eq  $dir)
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                {
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                push(@invads,$pin_name);
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                $in_count = $in_count+1;
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                if( length($pin_name) > $in_length) { $in_length =  length($pin_name)};
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                }
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              if("out" eq  $dir)
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                {
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                push(@outvads,$pin_name);
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                $out_count = $out_count+1;
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                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
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                }
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              if("inout" eq  $dir)
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                {
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                push(@inoutvads,$pin_name);
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                $out_count = $out_count+1;
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                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
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                }
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              }
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            else
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              {
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              $pin_name = $sig_name;
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              if("in" eq  $dir)
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                {
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                push(@inpads,$pin_name);
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                $in_count = $in_count+1;
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                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
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                }
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              if("out" eq  $dir)
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                {
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                push(@outpads,$pin_name);
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                $out_count = $out_count+1;
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                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
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                }
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              if("inout" eq  $dir)
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                {
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                push(@inoutpads,$pin_name);
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                $out_count = $out_count+1;
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                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
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                }
159
 
160
              };
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        }
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        my $max_pins;
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        if($in_count > $out_count) {$max_pins = $in_count ;} else  {$max_pins = $out_count ;}
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        my $box_h   = ($max_pins * 200) +300;
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        my $box_w   = ($in_length +$out_length)*10*$size +400;
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        my $out_title = ($in_length +$out_length)*10*$size +600;
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        my $out_edg = ($in_length +$out_length)*10*$size +700;
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        my $out_pad = ($in_length +$out_length)*10*$size +1000;
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        my $title   = $box_h +150;
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        my $ref_des = $box_h +350;
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        printf FILE ("v 20100214 1\n");
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        printf FILE ("B 300 0  $box_w $box_h 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1\n");
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        printf FILE ("T 400 $title 5 10 1 1 0 0 1 1\ndevice=%s\n", $mod->name);
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        printf FILE ("T 400 $ref_des 8 10 1 1 0 0 1 1\n%srefdes=U?\n");
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        printf  ("%s\n", $mod->name);
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         my $pin_y = 200;
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         my $pin_seq = 1;
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         while( $name =pop(@invads))
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          {
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          printf FILE ("P 300 $pin_y 0 $pin_y 10 1 1 \n");
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          printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1\npinnumber=%s\n",$name);
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          printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1\npinseq=%s\n}\n",$pin_seq);
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          $pin_seq = $pin_seq +1;
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          $pin_y = $pin_y +200;
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          }
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         while( $name =pop(@inpads))
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          {
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           printf FILE ("P 300 $pin_y 0 $pin_y 4 0 1  \n");
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           printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1 \npinnumber=%s\n",$name);
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           printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1 \npinseq=%s\n}\n",$pin_seq);
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           $pin_seq = $pin_seq +1;
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           $pin_y = $pin_y +200;
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          }
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         $pin_y = 200;
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         while( $name =pop(@outvads))
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          {
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           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
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           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
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           printf FILE ("T $out_title $pin_y $color  $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
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           $pin_seq = $pin_seq +1;
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           $pin_y = $pin_y +200;
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          }
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         while( $name =pop(@outpads))
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          {
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           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
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           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
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           printf FILE ("T $out_edg $pin_y $color  $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
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           $pin_seq = $pin_seq +1;
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           $pin_y = $pin_y +200;
228
          }
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230
 
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         while( $name =pop(@inoutvads))
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          {
235
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
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           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
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           printf FILE ("T $out_title $pin_y $color  $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
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           $pin_seq = $pin_seq +1;
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           $pin_y = $pin_y +200;
240
          }
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243
         while( $name =pop(@inoutpads))
244
          {
245
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
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           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
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           printf FILE ("T $out_edg $pin_y $color  $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
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           $pin_seq = $pin_seq +1;
249
           $pin_y = $pin_y +200;
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          }
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259
        foreach my $cell ($mod->cells_sorted) {
260
            close(FILE);
261
            make_sch ($cell->submod, $cell->name) if $cell->submod;
262
        }
263
    }
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1;
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