Subversion Repositories socgen

eval 'exec `which perl` -S $0 ${1+"$@"}'

   if 0;

#/**********************************************************************/

#/*                                                                    */

#/*             -------                                                */

#/*            /   SOC  \                                              */

#/*           /    GEN   \                                             */

#/*          /    TOOL    \                                            */

#/*          ==============                                            */

#/*          |            |                                            */

#/*          |____________|                                            */

#/*                                                                    */

#/*  convert verilog file(s) to a geda symbol                          */

#/*                                                                    */

#/*                                                                    */

#/*  Author(s):                                                        */

#/*      - John Eaton, jt_eaton@opencores.org                          */

#/*                                                                    */

#/**********************************************************************/

#/*                                                                    */

#/*    Copyright (C) <2010>                     */

#/*                                                                    */

#/*  This source file may be used and distributed without              */

#/*  restriction provided that this copyright statement is not         */

#/*  removed from the file and that any derivative work contains       */

#/*  the original copyright notice and the associated disclaimer.      */

#/*                                                                    */

#/*  This source file is free software; you can redistribute it        */

#/*  and/or modify it under the terms of the GNU Lesser General        */

#/*  Public License as published by the Free Software Foundation;      */

#/*  either version 2.1 of the License, or (at your option) any        */

#/*  later version.                                                    */

#/*                                                                    */

#/*  This source is distributed in the hope that it will be            */

#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */

#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */

#/*  PURPOSE.  See the GNU Lesser General Public License for more      */

#/*  details.                                                          */

#/*                                                                    */

#/*  You should have received a copy of the GNU Lesser General         */

#/*  Public License along with this source; if not, download it        */

#/*  from http://www.opencores.org/lgpl.shtml                          */

#/*                                                                    */

#/**********************************************************************/

#  ToDo:

#  parse reg from output bus name

#  parse bus and change pin type to bus

use Verilog::Netlist;

# Setup options so files can be found

use Verilog::Getopt;

my $opt = new Verilog::Getopt;

$opt->parameter( "+incdir+verilog",

                    "-y","verilog",

               );

@files            = @ARGV;

# Prepare netlist

my $nl = new Verilog::Netlist (options => $opt,);

foreach $file (@files) {

                        print "Parsing   $file\n";

                        $nl->read_file (filename=>$file);

}

# Read in any sub-modules

$nl->link();

$nl->exit_if_error();

foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}

sub make_sch {

        my $mod = shift;

        my $mod_name  = $mod->name;

        open(FILE,">xml/${mod_name}.xml") or die "No sym directory";

          printf FILE ("\n");

        foreach my $sig ($mod->ports_sorted) {

            my $dir       =  $sig->direction;

            my $data_type =  $sig->data_type;

            my $sig_name  =  $sig->name;

            $data_type  =~ s/reg //;

            $data_type  =~ s/reg//;

          printf FILE ("\n  %sput\n",$dir);

            if($data_type)

              {

              printf FILE ("  %s\n",$data_type);

              $pin_name = "$sig_name"."$data_type";

              }

          printf FILE ("  %s\n\n\n",$sig_name);

        }

          printf FILE ("\n");

        foreach my $cell ($mod->cells_sorted) {

            close(FILE);

            make_sch ($cell->submod, $cell->name) if $cell->submod;

        }

    }

1;