URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [documentation/] [ver2gedasch] - Blame information for rev 135

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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;
#/****************************************************************************/
#/*                                                                          */
#/*   SOCGEN Design for Reuse toolset                                        */
#/*                                                                          */
#/*   Version 1.0.0                                                          */
#/*                                                                          */
#/*   Author(s):                                                             */
#/*      - John Eaton, z3qmtr45@gmail.com                                    */
#/*                                                                          */
#/****************************************************************************/
#/*                                                                          */
#/*                                                                          */
#/*             Copyright 2016 John T Eaton                                  */
#/*                                                                          */
#/* Licensed under the Apache License, Version 2.0 (the "License");          */
#/* you may not use this file except in compliance with the License.         */
#/* You may obtain a copy of the License at                                  */
#/*                                                                          */
#/*    http://www.apache.org/licenses/LICENSE-2.0                            */
#/*                                                                          */
#/* Unless required by applicable law or agreed to in writing, software      */
#/* distributed under the License is distributed on an "AS IS" BASIS,        */
#/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */
#/* See the License for the specific language governing permissions and      */
#/* limitations under the License.                                           */
#/*                                                                          */
#/*                                                                          */
#/****************************************************************************/
 
 
#  ToDo:
#  parse reg from output bus name
#  parse bus and change pin type to bus
 
use Verilog::Netlist;
 
# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
                    "-y","verilog",
               );
 
 
 
 
my @files            = ();
 
$SRCFILE            = @ARGV[0];
$outfile            = @ARGV[1];
 
 
 
 
             push @files,  "$SRCFILE";
 
 
 
 
 
 
# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
 
 
 
 
 
 
foreach $file (@files) {
                        print "Parsing   $file\n";
                        $nl->read_file (filename=>$file);
}
 
 
 
 
 
 
 
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();
 
 
foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
 
 
 
sub make_sch {
        my $mod = shift;
        my $mod_name  = $mod->name;
 
        my $in_count   = 0;
        my $out_count  = 0;
        my $in_length  = 0;
        my $out_length = 0;
 
        my $color =  5;
        my $size  = 10;
 
 
        open(FILE,">${outfile}${mod_name}.sch") or die "No sch directory";
 
        foreach my $sig ($mod->ports_sorted) {
 
            my $dir       =  $sig->direction;
            my $data_type =  $sig->data_type;
            my $sig_name  =  $sig->name;
            $data_type  =~ s/reg //;
            $data_type  =~ s/reg//;
 
 
 
 
 
 
            if($data_type)
              {
              $pin_name = "$sig_name"."$data_type";
              if("in" eq  $dir)
                {
                push(@invads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length) { $in_length =  length($pin_name)};
                }
              if("out" eq  $dir)
                {
                push(@outvads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
              if("inout" eq  $dir)
                {
                push(@inoutvads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
 
              }
            else
              {
              $pin_name = $sig_name;
              if("in" eq  $dir)
                {
                push(@inpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
              if("out" eq  $dir)
                {
                push(@outpads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
              if("inout" eq  $dir)
                {
                push(@inoutpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
              }
 
 
           };
 
 
        }
 
        my $max_pins;
 
        if($in_count > $out_count) {$max_pins = $in_count ;} else  {$max_pins = $out_count ;}
 
        my $in_edg  = ($in_length)*10*$size +200;
        my $in_pad  = ($in_length)*10*$size +200;
        my $out_edg = ($in_length +$out_length)*10*$size +2500;
        my $out_pad = ($in_length +$out_length)*10*$size +1500;
 
        printf FILE ("v 20100214 1\n");
 
        printf  ("%s\n", $mod->name);
 
         my $pin_y = 300;
 
         while( $name =pop(@invads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 in_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@inpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 in_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
         while( $name =pop(@inoutvads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 io_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@inoutpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 io_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
 
         $pin_y = 300;
 
         while( $name =pop(@outvads))
          {
           printf FILE ("C $out_pad $pin_y  1 0  0 out_port_v.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
         while( $name =pop(@outpads))
          {
           printf FILE ("C $out_pad $pin_y  1 0 0 out_port.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }
 
 
 
 
 
 
        foreach my $cell ($mod->cells_sorted) {
            close(FILE);
            make_sch ($cell->submod, $cell->name) if $cell->submod;
        }
    }
 
 
 
 
 
 
 
1;
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [documentation/] [ver2gedasch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	128	jt_eaton	eval 'exec `which perl` -S $0 ${1+"$@"}'
2			`if 0;`
3	135	jt_eaton	`#/****************************************************************************/`
4			`#/* */`
5			`#/* SOCGEN Design for Reuse toolset */`
6			`#/* */`
7			`#/* Version 1.0.0 */`
8			`#/* */`
9			`#/* Author(s): */`
10			`#/* - John Eaton, z3qmtr45@gmail.com */`
11			`#/* */`
12			`#/****************************************************************************/`
13			`#/* */`
14			`#/* */`
15			`#/* Copyright 2016 John T Eaton */`
16			`#/* */`
17			`#/* Licensed under the Apache License, Version 2.0 (the "License"); */`
18			`#/* you may not use this file except in compliance with the License. */`
19			`#/* You may obtain a copy of the License at */`
20			`#/* */`
21			`#/* http://www.apache.org/licenses/LICENSE-2.0 */`
22			`#/* */`
23			`#/* Unless required by applicable law or agreed to in writing, software */`
24			`#/* distributed under the License is distributed on an "AS IS" BASIS, */`
25			`#/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */`
26			`#/* See the License for the specific language governing permissions and */`
27			`#/* limitations under the License. */`
28			`#/* */`
29			`#/* */`
30			`#/****************************************************************************/`
31	128	jt_eaton
32
33			`# ToDo:`
34			`# parse reg from output bus name`
35			`# parse bus and change pin type to bus`
36
37			`use Verilog::Netlist;`
38
39			`# Setup options so files can be found`
40			`use Verilog::Getopt;`
41			`my $opt = new Verilog::Getopt;`
42			`$opt->parameter( "+incdir+verilog",`
43			`"-y","verilog",`
44			`);`
45
46
47
48
49			`my @files = ();`
50
51			`$SRCFILE = @ARGV[0];`
52			`$outfile = @ARGV[1];`
53
54
55
56
57			`push @files, "$SRCFILE";`
58
59
60
61
62
63
64			`# Prepare netlist`
65			`my $nl = new Verilog::Netlist (options => $opt,);`
66
67
68
69
70
71
72			`foreach $file (@files) {`
73			`print "Parsing $file\n";`
74			`$nl->read_file (filename=>$file);`
75			`}`
76
77
78
79
80
81
82
83			`# Read in any sub-modules`
84			`$nl->link();`
85			`$nl->exit_if_error();`
86
87
88			`foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}`
89
90
91
92			`sub make_sch {`
93			`my $mod = shift;`
94			`my $mod_name = $mod->name;`
95
96			`my $in_count = 0;`
97			`my $out_count = 0;`
98			`my $in_length = 0;`
99			`my $out_length = 0;`
100
101			`my $color = 5;`
102			`my $size = 10;`
103
104
105			`open(FILE,">${outfile}${mod_name}.sch") or die "No sch directory";`
106
107			`foreach my $sig ($mod->ports_sorted) {`
108
109			`my $dir = $sig->direction;`
110			`my $data_type = $sig->data_type;`
111			`my $sig_name = $sig->name;`
112			`$data_type =~ s/reg //;`
113			`$data_type =~ s/reg//;`
114
115
116
117
118
119
120			`if($data_type)`
121			`{`
122			`$pin_name = "$sig_name"."$data_type";`
123			`if("in" eq $dir)`
124			`{`
125			`push(@invads,$pin_name);`
126			`$in_count = $in_count+1;`
127			`if( length($pin_name) > $in_length) { $in_length = length($pin_name)};`
128			`}`
129			`if("out" eq $dir)`
130			`{`
131			`push(@outvads,$pin_name);`
132			`$out_count = $out_count+1;`
133			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
134			`}`
135			`if("inout" eq $dir)`
136			`{`
137			`push(@inoutvads,$pin_name);`
138			`$in_count = $in_count+1;`
139			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
140			`}`
141
142			`}`
143			`else`
144			`{`
145			`$pin_name = $sig_name;`
146			`if("in" eq $dir)`
147			`{`
148			`push(@inpads,$pin_name);`
149			`$in_count = $in_count+1;`
150			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
151			`}`
152			`if("out" eq $dir)`
153			`{`
154			`push(@outpads,$pin_name);`
155			`$out_count = $out_count+1;`
156			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
157			`}`
158
159			`if("inout" eq $dir)`
160			`{`
161			`push(@inoutpads,$pin_name);`
162			`$in_count = $in_count+1;`
163			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
164			`}`
165
166
167			`};`
168
169
170			`}`
171
172			`my $max_pins;`
173
174			`if($in_count > $out_count) {$max_pins = $in_count ;} else {$max_pins = $out_count ;}`
175
176			`my $in_edg = ($in_length)10$size +200;`
177			`my $in_pad = ($in_length)10$size +200;`
178			`my $out_edg = ($in_length +$out_length)10$size +2500;`
179			`my $out_pad = ($in_length +$out_length)10$size +1500;`
180
181			`printf FILE ("v 20100214 1\n");`
182
183			`printf ("%s\n", $mod->name);`
184
185			`my $pin_y = 300;`
186
187			`while( $name =pop(@invads))`
188			`{`
189			`printf FILE ("C $in_pad $pin_y 1 0 0 in_port_v.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);`
190			`$pin_y = $pin_y +400;`
191			`}`
192
193
194			`while( $name =pop(@inpads))`
195			`{`
196			`printf FILE ("C $in_pad $pin_y 1 0 0 in_port.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);`
197			`$pin_y = $pin_y +400;`
198			`}`
199
200
201
202			`while( $name =pop(@inoutvads))`
203			`{`
204			`printf FILE ("C $in_pad $pin_y 1 0 0 io_port_v.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);`
205			`$pin_y = $pin_y +400;`
206			`}`
207
208
209			`while( $name =pop(@inoutpads))`
210			`{`
211			`printf FILE ("C $in_pad $pin_y 1 0 0 io_port.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);`
212			`$pin_y = $pin_y +400;`
213			`}`
214
215
216
217
218			`$pin_y = 300;`
219
220			`while( $name =pop(@outvads))`
221			`{`
222			`printf FILE ("C $out_pad $pin_y 1 0 0 out_port_v.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);`
223			`$pin_y = $pin_y +400;`
224			`}`
225
226
227			`while( $name =pop(@outpads))`
228			`{`
229			`printf FILE ("C $out_pad $pin_y 1 0 0 out_port.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);`
230			`$pin_y = $pin_y +400;`
231			`}`
232
233
234
235
236
237
238			`foreach my $cell ($mod->cells_sorted) {`
239			`close(FILE);`
240			`make_sch ($cell->submod, $cell->name) if $cell->submod;`
241			`}`
242			`}`
243
244
245
246
247
248
249
250			`1;`
251
252
253
254
255
256
257