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// Created by fizzim.pl version 4.41 on 2012:05:11 at 18:29:56 (www.fizzim.com)
 
module `VARIANT`multibit_dp (
  output reg [7:0] counter,
  output wire ds,
  output reg [6:5] mmout,
  output reg mout,
  output wire rd,
  output wire [15:13] rmout,
  input wire clk,
  input wire [7:0] counter_preset,
  input wire go,
  input wire [3:0] mbin,
  input wire rst_n,
  input wire ws
);
 
  // state bits
  parameter
  IDLE = 6'b000000, // extra=0 rmout[15:13]=000 rd=0 ds=0
  DLY  = 6'b010110, // extra=0 rmout[15:13]=101 rd=1 ds=0
  DONE = 6'b001100, // extra=0 rmout[15:13]=011 rd=0 ds=0
  READ = 6'b110110; // extra=1 rmout[15:13]=101 rd=1 ds=0
 
  reg [5:0] state;
  reg [5:0] nextstate;
 
  // comb always block
  always @* begin
    nextstate = state; // default to hold value because implied_loopback is set
    mmout[6:5] = 'b00; // default
    mout = 0; // default
    case (state)
      IDLE: begin
        mmout[6:5] = 'b11;
        mout = go && (mbin == 'hd);
        if (go && (mbin == 'hd)) begin
          nextstate = READ;
        end
      end
      DLY : begin
        mout = 1;
        if (ws) begin
          nextstate = READ;
        end
        else begin
          nextstate = DONE;
        end
      end
      DONE: begin
        begin
          nextstate = IDLE;
        end
      end
      READ: begin
        mout = 1;
        begin
          nextstate = DLY;
        end
      end
    endcase
  end
 
  // Assign reg'd outputs to state bits
  assign ds = state[0];
  assign rd = state[1];
  assign rmout[15:13] = state[4:2];
 
  // sequential always block
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      state <= IDLE;
    else
      state <= nextstate;
  end
 
  // datapath sequential always block
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      counter[7:0] <= counter_preset[7:0];
    end
    else begin
      counter[7:0] <= counter[7:0]; // default
      case (nextstate)
        IDLE: begin
          counter[7:0] <= counter_preset[7:0];
        end
        DLY : begin
          counter[7:0] <= counter[7:0] + 1;
        end
        DONE: begin
          counter[7:0] <= 'hff;
        end
      endcase
    end
  end
 
  // This code allows you to see state names in simulation
  `ifndef SYNTHESIS
  reg [31:0] statename;
  always @* begin
    case (state)
      IDLE:
        statename = "IDLE";
      DLY :
        statename = "DLY";
      DONE:
        statename = "DONE";
      READ:
        statename = "READ";
      default:
        statename = "XXXX";
    endcase
  end
  `endif
 
endmodule
 

Line No.	Rev	Author	Line
1	117	jt_eaton
2			`// Created by fizzim.pl version 4.41 on 2012:05:11 at 18:29:56 (www.fizzim.com)`
3
4			module `VARIANT`multibit_dp (
5			`output reg [7:0] counter,`
6			`output wire ds,`
7			`output reg [6:5] mmout,`
8			`output reg mout,`
9			`output wire rd,`
10			`output wire [15:13] rmout,`
11			`input wire clk,`
12			`input wire [7:0] counter_preset,`
13			`input wire go,`
14			`input wire [3:0] mbin,`
15			`input wire rst_n,`
16			`input wire ws`
17			`);`
18
19			`// state bits`
20			`parameter`
21			`IDLE = 6'b000000, // extra=0 rmout[15:13]=000 rd=0 ds=0`
22			`DLY = 6'b010110, // extra=0 rmout[15:13]=101 rd=1 ds=0`
23			`DONE = 6'b001100, // extra=0 rmout[15:13]=011 rd=0 ds=0`
24			`READ = 6'b110110; // extra=1 rmout[15:13]=101 rd=1 ds=0`
25
26			`reg [5:0] state;`
27			`reg [5:0] nextstate;`
28
29			`// comb always block`
30			`always @* begin`
31			`nextstate = state; // default to hold value because implied_loopback is set`
32			`mmout[6:5] = 'b00; // default`
33			`mout = 0; // default`
34			`case (state)`
35			`IDLE: begin`
36			`mmout[6:5] = 'b11;`
37			`mout = go && (mbin == 'hd);`
38			`if (go && (mbin == 'hd)) begin`
39			`nextstate = READ;`
40			`end`
41			`end`
42			`DLY : begin`
43			`mout = 1;`
44			`if (ws) begin`
45			`nextstate = READ;`
46			`end`
47			`else begin`
48			`nextstate = DONE;`
49			`end`
50			`end`
51			`DONE: begin`
52			`begin`
53			`nextstate = IDLE;`
54			`end`
55			`end`
56			`READ: begin`
57			`mout = 1;`
58			`begin`
59			`nextstate = DLY;`
60			`end`
61			`end`
62			`endcase`
63			`end`
64
65			`// Assign reg'd outputs to state bits`
66			`assign ds = state[0];`
67			`assign rd = state[1];`
68			`assign rmout[15:13] = state[4:2];`
69
70			`// sequential always block`
71			`always @(posedge clk or negedge rst_n) begin`
72			`if (!rst_n)`
73			`state <= IDLE;`
74			`else`
75			`state <= nextstate;`
76			`end`
77
78			`// datapath sequential always block`
79			`always @(posedge clk or negedge rst_n) begin`
80			`if (!rst_n) begin`
81			`counter[7:0] <= counter_preset[7:0];`
82			`end`
83			`else begin`
84			`counter[7:0] <= counter[7:0]; // default`
85			`case (nextstate)`
86			`IDLE: begin`
87			`counter[7:0] <= counter_preset[7:0];`
88			`end`
89			`DLY : begin`
90			`counter[7:0] <= counter[7:0] + 1;`
91			`end`
92			`DONE: begin`
93			`counter[7:0] <= 'hff;`
94			`end`
95			`endcase`
96			`end`
97			`end`
98
99			`// This code allows you to see state names in simulation`
100			`ifndef SYNTHESIS
101			`reg [31:0] statename;`
102			`always @* begin`
103			`case (state)`
104			`IDLE:`
105			`statename = "IDLE";`
106			`DLY :`
107			`statename = "DLY";`
108			`DONE:`
109			`statename = "DONE";`
110			`READ:`
111			`statename = "READ";`
112			`default:`
113			`statename = "XXXX";`
114			`endcase`
115			`end`
116			`endif
117
118			`endmodule`
119

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