OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [ip-xact/] [1685.1/] [model.xsd] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
2
62
63
    
64
    
65
    
66
    
67
        
68
            Component view type
69
        
70
        
71
            
72
            
73
                
74
                     Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from spirit:fileType. The tool values are defined by the SPIRIT Consortium, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.  
75
                
76
                
77
                    
78
                        
79
                    
80
                
81
            
82
            
83
                
84
                    
85
                         References an IP-XACT design or configuration document (by VLNV) that provides a design for the component 
86
                    
87
                
88
                
89
                    
90
                        
91
                             The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design.  
92
                        
93
                        
94
                            
95
                                
96
                                    
97
                                        
98
                                            A value of 'true' indicates that this value must match the language being generated for the design.
99
                                        
100
                                    
101
                                
102
                            
103
                        
104
                    
105
                    
106
                        
107
                            Language specific name to identity the model. Verilog or SystemVerilog this is the module name. For VHDL this is, with ()’s, the entity(architecture) name pair or without, a single configuration name.  For SystemC this is the class name.
108
                        
109
                    
110
                    
111
                        
112
                            Default command and flags used to build derived files from the sourceName files in the referenced file sets.
113
                        
114
                    
115
                    
116
                    
117
                    
118
                        
119
                             Container for white box element references.  
120
                        
121
                        
122
                            
123
                                
124
                                    
125
                                         Reference to a white box element which is visible within this view.  
126
                                    
127
                                
128
                            
129
                        
130
                    
131
                    
132
                
133
            
134
            
135
        
136
    
137
    
138
        
139
            Abstraction view type
140
        
141
        
142
            
143
            
144
                
145
                     Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from spirit:fileType. The tool values are defined by the SPIRIT Consortium, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.  
146
                
147
                
148
                    
149
                        
150
                    
151
                
152
            
153
            
154
                
155
                     The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design.  
156
                
157
                
158
                    
159
                        
160
                            
161
                                
162
                                    A value of 'true' indicates that this value must match the language being generated for the design.
163
                                
164
                            
165
                        
166
                    
167
                
168
            
169
            
170
                
171
                    Language specific name to identity the model. Verilog or SystemVerilog this is the module name. For VHDL this is, with ()’s, the entity(architecture) name pair or without a single configuration name.  For SystemC this is the class name.
172
                
173
            
174
            
175
                
176
                    Default command and flags used to build derived files from the sourceName files in the referenced file sets.
177
                
178
            
179
            
180
            
181
            
182
        
183
    
184
    
185
        
186
            Model information.
187
                        
188
        
189
        
190
            
191
                
192
                    View container
193
                
194
                
195
                    
196
                        
197
                            
198
                                Single view of a component
199
                            
200
                        
201
                    
202
                
203
            
204
            
205
                
206
                    Port container
207
                
208
                
209
                    
210
                        
211
                    
212
                
213
            
214
            
215
                
216
                    Model parameter name value pairs container
217
                
218
                
219
                    
220
                        
221
                            
222
                                A model parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used.
223
                                                                
224
                            
225
                        
226
                    
227
                
228
            
229
        
230
    
231
    
232
        
233
            Model information for an abstractor.
234
        
235
        
236
            
237
                
238
                    View container
239
                
240
                
241
                    
242
                        
243
                            
244
                                Single view of an abstractor
245
                            
246
                        
247
                    
248
                
249
            
250
            
251
                
252
                    Port container
253
                
254
                
255
                    
256
                        
257
                    
258
                
259
            
260
            
261
                
262
                    Model parameter name value pairs container
263
                
264
                
265
                    
266
                        
267
                            
268
                                A model parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicate how the model parameter is to be used.
269
                                                                
270
                            
271
                        
272
                    
273
                
274
            
275
        
276
    
277
    
278
        
279
            Model information.
280
        
281
    
282
    
283
        
284
             Reference to a whiteboxElement within a view. The 'name' attribute must refer to a whiteboxElement defined within this component.  
285
        
286
        
287
            
288
                
289
                     The whiteboxPath elements (as a set) define the name(s) needed to define the entire white box element in this view.  
290
                
291
                
292
                    
293
                        
294
                            
295
                                 The view specific name for a portion of the white box element.  
296
                            
297
                        
298
                        
299
                            
300
                                 Optional bound on the path name. If not specified, the size of the element referred to by pathName must be determined from the referenced element.  
301
                            
302
                            
303
                                
304
                                     Indicates the left bound value for the associated path name.  
305
                                
306
                            
307
                            
308
                                
309
                                     Indicates the right bound values for the associated path name.  
310
                                
311
                            
312
                        
313
                    
314
                
315
            
316
        
317
        
318
            
319
                Reference to a whiteboxElement defined within this component.  
320
            
321
        
322
    
323

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.