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            The direction of a component port.

            Definition of the indecies for a vectored port.

                        The optional elements left and right can be used to select a bit-slice of a port vector to map to the bus interface. 

                        The optional elements left and right can be used to select a bit-slice of a port vector to map to the bus interface. 

            Basic port declarations.

                    Port style

                        Defines a port whose type resolves to simple bits.

                        Defines a port that implements or uses a service that can be implemented with functions or methods.

                        Port access characteristics.

            A port description, giving a name and an access type for high level ports. 

            A port description, giving a name and an access type for high level ports. 

                                Port style

                                    Defines a port whose type resolves to simple bits.

                                    Defines a port that implements or uses a service that can be implemented with functions or methods.

                                    Port access characteristics.

            If this element is present, the type of access is restricted to the specified value.

            Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed by pointer.

            Definition of a single transactional type defintion

                        The name of the port type. Can be any predefined type such sc_port or sc_export in SystemC or any user-defined type such as tlm_port.

                                        Defines that the type for the port has constrainted the number of bits in the vector

                        Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition.

            Definition of a single service type defintion

                        The name of the service type. Can be any predefined type such as booean or integer or any user-defined type such as addr_type or data_type.

                                        Defines that the type for the port has constrainted the number of bits in the vector

                                        Defines that the typeName supplied for this service is implicit and a netlister should not declare this service in

a language specific top-level netlist 

                        Where the definition of the type is contained if the type if not part of the language. For SystemC and SystemVerilog it is the include file containing the type definition.

                        list service parameters (e.g. parameters for a systemVerilog interface)

            Definition of a single wire type defintion that can relate to multiple views.

                        The name of the logic type. Examples could be std_logic, std_ulogic, std_logic_vector, sc_logic, ...

                                        Defines that the type for the port has constrainted the number of bits in the vector

                        Where the definition of the type is contained. For std_logic, this is contained in IEEE.std_logic_1164.all. For sc_logic, this is contained in systemc.h. For VHDL this is the library and package as defined by the "used" statement. For SystemC and SystemVerilog it is the include file required. For verilog this is not needed.

                        A reference to a view name in the file for which this type applies.

            The group of type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

            The group of wire type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

            If present, is a method to be used to get hold of the object representing the port. This is typically a function call or array element reference in systemC.

            Describes port characteristics.

            Wire port type for a component.

                    The direction of a wire style port. The basic directions for a port are 'in' for input ports, 'out' for output port and 'inout' for bidirectional and tristate ports.

A value of 'phantom' is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

                    Specific left and right vector bounds. Signal width is

max(left,right)-min(left,right)+1 When the bounds are not present, a scalar port is assumed.

                True if logical ports with different directions from the physical port direction may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all direction value to be mapped onto the physical port. Also ignored for inout ports, since any logical port maybe mapped to a physical inout port.                  

            Transactional port type.

                    Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV).

                    Describes the interface protocol.

                                Defines how the port accesses this service.

                                The group of service type definitions. 

                    Bounds number of legal connections.

                                Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections.

                                Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1.

                True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for "both" ports, since any logical port may be mapped to a physical "both" port.                   

            Wire port type for an abstractor.

                            Specific left and right vector bounds. Signal width is

max(left,right)-min(left,right)+1 When the bounds are not present, a scalar port is assumed.

                    Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed through a pointer.