1 |
119 |
jt_eaton |
eval 'exec `which perl` -S $0 ${1+"$@"}'
|
2 |
|
|
if 0;
|
3 |
|
|
|
4 |
|
|
#/**********************************************************************/
|
5 |
|
|
#/* */
|
6 |
|
|
#/* ------- */
|
7 |
|
|
#/* / SOC \ */
|
8 |
|
|
#/* / GEN \ */
|
9 |
|
|
#/* / TOOL \ */
|
10 |
|
|
#/* ============== */
|
11 |
|
|
#/* | | */
|
12 |
|
|
#/* |____________| */
|
13 |
|
|
#/* */
|
14 |
|
|
#/* */
|
15 |
|
|
#/* */
|
16 |
|
|
#/* Author(s): */
|
17 |
|
|
#/* - John Eaton, jt_eaton@opencores.org */
|
18 |
|
|
#/* */
|
19 |
|
|
#/**********************************************************************/
|
20 |
|
|
#/* */
|
21 |
|
|
#/* Copyright (C) <2010-2011> */
|
22 |
|
|
#/* */
|
23 |
|
|
#/* This source file may be used and distributed without */
|
24 |
|
|
#/* restriction provided that this copyright statement is not */
|
25 |
|
|
#/* removed from the file and that any derivative work contains */
|
26 |
|
|
#/* the original copyright notice and the associated disclaimer. */
|
27 |
|
|
#/* */
|
28 |
|
|
#/* This source file is free software; you can redistribute it */
|
29 |
|
|
#/* and/or modify it under the terms of the GNU Lesser General */
|
30 |
|
|
#/* Public License as published by the Free Software Foundation; */
|
31 |
|
|
#/* either version 2.1 of the License, or (at your option) any */
|
32 |
|
|
#/* later version. */
|
33 |
|
|
#/* */
|
34 |
|
|
#/* This source is distributed in the hope that it will be */
|
35 |
|
|
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
|
36 |
|
|
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
|
37 |
|
|
#/* PURPOSE. See the GNU Lesser General Public License for more */
|
38 |
|
|
#/* details. */
|
39 |
|
|
#/* */
|
40 |
|
|
#/* You should have received a copy of the GNU Lesser General */
|
41 |
|
|
#/* Public License along with this source; if not, download it */
|
42 |
|
|
#/* from http://www.opencores.org/lgpl.shtml */
|
43 |
|
|
#/* */
|
44 |
|
|
#/**********************************************************************/
|
45 |
|
|
|
46 |
|
|
|
47 |
|
|
|
48 |
|
|
############################################################################
|
49 |
|
|
# General PERL config
|
50 |
|
|
############################################################################
|
51 |
|
|
use Getopt::Long;
|
52 |
|
|
use English;
|
53 |
|
|
use File::Basename;
|
54 |
|
|
use Cwd;
|
55 |
|
|
use XML::LibXML;
|
56 |
|
|
use lib './tools';
|
57 |
|
|
use sys::lib;
|
58 |
|
|
use yp::lib;
|
59 |
|
|
|
60 |
|
|
|
61 |
|
|
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
|
62 |
|
|
|
63 |
|
|
|
64 |
|
|
############################################################################
|
65 |
|
|
### Process the options
|
66 |
|
|
############################################################################
|
67 |
|
|
|
68 |
|
|
Getopt::Long::config("require_order", "prefix=-");
|
69 |
|
|
GetOptions("h",
|
70 |
128 |
jt_eaton |
"envidentifier=s" => \$envidentifier,
|
71 |
119 |
jt_eaton |
"prefix=s" => \$prefix,
|
72 |
|
|
"vendor=s" => \$vendor,
|
73 |
131 |
jt_eaton |
"library=s" => \$library,
|
74 |
119 |
jt_eaton |
"version=s" => \$version,
|
75 |
|
|
"component=s" => \$component,
|
76 |
|
|
"dest_dir=s" => \$dest_dir,
|
77 |
|
|
"bus_intf=s" => \$bus_intf
|
78 |
|
|
) || die "(use '$program_name -h' for help)";
|
79 |
|
|
|
80 |
|
|
|
81 |
|
|
##############################################################################
|
82 |
|
|
## Help option
|
83 |
|
|
##############################################################################
|
84 |
|
|
if ( $opt_h )
|
85 |
|
|
{
|
86 |
131 |
jt_eaton |
print "\n build_registers -envidentifier {sim|syn} -prefix /work -library library_name -component comp_name -version version_name -bus_intf bus_interface -dest_dir dest_dir";
|
87 |
119 |
jt_eaton |
print "\n";
|
88 |
|
|
exit 1;
|
89 |
|
|
}
|
90 |
|
|
|
91 |
|
|
|
92 |
|
|
##############################################################################
|
93 |
|
|
##
|
94 |
|
|
##############################################################################
|
95 |
|
|
|
96 |
128 |
jt_eaton |
my $parser = XML::LibXML->new();
|
97 |
119 |
jt_eaton |
|
98 |
|
|
|
99 |
|
|
$home = cwd();
|
100 |
|
|
|
101 |
128 |
jt_eaton |
|
102 |
131 |
jt_eaton |
my $socgen_file = $parser->parse_file(yp::lib::find_componentConfiguration($vendor,$library,$component));
|
103 |
130 |
jt_eaton |
my $ip_name_base_macro = $socgen_file->findnodes("//socgen:componentConfiguration/socgen:ip_name_base_macro/text()")->to_literal;
|
104 |
128 |
jt_eaton |
|
105 |
|
|
|
106 |
|
|
|
107 |
|
|
|
108 |
|
|
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
|
112 |
119 |
jt_eaton |
my $variant;
|
113 |
|
|
if($version) {$variant = "${component}_${version}";}
|
114 |
|
|
else {$variant = "${component}";}
|
115 |
|
|
|
116 |
131 |
jt_eaton |
my $lib_comp_sep = yp::lib::find_lib_comp_sep($vendor,$library,$component);
|
117 |
|
|
my $comp_xml_sep = yp::lib::find_comp_xml_sep($vendor,$library,$component,$version);
|
118 |
119 |
jt_eaton |
|
119 |
|
|
#############################################################################
|
120 |
|
|
##
|
121 |
|
|
##
|
122 |
|
|
#############################################################################
|
123 |
|
|
|
124 |
131 |
jt_eaton |
print " Building RTL Registers for $prefix $vendor $library $component $variant in $dest_dir\n" ;
|
125 |
119 |
jt_eaton |
|
126 |
|
|
|
127 |
|
|
|
128 |
131 |
jt_eaton |
my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}";
|
129 |
119 |
jt_eaton |
mkdir $path,0755 unless( -e $path );
|
130 |
|
|
|
131 |
|
|
|
132 |
|
|
|
133 |
|
|
my $name;
|
134 |
131 |
jt_eaton |
|
135 |
119 |
jt_eaton |
my $memmap_name;
|
136 |
|
|
my $memmap_base;
|
137 |
|
|
my $addblk_name;
|
138 |
|
|
my $addblk_range;
|
139 |
|
|
my $addblk_numrange;
|
140 |
|
|
my $addblk_numaddbits;
|
141 |
|
|
my $addblk_width;
|
142 |
|
|
my $byte_size;
|
143 |
|
|
my $reg_dim;
|
144 |
|
|
my $memMap;
|
145 |
|
|
|
146 |
|
|
|
147 |
|
|
my $memmap_name;
|
148 |
|
|
my $memmap_base;
|
149 |
|
|
my $memmap_numbase;
|
150 |
|
|
my $memmap_size;
|
151 |
|
|
my $memmap_type;
|
152 |
|
|
my $parmap_name;
|
153 |
|
|
|
154 |
|
|
my $reg_offset;
|
155 |
|
|
my $reg_numoffset;
|
156 |
|
|
my $reg_dimbits;
|
157 |
|
|
my $reg_create;
|
158 |
|
|
my $reg_has_read;
|
159 |
|
|
my $reg_has_write;
|
160 |
|
|
my $opt_bigendian;
|
161 |
|
|
|
162 |
|
|
my $reg_numdim;
|
163 |
|
|
|
164 |
|
|
my $max_dim = 1;
|
165 |
|
|
my $max_has_read = 0;
|
166 |
|
|
my $max_has_write = 0;
|
167 |
|
|
my $max_has_create = 0;
|
168 |
|
|
|
169 |
|
|
my $pad;
|
170 |
|
|
my $sys_byte_lanes;
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
@registers = ();
|
174 |
|
|
|
175 |
|
|
#/**********************************************************************/
|
176 |
|
|
#/* */
|
177 |
|
|
#/* Parse register block info from ip-xact file */
|
178 |
|
|
#/* */
|
179 |
|
|
#/* */
|
180 |
|
|
#/**********************************************************************/
|
181 |
|
|
|
182 |
|
|
|
183 |
|
|
|
184 |
128 |
jt_eaton |
|
185 |
131 |
jt_eaton |
my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($vendor,$library,$component,$version));
|
186 |
119 |
jt_eaton |
|
187 |
|
|
$name = $spirit_component_file->findnodes('//spirit:component/spirit:name/text()')->to_literal ;
|
188 |
|
|
$version = $spirit_component_file->findnodes('//spirit:component/spirit:version/text()')->to_literal ;
|
189 |
|
|
$vendor = $spirit_component_file->findnodes('//spirit:component/spirit:vendor/text()')->to_literal ;
|
190 |
|
|
$library = $spirit_component_file->findnodes('//spirit:component/spirit:library/text()')->to_literal ;
|
191 |
|
|
|
192 |
|
|
foreach my $bus_iface ($spirit_component_file->findnodes("//spirit:busInterface[spirit:name/text() = '$bus_intf']/spirit:slave"))
|
193 |
|
|
{
|
194 |
|
|
$BI_name = $bus_iface->findnodes('../spirit:name/text()')->to_literal ;
|
195 |
|
|
$BI_endian = $bus_iface->findnodes('../spirit:endianness/text()')->to_literal ;
|
196 |
|
|
$BI_width = $bus_iface->findnodes('../spirit:bitsInLau/text()')->to_literal ;
|
197 |
|
|
$BI_xname = $bus_iface->findnodes('../spirit:abstractionType/@spirit:name')->to_literal ;
|
198 |
|
|
$memMap = $bus_iface->findnodes('../spirit:slave/spirit:memoryMapRef/@spirit:memoryMapRef')->to_literal ;
|
199 |
|
|
}
|
200 |
|
|
|
201 |
|
|
unless($BI_endian) {$BI_endian = "little";}
|
202 |
|
|
$byte_size = int($BI_width) ;
|
203 |
|
|
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
|
210 |
|
|
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']"))
|
211 |
|
|
{
|
212 |
|
|
$memmap_name = $comp_view->findnodes('./spirit:bank/spirit:name/text()')->to_literal ;
|
213 |
|
|
$memmap_base = $comp_view->findnodes('./spirit:bank/spirit:baseAddress/text()')->to_literal ;
|
214 |
|
|
$memmap_size = $comp_view->findnodes('./spirit:addressUnitBits/text()')->to_literal ;
|
215 |
|
|
$memmap_type = $comp_view->findnodes('./spirit:bank/@spirit:bankAlignment')->to_literal ;
|
216 |
|
|
$parmap_name = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
|
220 |
|
|
$memmap_numbase = hex($memmap_base);
|
221 |
|
|
|
222 |
|
|
#/**********************************************************************/
|
223 |
|
|
#/* */
|
224 |
|
|
#/* Print header, module name and start parameters */
|
225 |
|
|
#/* */
|
226 |
|
|
#/* */
|
227 |
|
|
#/**********************************************************************/
|
228 |
|
|
|
229 |
131 |
jt_eaton |
my $outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/${name}_${version}_${memmap_name}";
|
230 |
119 |
jt_eaton |
open OUTFILE,">$outfile" or die "unable to open $outfile";
|
231 |
|
|
|
232 |
|
|
print OUTFILE " /*********************************************/ \n";
|
233 |
|
|
print OUTFILE sprintf(" /* Vendor: %24s */ \n",$vendor);
|
234 |
|
|
print OUTFILE sprintf(" /* Library: %24s */ \n",$library);
|
235 |
|
|
print OUTFILE sprintf(" /* Component: %24s */ \n",$name);
|
236 |
|
|
print OUTFILE sprintf(" /* Version: %24s */ \n",$version);
|
237 |
|
|
print OUTFILE sprintf(" /* MemMap: %24s */ \n",$memmap_name);
|
238 |
|
|
print OUTFILE sprintf(" /* Base: %24s */ \n",$memmap_base);
|
239 |
|
|
print OUTFILE sprintf(" /* Type: %24s */ \n",$memmap_type);
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
|
244 |
|
|
if($BI_endian eq "big" )
|
245 |
|
|
{
|
246 |
|
|
$opt_bigendian = 1;
|
247 |
|
|
print OUTFILE " /* Endian: Big */ \n";
|
248 |
|
|
}
|
249 |
|
|
else
|
250 |
|
|
|
251 |
|
|
{
|
252 |
|
|
print OUTFILE " /* Endian: Little */ \n";
|
253 |
|
|
$opt_bigendian = 0;
|
254 |
|
|
}
|
255 |
|
|
|
256 |
|
|
print OUTFILE sprintf(" /*********************************************/ \n");
|
257 |
|
|
|
258 |
|
|
|
259 |
|
|
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock/spirit:name"))
|
260 |
|
|
{
|
261 |
|
|
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
|
262 |
|
|
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
|
263 |
|
|
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
|
264 |
|
|
|
265 |
|
|
|
266 |
|
|
|
267 |
|
|
$addblk_numrange = hex($addblk_range);
|
268 |
|
|
$addblk_numaddbits = log($addblk_numrange)/log(2);
|
269 |
|
|
|
270 |
|
|
$sys_byte_lanes = int( $addblk_width) / $byte_size ;
|
271 |
|
|
|
272 |
|
|
if ($sys_byte_lanes == 4 ) { $adr_base = 2;}
|
273 |
|
|
elsif ($sys_byte_lanes == 2 ) { $adr_base = 1;}
|
274 |
|
|
else { $adr_base = 0;}
|
275 |
|
|
|
276 |
|
|
|
277 |
|
|
print OUTFILE sprintf(" /* AddressBlock: %24s */ \n",$addblk_name);
|
278 |
|
|
print OUTFILE sprintf(" /* NumBase: %24s */ \n",$memmap_numbase);
|
279 |
|
|
print OUTFILE sprintf(" /* Range: %24s */ \n",$addblk_range);
|
280 |
|
|
print OUTFILE sprintf(" /* NumRange: %24s */ \n",$addblk_numrange);
|
281 |
|
|
print OUTFILE sprintf(" /* NumAddBits: %24s */ \n",$addblk_numaddbits);
|
282 |
|
|
print OUTFILE sprintf(" /* Width: %24s */ \n",$addblk_width);
|
283 |
|
|
print OUTFILE sprintf(" /* Byte_lanes: %24s */ \n",$sys_byte_lanes);
|
284 |
|
|
print OUTFILE sprintf(" /* Byte_size: %24s */ \n",$byte_size);
|
285 |
|
|
print OUTFILE sprintf(" /*********************************************/ \n");
|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
foreach my $reg_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock[spirit:name/text() = '$addblk_name']/spirit:register/spirit:name "))
|
289 |
|
|
|
290 |
|
|
{
|
291 |
|
|
$reg_name = $reg_view->findnodes('./text()')->to_literal ;
|
292 |
|
|
$reg_offset = $reg_view->findnodes('../spirit:addressOffset/text()')->to_literal ;
|
293 |
|
|
$reg_dim = $reg_view->findnodes('../spirit:dim/text()')->to_literal ;
|
294 |
|
|
$reg_size = $reg_view->findnodes('../spirit:size/text()')->to_literal ;
|
295 |
|
|
$reg_access = $reg_view->findnodes('../spirit:access/text()')->to_literal ;
|
296 |
|
|
$reg_numoffset = hex($reg_offset) + $memmap_numbase;
|
297 |
|
|
unless($reg_dim) {$reg_dim = "0x1" ;}
|
298 |
|
|
$reg_numdim = hex($reg_dim);
|
299 |
|
|
|
300 |
|
|
if($reg_numdim > $max_dim ) {$max_dim = $reg_numdim;}
|
301 |
|
|
|
302 |
|
|
if($reg_numdim)
|
303 |
|
|
{
|
304 |
|
|
$reg_dimbits = log($reg_numdim)/log(2);
|
305 |
|
|
}
|
306 |
|
|
else
|
307 |
|
|
{
|
308 |
|
|
$reg_dimbits = 1;
|
309 |
|
|
}
|
310 |
|
|
|
311 |
|
|
if($reg_access eq "read-write")
|
312 |
|
|
{
|
313 |
|
|
$reg_has_read = 1;
|
314 |
|
|
$reg_has_write = 1;
|
315 |
|
|
if($reg_numdim)
|
316 |
|
|
{
|
317 |
|
|
if($reg_dimbits) {$reg_create = 0;}
|
318 |
|
|
else {$reg_create = 1;}
|
319 |
|
|
}
|
320 |
|
|
else
|
321 |
|
|
{
|
322 |
|
|
$reg_create = 0;
|
323 |
|
|
}
|
324 |
|
|
}
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
if($reg_access eq "read-only")
|
332 |
|
|
{
|
333 |
|
|
$reg_has_read = 1;
|
334 |
|
|
$reg_has_write = 0;
|
335 |
|
|
if($reg_numdim)
|
336 |
|
|
{
|
337 |
|
|
if($reg_dimbits) {$reg_create = 0;}
|
338 |
|
|
else {$reg_create = 1;}
|
339 |
|
|
}
|
340 |
|
|
else
|
341 |
|
|
{
|
342 |
|
|
$reg_create = 0;
|
343 |
|
|
}
|
344 |
|
|
|
345 |
|
|
}
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
if($reg_access eq "write-only")
|
349 |
|
|
{
|
350 |
|
|
$reg_has_read = 0;
|
351 |
|
|
$reg_has_write = 1;
|
352 |
|
|
if($reg_numdim)
|
353 |
|
|
{
|
354 |
|
|
if($reg_dimbits) {$reg_create = 0;}
|
355 |
|
|
else {$reg_create = 1;}
|
356 |
|
|
}
|
357 |
|
|
else
|
358 |
|
|
{
|
359 |
|
|
$reg_create = 0;
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
}
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
if($reg_access eq "write-strobe")
|
366 |
|
|
{
|
367 |
|
|
$reg_has_read = 0;
|
368 |
|
|
$reg_has_write = 1;
|
369 |
|
|
$reg_create = 0;
|
370 |
|
|
}
|
371 |
|
|
|
372 |
|
|
if($reg_has_read){$max_has_read = 1;}
|
373 |
|
|
if($reg_has_write){$max_has_write = 1;}
|
374 |
|
|
if($reg_create) {$max_has_create = 1;}
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
|
381 |
|
|
print OUTFILE sprintf(" /* Reg Name: %22s */ \n",$reg_name);
|
382 |
|
|
print OUTFILE sprintf(" /* Reg Offset: %22s */ \n",$reg_offset);
|
383 |
|
|
print OUTFILE sprintf(" /* Reg numOffset: %22s */ \n",$reg_numoffset);
|
384 |
|
|
print OUTFILE sprintf(" /* Reg size: %22s */ \n",$reg_size);
|
385 |
|
|
print OUTFILE sprintf(" /* Reg Dim: %22s */ \n",$reg_dim);
|
386 |
|
|
print OUTFILE sprintf(" /* Reg numDim: %22s */ \n",$reg_numdim);
|
387 |
|
|
print OUTFILE sprintf(" /* Reg DimBits: %22s */ \n",$reg_dimbits);
|
388 |
|
|
print OUTFILE sprintf(" /* Reg Create: %22s */ \n",$reg_create);
|
389 |
|
|
print OUTFILE sprintf(" /* Reg access: %22s */ \n",$reg_access);
|
390 |
|
|
print OUTFILE sprintf(" /* Reg has_read: %22s */ \n",$reg_has_read);
|
391 |
|
|
print OUTFILE sprintf(" /* Reg has_write: %22s */ \n",$reg_has_write);
|
392 |
|
|
print OUTFILE sprintf(" /*********************************************/ \n");
|
393 |
|
|
|
394 |
|
|
push @registers , ":::${reg_name}:::${reg_numoffset}:::${reg_size}:::${reg_numdim}:::${reg_dimbits}:::${reg_create}:::${reg_access}:::${reg_has_read}:::${reg_has_write}:::";
|
395 |
|
|
|
396 |
|
|
}
|
397 |
|
|
}
|
398 |
|
|
|
399 |
|
|
if($memmap_type eq "serial") { $memmap_numbase = $memmap_numbase + $addblk_numrange; }
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
}
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
$num_add = log($max_dim)/log(2);
|
410 |
|
|
print OUTFILE sprintf(" /*********************************************/ \n");
|
411 |
|
|
print OUTFILE sprintf(" /* Max_dim: %22s */ \n",$max_dim);
|
412 |
|
|
print OUTFILE sprintf(" /* num_add: %22s */ \n",$num_add);
|
413 |
|
|
print OUTFILE sprintf(" /* mas_has_read: %22s */ \n",$max_has_read);
|
414 |
|
|
print OUTFILE sprintf(" /* mas_has_write: %22s */ \n",$max_has_write);
|
415 |
|
|
print OUTFILE sprintf(" /* mas_has_create: %22s */ \n",$max_has_create);
|
416 |
|
|
print OUTFILE sprintf(" /*********************************************/ \n");
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
print OUTFILE " /*********************************************/ \n";
|
426 |
128 |
jt_eaton |
print OUTFILE "\n\nmodule `${ip_name_base_macro}`";
|
427 |
119 |
jt_eaton |
print OUTFILE uc(${memmap_name});
|
428 |
|
|
print OUTFILE "\n";
|
429 |
134 |
jt_eaton |
print OUTFILE "#( parameter UNSELECTED = {${byte_size}{1'b1}},\n";
|
430 |
|
|
print OUTFILE " parameter UNMAPPED = {${byte_size}{1'b0}}";
|
431 |
119 |
jt_eaton |
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
foreach $line (@registers)
|
440 |
|
|
{
|
441 |
|
|
|
442 |
|
|
$_ = $line;
|
443 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
444 |
|
|
{
|
445 |
|
|
my $t_name = $1;
|
446 |
|
|
my $t_numoffset = $2;
|
447 |
|
|
my $t_size = $3;
|
448 |
|
|
my $t_numdim = $4;
|
449 |
|
|
my $t_dimbits = $5;
|
450 |
|
|
my $t_create = $6;
|
451 |
|
|
my $t_access = $7;
|
452 |
|
|
my $t_has_read = $8;
|
453 |
|
|
my $t_has_write = $9;
|
454 |
|
|
|
455 |
|
|
if( $t_has_write eq "1" and $t_create eq "1")
|
456 |
|
|
{
|
457 |
|
|
print OUTFILE ",\n parameter ";
|
458 |
|
|
print OUTFILE uc(${t_name});
|
459 |
|
|
print OUTFILE "_RST = ${t_size}'b0";
|
460 |
|
|
}
|
461 |
|
|
|
462 |
|
|
$pad = $byte_size -( int(${t_size}) % $byte_size ) ;
|
463 |
|
|
if ( $pad == $byte_size ) { $pad = 0;}
|
464 |
|
|
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
if($pad)
|
468 |
|
|
{
|
469 |
|
|
if( $t_has_read eq "1")
|
470 |
|
|
{
|
471 |
|
|
print OUTFILE ",\n parameter ";
|
472 |
|
|
print OUTFILE uc(${t_name});
|
473 |
|
|
print OUTFILE "_PAD = ${pad}'b0";
|
474 |
|
|
}
|
475 |
|
|
|
476 |
|
|
}
|
477 |
|
|
|
478 |
|
|
}
|
479 |
|
|
}
|
480 |
|
|
|
481 |
|
|
print OUTFILE ")\n ";
|
482 |
|
|
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
#/**********************************************************************/
|
490 |
|
|
#/* */
|
491 |
|
|
#/* Print io ports */
|
492 |
|
|
#/* */
|
493 |
|
|
#/* */
|
494 |
|
|
#/**********************************************************************/
|
495 |
|
|
|
496 |
|
|
print OUTFILE "(\n";
|
497 |
|
|
print OUTFILE " input wire clk,\n";
|
498 |
|
|
print OUTFILE " input wire reset,\n";
|
499 |
|
|
print OUTFILE " input wire enable,\n";
|
500 |
|
|
print OUTFILE " input wire cs,\n";
|
501 |
|
|
if($max_has_write){ print OUTFILE " input wire wr,\n";}
|
502 |
|
|
if($max_has_read) {print OUTFILE " input wire rd,\n";}
|
503 |
|
|
if($max_has_write) {print OUTFILE " input wire [${addblk_width}-1:0] wdata,\n";}
|
504 |
|
|
if($max_has_read) {print OUTFILE " output reg [${addblk_width}-1:0] rdata,\n";}
|
505 |
|
|
print OUTFILE " input wire [${sys_byte_lanes}-1:0] byte_lanes,\n";
|
506 |
|
|
print OUTFILE " input wire [${addblk_numaddbits}-1:${adr_base}] addr";
|
507 |
|
|
|
508 |
|
|
if($max_dim gt "1" )
|
509 |
|
|
{
|
510 |
|
|
print OUTFILE " ,\n output wire [${num_add}-1:0] addr_out";
|
511 |
|
|
}
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
foreach $line (@registers)
|
523 |
|
|
{
|
524 |
|
|
$_ = $line;
|
525 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
526 |
|
|
{
|
527 |
|
|
my $t_name = $1;
|
528 |
|
|
my $t_numoffset = $2;
|
529 |
|
|
my $t_size = $3;
|
530 |
|
|
my $t_numdim = $4;
|
531 |
|
|
my $t_dimbits = $5;
|
532 |
|
|
my $t_create = $6;
|
533 |
|
|
my $t_access = $7;
|
534 |
|
|
my $t_has_read = $8;
|
535 |
|
|
my $t_has_write = $9;
|
536 |
|
|
|
537 |
|
|
print OUTFILE ",\n output wire ${t_name}_cs ";
|
538 |
|
|
print OUTFILE ",\n output reg ${t_name}_dec ";
|
539 |
|
|
|
540 |
|
|
if($t_size == 1)
|
541 |
|
|
{
|
542 |
|
|
if( $t_has_read eq "1")
|
543 |
|
|
{
|
544 |
|
|
print OUTFILE ",\n input wire ${t_name}_rdata ";
|
545 |
|
|
}
|
546 |
|
|
|
547 |
|
|
if( $t_has_write eq "1")
|
548 |
|
|
{
|
549 |
|
|
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
|
550 |
|
|
if( $t_create eq "1")
|
551 |
|
|
{
|
552 |
|
|
print OUTFILE ",\n output reg $t_name ";
|
553 |
|
|
print OUTFILE ",\n input wire next_${t_name} ";
|
554 |
|
|
}
|
555 |
|
|
else
|
556 |
|
|
{
|
557 |
|
|
print OUTFILE ",\n output reg ${t_name}_wdata ";
|
558 |
|
|
}
|
559 |
|
|
}
|
560 |
|
|
}
|
561 |
|
|
|
562 |
|
|
else
|
563 |
|
|
{
|
564 |
|
|
if( $t_has_read eq "1")
|
565 |
|
|
{
|
566 |
|
|
print OUTFILE ",\n input wire [${t_size}-1:0] ${t_name}_rdata ";
|
567 |
|
|
}
|
568 |
|
|
|
569 |
|
|
if( $t_has_write eq "1")
|
570 |
|
|
{
|
571 |
|
|
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
|
572 |
|
|
if( $t_create eq "1")
|
573 |
|
|
{
|
574 |
|
|
print OUTFILE ",\n output reg [${t_size}-1:0] $t_name ";
|
575 |
|
|
print OUTFILE ",\n input wire [${t_size}-1:0] next_${t_name} ";
|
576 |
|
|
}
|
577 |
|
|
else
|
578 |
|
|
{
|
579 |
|
|
print OUTFILE ",\n output reg [${t_size}-1:0] ${t_name}_wdata ";
|
580 |
|
|
}
|
581 |
|
|
}
|
582 |
|
|
}
|
583 |
|
|
|
584 |
|
|
|
585 |
|
|
if( $t_has_write eq "1")
|
586 |
|
|
{
|
587 |
|
|
if($t_size > ${byte_size}) { print OUTFILE ",\n output reg ${t_name}_wr_1 "; }
|
588 |
|
|
if($t_size > (${byte_size}*2)) { print OUTFILE ",\n output reg ${t_name}_wr_2 "; }
|
589 |
|
|
if($t_size > (${byte_size}*3)) { print OUTFILE ",\n output reg ${t_name}_wr_3 "; }
|
590 |
|
|
}
|
591 |
|
|
}
|
592 |
|
|
}
|
593 |
|
|
|
594 |
|
|
print OUTFILE "\n);\n\n\n";
|
595 |
|
|
|
596 |
|
|
|
597 |
|
|
|
598 |
|
|
|
599 |
|
|
|
600 |
|
|
|
601 |
|
|
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
|
612 |
|
|
|
613 |
|
|
|
614 |
|
|
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
|
619 |
|
|
|
620 |
|
|
|
621 |
|
|
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
|
625 |
|
|
#/**********************************************************************/
|
626 |
|
|
#/* */
|
627 |
|
|
#/* Print parameters for register addresses */
|
628 |
|
|
#/* */
|
629 |
|
|
#/* */
|
630 |
|
|
#/**********************************************************************/
|
631 |
|
|
|
632 |
|
|
|
633 |
|
|
foreach $line (@registers)
|
634 |
|
|
{
|
635 |
|
|
$_ = $line;
|
636 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
637 |
|
|
{
|
638 |
|
|
my $t_name = $1;
|
639 |
|
|
my $t_numoffset = $2;
|
640 |
|
|
my $t_size = $3;
|
641 |
|
|
my $t_numdim = $4;
|
642 |
|
|
my $t_dimbits = $5;
|
643 |
|
|
my $t_create = $6;
|
644 |
|
|
my $t_access = $7;
|
645 |
|
|
my $t_has_read = $8;
|
646 |
|
|
my $t_has_write = $9;
|
647 |
|
|
|
648 |
|
|
print OUTFILE "parameter ";
|
649 |
|
|
print OUTFILE uc(${t_name});
|
650 |
|
|
print OUTFILE " = ${addblk_numaddbits}'d${t_numoffset};\n";
|
651 |
|
|
my $register_addressOffset_end = $t_numoffset + $t_numdim;
|
652 |
|
|
print OUTFILE "parameter ";
|
653 |
|
|
print OUTFILE uc(${t_name});
|
654 |
|
|
print OUTFILE "_END = ${addblk_numaddbits}'d${register_addressOffset_end};\n";
|
655 |
|
|
|
656 |
|
|
}
|
657 |
|
|
|
658 |
|
|
}
|
659 |
|
|
|
660 |
|
|
|
661 |
134 |
jt_eaton |
# print OUTFILE " input wire [${addblk_numaddbits}-1:${adr_base}] addr";
|
662 |
119 |
jt_eaton |
|
663 |
|
|
|
664 |
|
|
#/**********************************************************************/
|
665 |
|
|
#/* */
|
666 |
|
|
#/* write data register creation */
|
667 |
|
|
#/* */
|
668 |
|
|
#/* */
|
669 |
|
|
#/**********************************************************************/
|
670 |
|
|
|
671 |
|
|
|
672 |
|
|
|
673 |
|
|
print OUTFILE "\n\n";
|
674 |
|
|
print OUTFILE " reg [${addblk_width}-1:0] rdata_i;\n";
|
675 |
|
|
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
foreach $line (@registers)
|
679 |
|
|
{
|
680 |
|
|
$_ = $line;
|
681 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
682 |
|
|
{
|
683 |
|
|
my $t_name = $1;
|
684 |
|
|
my $t_numoffset = $2;
|
685 |
|
|
my $t_size = $3;
|
686 |
|
|
my $t_numdim = $4;
|
687 |
|
|
my $t_dimbits = $5;
|
688 |
|
|
my $t_create = $6;
|
689 |
|
|
my $t_access = $7;
|
690 |
|
|
my $t_has_read = $8;
|
691 |
|
|
my $t_has_write = $9;
|
692 |
|
|
|
693 |
|
|
if(( $t_has_write eq "1") and ( $t_create eq "1"))
|
694 |
|
|
{
|
695 |
|
|
if($t_size eq 1){ print OUTFILE "reg ${t_name}_wdata;\n";}
|
696 |
|
|
else { print OUTFILE "reg [${t_size}-1:0] ${t_name}_wdata;\n";}
|
697 |
|
|
}
|
698 |
|
|
}
|
699 |
|
|
}
|
700 |
|
|
|
701 |
|
|
|
702 |
|
|
|
703 |
|
|
|
704 |
|
|
|
705 |
|
|
|
706 |
|
|
|
707 |
|
|
|
708 |
|
|
|
709 |
|
|
|
710 |
|
|
|
711 |
|
|
|
712 |
|
|
|
713 |
|
|
|
714 |
|
|
|
715 |
|
|
|
716 |
|
|
|
717 |
|
|
|
718 |
|
|
|
719 |
|
|
#/**********************************************************************/
|
720 |
|
|
#/* */
|
721 |
|
|
#/* Set up for block width and endian */
|
722 |
|
|
#/* seperate pass for each byte lane */
|
723 |
|
|
#/* */
|
724 |
|
|
#/**********************************************************************/
|
725 |
|
|
|
726 |
|
|
|
727 |
|
|
|
728 |
|
|
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
for ($log_byte_lane =0; $log_byte_lane < $sys_byte_lanes; $log_byte_lane++)
|
732 |
|
|
{
|
733 |
|
|
if($adr_base == 2)
|
734 |
|
|
{
|
735 |
|
|
if ($opt_bigendian)
|
736 |
|
|
{
|
737 |
|
|
if ( $log_byte_lane == 0) {$phy_byte_lane = 3;}
|
738 |
|
|
elsif ( $log_byte_lane == 1) {$phy_byte_lane = 2;}
|
739 |
|
|
elsif ( $log_byte_lane == 2) {$phy_byte_lane = 1;}
|
740 |
|
|
else {$phy_byte_lane = 0;}
|
741 |
|
|
}
|
742 |
|
|
else
|
743 |
|
|
{$phy_byte_lane = $log_byte_lane}
|
744 |
|
|
}
|
745 |
|
|
|
746 |
|
|
elsif($adr_base == 1)
|
747 |
|
|
{
|
748 |
|
|
if ($opt_bigendian)
|
749 |
|
|
{
|
750 |
|
|
if ( $log_byte_lane == 0) {$phy_byte_lane = 1;}
|
751 |
|
|
else {$phy_byte_lane = 0;}
|
752 |
|
|
}
|
753 |
|
|
else
|
754 |
|
|
{$phy_byte_lane = $log_byte_lane}
|
755 |
|
|
}
|
756 |
|
|
else
|
757 |
|
|
{$phy_byte_lane = $log_byte_lane}
|
758 |
|
|
|
759 |
|
|
|
760 |
|
|
|
761 |
|
|
#/**********************************************************************/
|
762 |
|
|
#/* */
|
763 |
|
|
#/* Debug */
|
764 |
|
|
#/* */
|
765 |
|
|
#/* */
|
766 |
|
|
#/**********************************************************************/
|
767 |
|
|
|
768 |
|
|
|
769 |
|
|
print OUTFILE "/*QQQ Reg_Name Reg_Access sys_byte_lanes reg_byte_lanes reg_size reg_add ar_base log_byte_lane phy_byte_lane reg_lane pad_size padding bigend */ \n";
|
770 |
|
|
|
771 |
|
|
|
772 |
|
|
|
773 |
|
|
foreach $line (@registers)
|
774 |
|
|
{
|
775 |
|
|
$_ = $line;
|
776 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
777 |
|
|
{
|
778 |
|
|
my $t_name = $1;
|
779 |
|
|
my $t_numoffset = $2;
|
780 |
|
|
my $t_size = $3;
|
781 |
|
|
my $t_numdim = $4;
|
782 |
|
|
my $t_dimbits = $5;
|
783 |
|
|
my $t_create = $6;
|
784 |
|
|
my $t_access = $7;
|
785 |
|
|
my $t_has_read = $8;
|
786 |
|
|
my $t_has_write = $9;
|
787 |
|
|
|
788 |
|
|
|
789 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
790 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
791 |
|
|
my $pad_size = $t_size % $byte_size ;
|
792 |
|
|
|
793 |
|
|
|
794 |
|
|
|
795 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
796 |
|
|
else
|
797 |
|
|
{
|
798 |
|
|
$padding = 0;
|
799 |
|
|
$pad_size = ${byte_size};
|
800 |
|
|
}
|
801 |
|
|
|
802 |
|
|
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
|
803 |
|
|
my $strng = sprintf( "/*QQQ %16s %12s %11s %6s %6s %6s %6s %6s %6s %6s %2s %6s %6s */ \n",${t_name},${t_access},${sys_byte_lanes},${reg_byte_lanes},${t_size},${t_numoffset},${adr_base},${log_byte_lane},${phy_byte_lane},${reg_byte_lane},${pad_size},${padding},${opt_bigendian});
|
804 |
|
|
|
805 |
|
|
print OUTFILE $strng;
|
806 |
|
|
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
}
|
810 |
|
|
}
|
811 |
|
|
|
812 |
|
|
print OUTFILE "\n\n\n";
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
#/**********************************************************************/
|
820 |
|
|
#/* */
|
821 |
|
|
#/* Read Data Muxing */
|
822 |
|
|
#/* */
|
823 |
|
|
#/* */
|
824 |
|
|
#/**********************************************************************/
|
825 |
|
|
|
826 |
|
|
|
827 |
|
|
if($max_has_read == "1" and $max_has_create == "1")
|
828 |
|
|
{
|
829 |
|
|
print OUTFILE "always@(*)\n";
|
830 |
|
|
print OUTFILE " if(rd && cs)\n";
|
831 |
|
|
print OUTFILE " begin\n";
|
832 |
|
|
print OUTFILE " if(byte_lanes[ $phy_byte_lane ])\n";
|
833 |
|
|
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; \n";
|
834 |
|
|
print OUTFILE " else\n";
|
835 |
|
|
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
|
836 |
|
|
print OUTFILE " end\n";
|
837 |
|
|
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
|
838 |
|
|
|
839 |
|
|
print OUTFILE "always@(*)\n";
|
840 |
|
|
print OUTFILE " case(addr[$addblk_numaddbits-1:${adr_base}])\n";
|
841 |
|
|
|
842 |
|
|
|
843 |
|
|
|
844 |
|
|
|
845 |
|
|
|
846 |
|
|
|
847 |
|
|
|
848 |
|
|
|
849 |
|
|
foreach $line (@registers)
|
850 |
|
|
{
|
851 |
|
|
$_ = $line;
|
852 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
853 |
|
|
{
|
854 |
|
|
my $t_name = $1;
|
855 |
|
|
my $t_numoffset = $2;
|
856 |
|
|
my $t_size = $3;
|
857 |
|
|
my $t_numdim = $4;
|
858 |
|
|
my $t_dimbits = $5;
|
859 |
|
|
my $t_create = $6;
|
860 |
|
|
my $t_access = $7;
|
861 |
|
|
my $t_has_read = $8;
|
862 |
|
|
my $t_has_write = $9;
|
863 |
|
|
|
864 |
|
|
|
865 |
|
|
|
866 |
|
|
|
867 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
868 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
869 |
|
|
my $pad_size = $t_size % $byte_size ;
|
870 |
|
|
|
871 |
|
|
|
872 |
|
|
|
873 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
874 |
|
|
else
|
875 |
|
|
{
|
876 |
|
|
$padding = 0;
|
877 |
|
|
$pad_size = ${byte_size};
|
878 |
|
|
}
|
879 |
|
|
|
880 |
|
|
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
|
881 |
|
|
|
882 |
|
|
|
883 |
|
|
my $REG_NAME = uc($t_name);
|
884 |
|
|
|
885 |
|
|
|
886 |
|
|
|
887 |
|
|
if( $t_has_read eq "1" )
|
888 |
|
|
{
|
889 |
|
|
|
890 |
|
|
if(( $sys_byte_lanes eq "1" ) and ( $reg_byte_lanes eq "1") )
|
891 |
|
|
{
|
892 |
|
|
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
|
893 |
|
|
{
|
894 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
895 |
|
|
if($padding)
|
896 |
|
|
{
|
897 |
|
|
if($pad_size eq "1")
|
898 |
|
|
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
|
899 |
|
|
else
|
900 |
|
|
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n";}
|
901 |
|
|
}
|
902 |
|
|
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
|
903 |
|
|
}
|
904 |
|
|
|
905 |
|
|
|
906 |
|
|
}
|
907 |
|
|
|
908 |
|
|
elsif( $sys_byte_lanes eq $reg_byte_lanes )
|
909 |
|
|
{
|
910 |
|
|
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
|
911 |
|
|
{
|
912 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
913 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
|
914 |
|
|
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
|
915 |
|
|
}
|
916 |
|
|
else
|
917 |
|
|
{
|
918 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
919 |
|
|
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
|
920 |
|
|
}
|
921 |
|
|
}
|
922 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
|
923 |
|
|
{
|
924 |
|
|
if($opt_bigendian)
|
925 |
|
|
{
|
926 |
|
|
print OUTFILE "{";
|
927 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
928 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
929 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
930 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n"; }
|
931 |
|
|
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";}
|
932 |
|
|
}
|
933 |
|
|
else
|
934 |
|
|
{
|
935 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
936 |
|
|
print OUTFILE "${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
937 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
938 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
|
939 |
|
|
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
|
940 |
|
|
}
|
941 |
|
|
}
|
942 |
|
|
|
943 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "3"))
|
944 |
|
|
{
|
945 |
|
|
if($opt_bigendian)
|
946 |
|
|
{
|
947 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
948 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
949 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
950 |
|
|
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
|
951 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
952 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
|
953 |
|
|
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n"; }
|
954 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
955 |
|
|
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
|
956 |
|
|
}
|
957 |
|
|
else
|
958 |
|
|
{
|
959 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
960 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
961 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
962 |
|
|
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
|
963 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
964 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
|
965 |
|
|
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
|
966 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
967 |
|
|
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
|
968 |
|
|
}
|
969 |
|
|
}
|
970 |
|
|
|
971 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "4"))
|
972 |
|
|
{
|
973 |
|
|
if($opt_bigendian)
|
974 |
|
|
{
|
975 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
976 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
977 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
978 |
|
|
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
|
979 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
980 |
|
|
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
|
981 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
982 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n";}
|
983 |
|
|
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
|
984 |
|
|
}
|
985 |
|
|
else
|
986 |
|
|
{
|
987 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
988 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
989 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
990 |
|
|
print OUTFILE " ${t_name}_rdata[(${byte_size}*2)-1:${byte_size}] ;//QQQQ\n";
|
991 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
992 |
|
|
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
|
993 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
994 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n"; }
|
995 |
|
|
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
|
996 |
|
|
}
|
997 |
|
|
}
|
998 |
|
|
|
999 |
|
|
|
1000 |
|
|
|
1001 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "3") )
|
1002 |
|
|
{
|
1003 |
|
|
if($opt_bigendian)
|
1004 |
|
|
{
|
1005 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1006 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
|
1007 |
|
|
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n"; }
|
1008 |
|
|
}
|
1009 |
|
|
else
|
1010 |
|
|
{
|
1011 |
|
|
|
1012 |
|
|
|
1013 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1014 |
|
|
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
|
1015 |
|
|
|
1016 |
|
|
unless ($log_byte_lane){
|
1017 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1018 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
|
1019 |
|
|
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
|
1020 |
|
|
}
|
1021 |
|
|
|
1022 |
|
|
|
1023 |
|
|
|
1024 |
|
|
}
|
1025 |
|
|
}
|
1026 |
|
|
|
1027 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "4") )
|
1028 |
|
|
{
|
1029 |
|
|
if($opt_bigendian)
|
1030 |
|
|
{
|
1031 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1032 |
|
|
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
|
1033 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1034 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
|
1035 |
|
|
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$phy_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n"; }
|
1036 |
|
|
}
|
1037 |
|
|
else
|
1038 |
|
|
{
|
1039 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1040 |
|
|
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
|
1041 |
|
|
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1042 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
|
1043 |
|
|
else { print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n";}
|
1044 |
|
|
}
|
1045 |
|
|
}
|
1046 |
|
|
|
1047 |
|
|
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1048 |
|
|
{
|
1049 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1050 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n"; }
|
1051 |
|
|
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
|
1052 |
|
|
}
|
1053 |
|
|
|
1054 |
|
|
|
1055 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1056 |
|
|
{
|
1057 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1058 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
|
1059 |
|
|
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
|
1060 |
|
|
}
|
1061 |
|
|
|
1062 |
|
|
|
1063 |
|
|
|
1064 |
|
|
|
1065 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
|
1066 |
|
|
{
|
1067 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1068 |
|
|
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
|
1069 |
|
|
}
|
1070 |
|
|
|
1071 |
|
|
|
1072 |
|
|
|
1073 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
|
1074 |
|
|
{
|
1075 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1076 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
|
1077 |
|
|
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
|
1078 |
|
|
}
|
1079 |
|
|
|
1080 |
|
|
|
1081 |
|
|
|
1082 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($phy_byte_lane) ne "3" )
|
1083 |
|
|
{
|
1084 |
|
|
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
|
1085 |
|
|
{
|
1086 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1087 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
|
1088 |
|
|
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
|
1089 |
|
|
}
|
1090 |
|
|
else
|
1091 |
|
|
{
|
1092 |
|
|
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
|
1093 |
|
|
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
|
1094 |
|
|
}
|
1095 |
|
|
}
|
1096 |
|
|
|
1097 |
|
|
}
|
1098 |
|
|
}
|
1099 |
|
|
|
1100 |
|
|
}
|
1101 |
|
|
|
1102 |
|
|
print OUTFILE "\n\n\n";
|
1103 |
|
|
print OUTFILE " default: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
|
1104 |
|
|
print OUTFILE " endcase\n\n";
|
1105 |
|
|
|
1106 |
|
|
|
1107 |
|
|
|
1108 |
|
|
|
1109 |
|
|
}
|
1110 |
|
|
|
1111 |
|
|
|
1112 |
|
|
|
1113 |
|
|
|
1114 |
|
|
|
1115 |
|
|
|
1116 |
|
|
|
1117 |
|
|
|
1118 |
|
|
|
1119 |
|
|
|
1120 |
|
|
|
1121 |
|
|
|
1122 |
|
|
|
1123 |
|
|
|
1124 |
|
|
#/**********************************************************************/
|
1125 |
|
|
#/* */
|
1126 |
|
|
#/* Read Data Muxing */
|
1127 |
|
|
#/* */
|
1128 |
|
|
#/* */
|
1129 |
|
|
#/**********************************************************************/
|
1130 |
|
|
|
1131 |
|
|
|
1132 |
|
|
if($max_has_read == "1" and $max_has_create == "0" )
|
1133 |
|
|
{
|
1134 |
|
|
print OUTFILE "always@(*)\n";
|
1135 |
|
|
print OUTFILE " if(rd && cs)\n";
|
1136 |
|
|
print OUTFILE " begin\n";
|
1137 |
|
|
print OUTFILE " if(byte_lanes[ $phy_byte_lane ])\n";
|
1138 |
|
|
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; \n";
|
1139 |
|
|
print OUTFILE " else\n";
|
1140 |
|
|
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
|
1141 |
|
|
print OUTFILE " end\n";
|
1142 |
|
|
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
|
1143 |
|
|
|
1144 |
|
|
print OUTFILE "always@(*)\n";
|
1145 |
|
|
print OUTFILE " begin\n";
|
1146 |
|
|
print OUTFILE " rdata_i = UNMAPPED;\n";
|
1147 |
|
|
|
1148 |
|
|
|
1149 |
|
|
foreach $line (@registers)
|
1150 |
|
|
{
|
1151 |
|
|
$_ = $line;
|
1152 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1153 |
|
|
{
|
1154 |
|
|
my $t_name = $1;
|
1155 |
|
|
my $t_numoffset = $2;
|
1156 |
|
|
my $t_size = $3;
|
1157 |
|
|
my $t_numdim = $4;
|
1158 |
|
|
my $t_dimbits = $5;
|
1159 |
|
|
my $t_create = $6;
|
1160 |
|
|
my $t_access = $7;
|
1161 |
|
|
my $t_has_read = $8;
|
1162 |
|
|
my $t_has_write = $9;
|
1163 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1164 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1165 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1166 |
|
|
|
1167 |
|
|
|
1168 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1169 |
|
|
else
|
1170 |
|
|
{
|
1171 |
|
|
$padding = 0;
|
1172 |
|
|
$pad_size = ${byte_size};
|
1173 |
|
|
}
|
1174 |
|
|
|
1175 |
|
|
|
1176 |
|
|
my $REG_NAME = uc($t_name);
|
1177 |
|
|
|
1178 |
|
|
|
1179 |
|
|
|
1180 |
|
|
|
1181 |
|
|
|
1182 |
|
|
if( $t_has_read eq "1" )
|
1183 |
|
|
{
|
1184 |
|
|
print OUTFILE "if( ${t_name}_cs ) rdata_i = ";
|
1185 |
|
|
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
|
1186 |
|
|
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n";}
|
1187 |
|
|
}
|
1188 |
|
|
|
1189 |
|
|
|
1190 |
|
|
|
1191 |
|
|
|
1192 |
|
|
|
1193 |
|
|
print OUTFILE "\n";
|
1194 |
|
|
|
1195 |
|
|
|
1196 |
|
|
|
1197 |
|
|
}
|
1198 |
|
|
|
1199 |
|
|
|
1200 |
|
|
}
|
1201 |
|
|
|
1202 |
|
|
print OUTFILE " end\n\n";
|
1203 |
|
|
|
1204 |
|
|
|
1205 |
|
|
}
|
1206 |
|
|
|
1207 |
|
|
|
1208 |
|
|
|
1209 |
|
|
|
1210 |
|
|
|
1211 |
|
|
|
1212 |
|
|
|
1213 |
|
|
|
1214 |
|
|
|
1215 |
|
|
|
1216 |
|
|
|
1217 |
|
|
|
1218 |
|
|
|
1219 |
|
|
|
1220 |
|
|
|
1221 |
|
|
|
1222 |
|
|
|
1223 |
|
|
|
1224 |
|
|
|
1225 |
|
|
|
1226 |
|
|
|
1227 |
|
|
|
1228 |
|
|
|
1229 |
|
|
|
1230 |
|
|
|
1231 |
|
|
|
1232 |
|
|
|
1233 |
|
|
|
1234 |
|
|
|
1235 |
|
|
|
1236 |
|
|
|
1237 |
|
|
|
1238 |
|
|
|
1239 |
|
|
|
1240 |
|
|
|
1241 |
|
|
|
1242 |
|
|
|
1243 |
|
|
|
1244 |
|
|
|
1245 |
|
|
#/**********************************************************************/
|
1246 |
|
|
#/* */
|
1247 |
|
|
#/* Write Data Selection */
|
1248 |
|
|
#/* */
|
1249 |
|
|
#/* */
|
1250 |
|
|
#/**********************************************************************/
|
1251 |
|
|
|
1252 |
|
|
|
1253 |
|
|
|
1254 |
|
|
if($max_has_write)
|
1255 |
|
|
{
|
1256 |
|
|
|
1257 |
|
|
print OUTFILE "always@(*)\n";
|
1258 |
|
|
print OUTFILE " begin\n";
|
1259 |
|
|
|
1260 |
|
|
foreach $line (@registers)
|
1261 |
|
|
{
|
1262 |
|
|
$_ = $line;
|
1263 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1264 |
|
|
{
|
1265 |
|
|
my $t_name = $1;
|
1266 |
|
|
my $t_numoffset = $2;
|
1267 |
|
|
my $t_size = $3;
|
1268 |
|
|
my $t_numdim = $4;
|
1269 |
|
|
my $t_dimbits = $5;
|
1270 |
|
|
my $t_create = $6;
|
1271 |
|
|
my $t_access = $7;
|
1272 |
|
|
my $t_has_read = $8;
|
1273 |
|
|
my $t_has_write = $9;
|
1274 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1275 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1276 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1277 |
|
|
|
1278 |
|
|
|
1279 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1280 |
|
|
else
|
1281 |
|
|
{
|
1282 |
|
|
$padding = 0;
|
1283 |
|
|
$pad_size = ${byte_size};
|
1284 |
|
|
}
|
1285 |
|
|
|
1286 |
|
|
|
1287 |
|
|
my $REG_NAME = uc($t_name);
|
1288 |
|
|
|
1289 |
|
|
|
1290 |
|
|
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
|
1291 |
|
|
|
1292 |
|
|
|
1293 |
|
|
|
1294 |
|
|
|
1295 |
|
|
if( $t_has_write eq "1" )
|
1296 |
|
|
{
|
1297 |
|
|
if ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "1"))
|
1298 |
|
|
{
|
1299 |
|
|
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0];// 1\n";
|
1300 |
|
|
}
|
1301 |
|
|
|
1302 |
|
|
elsif( $sys_byte_lanes eq $reg_byte_lanes )
|
1303 |
|
|
{
|
1304 |
|
|
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
|
1305 |
|
|
{
|
1306 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}];// 2\n";
|
1307 |
|
|
|
1308 |
|
|
}
|
1309 |
|
|
else
|
1310 |
|
|
{
|
1311 |
|
|
|
1312 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 3 \n";
|
1313 |
|
|
}
|
1314 |
|
|
}
|
1315 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
|
1316 |
|
|
{
|
1317 |
|
|
if($opt_bigendian)
|
1318 |
|
|
{
|
1319 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:0]; // 4 \n";
|
1320 |
|
|
|
1321 |
|
|
|
1322 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 5 \n";
|
1323 |
|
|
|
1324 |
|
|
}
|
1325 |
|
|
else
|
1326 |
|
|
{
|
1327 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 6 \n";
|
1328 |
|
|
|
1329 |
|
|
|
1330 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // ${byte_size}-1 \n";
|
1331 |
|
|
|
1332 |
|
|
}
|
1333 |
|
|
}
|
1334 |
|
|
|
1335 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "3"))
|
1336 |
|
|
{
|
1337 |
|
|
if($opt_bigendian)
|
1338 |
|
|
{
|
1339 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 8 \n";
|
1340 |
|
|
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 9 \n";
|
1341 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 10 \n";
|
1342 |
|
|
}
|
1343 |
|
|
else
|
1344 |
|
|
{
|
1345 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 11 \n";
|
1346 |
|
|
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 12 \n";
|
1347 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 13 \n";
|
1348 |
|
|
}
|
1349 |
|
|
}
|
1350 |
|
|
|
1351 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "4"))
|
1352 |
|
|
{
|
1353 |
|
|
if($opt_bigendian)
|
1354 |
|
|
{
|
1355 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 14 \n";
|
1356 |
|
|
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 15 \n";
|
1357 |
|
|
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 16 \n";
|
1358 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 17 \n";
|
1359 |
|
|
|
1360 |
|
|
}
|
1361 |
|
|
else
|
1362 |
|
|
{
|
1363 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 18 \n";
|
1364 |
|
|
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 19 \n";
|
1365 |
|
|
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 20 \n";
|
1366 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 21 \n";
|
1367 |
|
|
}
|
1368 |
|
|
}
|
1369 |
|
|
|
1370 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "3") )
|
1371 |
|
|
{
|
1372 |
|
|
if($opt_bigendian)
|
1373 |
|
|
{
|
1374 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 22 \n";
|
1375 |
|
|
}
|
1376 |
|
|
else
|
1377 |
|
|
{
|
1378 |
|
|
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
|
1379 |
|
|
if($log_byte_lane == 0)
|
1380 |
|
|
{
|
1381 |
|
|
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
|
1382 |
|
|
}
|
1383 |
|
|
}
|
1384 |
|
|
}
|
1385 |
|
|
|
1386 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "4") )
|
1387 |
|
|
{
|
1388 |
|
|
if($opt_bigendian)
|
1389 |
|
|
{
|
1390 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 24 \n";
|
1391 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1+$(byte_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 25 \n";
|
1392 |
|
|
}
|
1393 |
|
|
else
|
1394 |
|
|
{
|
1395 |
|
|
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 26 \n";
|
1396 |
|
|
if($log_byte_lane)
|
1397 |
|
|
{
|
1398 |
|
|
|
1399 |
|
|
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
|
1400 |
|
|
}
|
1401 |
|
|
else
|
1402 |
|
|
{
|
1403 |
|
|
|
1404 |
|
|
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
|
1405 |
|
|
}
|
1406 |
|
|
|
1407 |
|
|
}
|
1408 |
|
|
}
|
1409 |
|
|
|
1410 |
|
|
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1411 |
|
|
{
|
1412 |
|
|
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 28 \n";
|
1413 |
|
|
}
|
1414 |
|
|
|
1415 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1416 |
|
|
{
|
1417 |
|
|
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 29 \n";
|
1418 |
|
|
}
|
1419 |
|
|
|
1420 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
|
1421 |
|
|
{
|
1422 |
|
|
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 30 \n";
|
1423 |
|
|
}
|
1424 |
|
|
|
1425 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
|
1426 |
|
|
{
|
1427 |
|
|
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // \n";
|
1428 |
|
|
}
|
1429 |
|
|
|
1430 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($phy_byte_lane) ne "3" )
|
1431 |
|
|
{
|
1432 |
|
|
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
|
1433 |
|
|
{
|
1434 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 32 \n";
|
1435 |
|
|
}
|
1436 |
|
|
else
|
1437 |
|
|
{
|
1438 |
|
|
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 33 \n";
|
1439 |
|
|
}
|
1440 |
|
|
}
|
1441 |
|
|
|
1442 |
|
|
}
|
1443 |
|
|
}
|
1444 |
|
|
|
1445 |
|
|
}
|
1446 |
|
|
|
1447 |
|
|
print OUTFILE "\n\n\n";
|
1448 |
|
|
print OUTFILE " end\n\n";
|
1449 |
|
|
|
1450 |
|
|
|
1451 |
|
|
|
1452 |
|
|
|
1453 |
|
|
|
1454 |
|
|
#/**********************************************************************/
|
1455 |
|
|
#/* */
|
1456 |
|
|
#/* Write strobe Creation */
|
1457 |
|
|
#/* */
|
1458 |
|
|
#/* */
|
1459 |
|
|
#/**********************************************************************/
|
1460 |
|
|
|
1461 |
|
|
|
1462 |
|
|
|
1463 |
|
|
print OUTFILE "always@(*)\n";
|
1464 |
|
|
print OUTFILE " begin\n";
|
1465 |
|
|
|
1466 |
|
|
|
1467 |
|
|
|
1468 |
|
|
foreach $line (@registers)
|
1469 |
|
|
{
|
1470 |
|
|
$_ = $line;
|
1471 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1472 |
|
|
{
|
1473 |
|
|
my $t_name = $1;
|
1474 |
|
|
my $t_numoffset = $2;
|
1475 |
|
|
my $t_size = $3;
|
1476 |
|
|
my $t_numdim = $4;
|
1477 |
|
|
my $t_dimbits = $5;
|
1478 |
|
|
my $t_create = $6;
|
1479 |
|
|
my $t_access = $7;
|
1480 |
|
|
my $t_has_read = $8;
|
1481 |
|
|
my $t_has_write = $9;
|
1482 |
|
|
|
1483 |
|
|
|
1484 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1485 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1486 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1487 |
|
|
|
1488 |
|
|
|
1489 |
|
|
|
1490 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1491 |
|
|
else
|
1492 |
|
|
{
|
1493 |
|
|
$padding = 0;
|
1494 |
|
|
$pad_size = ${byte_size};
|
1495 |
|
|
}
|
1496 |
|
|
|
1497 |
|
|
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
|
1498 |
|
|
|
1499 |
|
|
|
1500 |
|
|
|
1501 |
|
|
my $REG_NAME = uc($t_name);
|
1502 |
|
|
|
1503 |
|
|
|
1504 |
|
|
|
1505 |
|
|
|
1506 |
|
|
|
1507 |
|
|
|
1508 |
|
|
|
1509 |
|
|
|
1510 |
|
|
if( $t_has_write eq "1" )
|
1511 |
|
|
{
|
1512 |
|
|
if ( $sys_byte_lanes eq $reg_byte_lanes )
|
1513 |
|
|
{
|
1514 |
|
|
print OUTFILE "${t_name}_wr_${phy_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
|
1515 |
|
|
}
|
1516 |
|
|
|
1517 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
|
1518 |
|
|
{
|
1519 |
|
|
if($opt_bigendian)
|
1520 |
|
|
{
|
1521 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
|
1522 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
|
1523 |
|
|
|
1524 |
|
|
}
|
1525 |
|
|
else
|
1526 |
|
|
{
|
1527 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
|
1528 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
|
1529 |
|
|
}
|
1530 |
|
|
}
|
1531 |
|
|
|
1532 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "3"))
|
1533 |
|
|
{
|
1534 |
|
|
if($opt_bigendian)
|
1535 |
|
|
{
|
1536 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
|
1537 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
|
1538 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
|
1539 |
|
|
}
|
1540 |
|
|
else
|
1541 |
|
|
{
|
1542 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
|
1543 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
|
1544 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
|
1545 |
|
|
}
|
1546 |
|
|
}
|
1547 |
|
|
|
1548 |
|
|
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "4"))
|
1549 |
|
|
{
|
1550 |
|
|
if($opt_bigendian)
|
1551 |
|
|
{
|
1552 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
|
1553 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
|
1554 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
|
1555 |
|
|
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
|
1556 |
|
|
}
|
1557 |
|
|
else
|
1558 |
|
|
{
|
1559 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
|
1560 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
|
1561 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
|
1562 |
|
|
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
|
1563 |
|
|
|
1564 |
|
|
}
|
1565 |
|
|
}
|
1566 |
|
|
|
1567 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "3") )
|
1568 |
|
|
{
|
1569 |
|
|
if ($log_byte_lane == 0 )
|
1570 |
|
|
{
|
1571 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
|
1572 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
|
1573 |
|
|
}
|
1574 |
|
|
elsif ($log_byte_lane == 1 )
|
1575 |
|
|
{
|
1576 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
|
1577 |
|
|
}
|
1578 |
|
|
}
|
1579 |
|
|
|
1580 |
|
|
|
1581 |
|
|
|
1582 |
|
|
elsif ( ($sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "4") )
|
1583 |
|
|
{
|
1584 |
|
|
if ($log_byte_lane == 0 )
|
1585 |
|
|
{
|
1586 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
|
1587 |
|
|
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
|
1588 |
|
|
}
|
1589 |
|
|
elsif ($log_byte_lane == 1 )
|
1590 |
|
|
{
|
1591 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
|
1592 |
|
|
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
|
1593 |
|
|
}
|
1594 |
|
|
}
|
1595 |
|
|
|
1596 |
|
|
|
1597 |
|
|
|
1598 |
|
|
|
1599 |
|
|
|
1600 |
|
|
|
1601 |
|
|
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1602 |
|
|
{
|
1603 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
|
1604 |
|
|
}
|
1605 |
|
|
|
1606 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
|
1607 |
|
|
{
|
1608 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
|
1609 |
|
|
}
|
1610 |
|
|
|
1611 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
|
1612 |
|
|
{
|
1613 |
|
|
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
|
1614 |
|
|
}
|
1615 |
|
|
|
1616 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
|
1617 |
|
|
{
|
1618 |
|
|
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
|
1619 |
|
|
}
|
1620 |
|
|
|
1621 |
|
|
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($log_byte_lane ne "3") )
|
1622 |
|
|
{
|
1623 |
|
|
if( ${reg_byte_lanes}-1 == $log_byte_lane )
|
1624 |
|
|
{
|
1625 |
|
|
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
|
1626 |
|
|
}
|
1627 |
|
|
else
|
1628 |
|
|
{
|
1629 |
|
|
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
|
1630 |
|
|
}
|
1631 |
|
|
}
|
1632 |
|
|
|
1633 |
|
|
}
|
1634 |
|
|
}
|
1635 |
|
|
|
1636 |
|
|
|
1637 |
|
|
}
|
1638 |
|
|
print OUTFILE "\n\n\n";
|
1639 |
|
|
print OUTFILE " end\n\n";
|
1640 |
|
|
|
1641 |
|
|
|
1642 |
|
|
}
|
1643 |
|
|
|
1644 |
|
|
|
1645 |
|
|
|
1646 |
|
|
|
1647 |
|
|
|
1648 |
|
|
|
1649 |
|
|
|
1650 |
|
|
|
1651 |
|
|
|
1652 |
|
|
|
1653 |
|
|
|
1654 |
|
|
|
1655 |
|
|
|
1656 |
|
|
|
1657 |
|
|
|
1658 |
|
|
|
1659 |
|
|
|
1660 |
|
|
|
1661 |
|
|
#/**********************************************************************/
|
1662 |
|
|
#/* */
|
1663 |
|
|
#/* Print read strobes */
|
1664 |
|
|
#/* */
|
1665 |
|
|
#/* */
|
1666 |
|
|
#/**********************************************************************/
|
1667 |
|
|
|
1668 |
|
|
|
1669 |
|
|
|
1670 |
|
|
|
1671 |
|
|
|
1672 |
|
|
foreach $line (@registers)
|
1673 |
|
|
{
|
1674 |
|
|
$_ = $line;
|
1675 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1676 |
|
|
{
|
1677 |
|
|
my $t_name = $1;
|
1678 |
|
|
my $t_numoffset = $2;
|
1679 |
|
|
my $t_size = $3;
|
1680 |
|
|
my $t_numdim = $4;
|
1681 |
|
|
my $t_dimbits = $5;
|
1682 |
|
|
my $t_create = $6;
|
1683 |
|
|
my $t_access = $7;
|
1684 |
|
|
my $t_has_read = $8;
|
1685 |
|
|
my $t_has_write = $9;
|
1686 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1687 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1688 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1689 |
|
|
|
1690 |
|
|
|
1691 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1692 |
|
|
else
|
1693 |
|
|
{
|
1694 |
|
|
$padding = 0;
|
1695 |
|
|
$pad_size = ${byte_size};
|
1696 |
|
|
}
|
1697 |
|
|
|
1698 |
|
|
|
1699 |
|
|
my $REG_NAME = uc($t_name);
|
1700 |
|
|
|
1701 |
|
|
|
1702 |
|
|
|
1703 |
|
|
|
1704 |
|
|
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
|
1705 |
|
|
|
1706 |
|
|
|
1707 |
|
|
|
1708 |
|
|
|
1709 |
|
|
|
1710 |
|
|
|
1711 |
|
|
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
|
1712 |
|
|
{
|
1713 |
|
|
|
1714 |
|
|
}
|
1715 |
|
|
|
1716 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 2))
|
1717 |
|
|
{
|
1718 |
|
|
|
1719 |
|
|
}
|
1720 |
|
|
|
1721 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 3))
|
1722 |
|
|
{
|
1723 |
|
|
|
1724 |
|
|
}
|
1725 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 4))
|
1726 |
|
|
{
|
1727 |
|
|
|
1728 |
|
|
}
|
1729 |
|
|
elsif ( ( $sys_byte_lanes == 2) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
|
1730 |
|
|
{
|
1731 |
|
|
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
|
1732 |
|
|
}
|
1733 |
|
|
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
|
1734 |
|
|
{
|
1735 |
|
|
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
|
1736 |
|
|
}
|
1737 |
|
|
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 2) and ( $log_byte_lane == $reg_byte_lane) )
|
1738 |
|
|
{
|
1739 |
|
|
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
|
1740 |
|
|
}
|
1741 |
|
|
}
|
1742 |
|
|
}
|
1743 |
|
|
|
1744 |
|
|
}
|
1745 |
|
|
|
1746 |
|
|
|
1747 |
|
|
|
1748 |
|
|
|
1749 |
|
|
|
1750 |
|
|
|
1751 |
|
|
|
1752 |
|
|
|
1753 |
|
|
|
1754 |
|
|
|
1755 |
|
|
foreach $line (@registers)
|
1756 |
|
|
{
|
1757 |
|
|
$_ = $line;
|
1758 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1759 |
|
|
{
|
1760 |
|
|
my $t_name = $1;
|
1761 |
|
|
my $t_numoffset = $2;
|
1762 |
|
|
my $t_size = $3;
|
1763 |
|
|
my $t_numdim = $4;
|
1764 |
|
|
my $t_dimbits = $5;
|
1765 |
|
|
my $t_create = $6;
|
1766 |
|
|
my $t_access = $7;
|
1767 |
|
|
my $t_has_read = $8;
|
1768 |
|
|
my $t_has_write = $9;
|
1769 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1770 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1771 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1772 |
|
|
|
1773 |
|
|
|
1774 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1775 |
|
|
else
|
1776 |
|
|
{
|
1777 |
|
|
$padding = 0;
|
1778 |
|
|
$pad_size = ${byte_size};
|
1779 |
|
|
}
|
1780 |
|
|
my $REG_NAME = uc($t_name);
|
1781 |
|
|
|
1782 |
|
|
|
1783 |
|
|
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
|
1784 |
|
|
|
1785 |
|
|
|
1786 |
|
|
|
1787 |
|
|
|
1788 |
|
|
|
1789 |
|
|
|
1790 |
|
|
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
|
1791 |
|
|
{
|
1792 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:0]== ${REG_NAME}[$addblk_numaddbits-1:0] );// 1\n"
|
1793 |
|
|
}
|
1794 |
|
|
|
1795 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 2))
|
1796 |
|
|
{
|
1797 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 2\n"
|
1798 |
|
|
}
|
1799 |
|
|
|
1800 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 3))
|
1801 |
|
|
{
|
1802 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 3\n"
|
1803 |
|
|
}
|
1804 |
|
|
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 4))
|
1805 |
|
|
{
|
1806 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
|
1807 |
|
|
}
|
1808 |
|
|
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 2))
|
1809 |
|
|
{
|
1810 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 4\n"
|
1811 |
|
|
}
|
1812 |
|
|
|
1813 |
|
|
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 3))
|
1814 |
|
|
{
|
1815 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
|
1816 |
|
|
}
|
1817 |
|
|
|
1818 |
|
|
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 4))
|
1819 |
|
|
{
|
1820 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
|
1821 |
|
|
}
|
1822 |
|
|
|
1823 |
|
|
|
1824 |
|
|
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 3))
|
1825 |
|
|
{
|
1826 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
|
1827 |
|
|
}
|
1828 |
|
|
|
1829 |
|
|
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 4))
|
1830 |
|
|
{
|
1831 |
|
|
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
|
1832 |
|
|
}
|
1833 |
|
|
|
1834 |
|
|
|
1835 |
|
|
|
1836 |
|
|
|
1837 |
|
|
}
|
1838 |
|
|
|
1839 |
|
|
}
|
1840 |
|
|
|
1841 |
|
|
print OUTFILE "\n\n always@(*)\n begin\n";
|
1842 |
|
|
foreach my $add_line (@add_decs)
|
1843 |
|
|
{
|
1844 |
|
|
print OUTFILE "${add_line}";
|
1845 |
|
|
}
|
1846 |
|
|
|
1847 |
|
|
print OUTFILE "\n end\n\n";
|
1848 |
|
|
|
1849 |
|
|
|
1850 |
|
|
|
1851 |
|
|
|
1852 |
|
|
|
1853 |
|
|
|
1854 |
|
|
|
1855 |
|
|
|
1856 |
|
|
|
1857 |
|
|
|
1858 |
|
|
|
1859 |
|
|
|
1860 |
|
|
|
1861 |
|
|
|
1862 |
|
|
|
1863 |
|
|
|
1864 |
|
|
|
1865 |
|
|
|
1866 |
|
|
|
1867 |
|
|
#/**********************************************************************/
|
1868 |
|
|
#/* */
|
1869 |
|
|
#/* Create Chip Selects */
|
1870 |
|
|
#/* */
|
1871 |
|
|
#/* */
|
1872 |
|
|
#/**********************************************************************/
|
1873 |
|
|
|
1874 |
|
|
print OUTFILE "\n /* verilator lint_off UNSIGNED */ \n";
|
1875 |
|
|
|
1876 |
|
|
foreach $line (@registers)
|
1877 |
|
|
{
|
1878 |
|
|
$_ = $line;
|
1879 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1880 |
|
|
{
|
1881 |
|
|
my $t_name = $1;
|
1882 |
|
|
my $t_numoffset = $2;
|
1883 |
|
|
my $t_size = $3;
|
1884 |
|
|
my $t_numdim = $4;
|
1885 |
|
|
my $t_dimbits = $5;
|
1886 |
|
|
my $t_create = $6;
|
1887 |
|
|
my $t_access = $7;
|
1888 |
|
|
my $t_has_read = $8;
|
1889 |
|
|
my $t_has_write = $9;
|
1890 |
|
|
my $REG_NAME = uc($t_name);
|
1891 |
134 |
jt_eaton |
print OUTFILE "assign ${t_name}_cs = cs && ( addr[$addblk_numaddbits-1:${adr_base}] >= ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ) && ( addr[$addblk_numaddbits-1:${adr_base}] < ${REG_NAME}_END[$addblk_numaddbits-1:${adr_base}] );\n";
|
1892 |
119 |
jt_eaton |
}
|
1893 |
|
|
}
|
1894 |
|
|
|
1895 |
|
|
|
1896 |
|
|
print OUTFILE "\n /* verilator lint_on UNSIGNED */ \n";
|
1897 |
|
|
|
1898 |
|
|
|
1899 |
|
|
|
1900 |
|
|
|
1901 |
|
|
|
1902 |
|
|
|
1903 |
|
|
#/**********************************************************************/
|
1904 |
|
|
#/* */
|
1905 |
|
|
#/* Create Registers */
|
1906 |
|
|
#/* */
|
1907 |
|
|
#/* */
|
1908 |
|
|
#/**********************************************************************/
|
1909 |
|
|
|
1910 |
|
|
foreach $line (@registers)
|
1911 |
|
|
{
|
1912 |
|
|
$_ = $line;
|
1913 |
|
|
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
|
1914 |
|
|
{
|
1915 |
|
|
my $t_name = $1;
|
1916 |
|
|
my $t_numoffset = $2;
|
1917 |
|
|
my $t_size = $3;
|
1918 |
|
|
my $t_numdim = $4;
|
1919 |
|
|
my $t_dimbits = $5;
|
1920 |
|
|
my $t_create = $6;
|
1921 |
|
|
my $t_access = $7;
|
1922 |
|
|
my $t_has_read = $8;
|
1923 |
|
|
my $t_has_write = $9;
|
1924 |
|
|
|
1925 |
|
|
|
1926 |
|
|
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
|
1927 |
|
|
my $reg_byte_lanes = $t_size / ${byte_size} ;
|
1928 |
|
|
my $pad_size = $t_size % $byte_size ;
|
1929 |
|
|
|
1930 |
|
|
|
1931 |
|
|
|
1932 |
|
|
if($pad_size) {$padding = $byte_size - $pad_size;}
|
1933 |
|
|
else
|
1934 |
|
|
{
|
1935 |
|
|
$padding = 0;
|
1936 |
|
|
$pad_size = ${byte_size};
|
1937 |
|
|
}
|
1938 |
|
|
|
1939 |
|
|
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
|
1940 |
|
|
|
1941 |
|
|
|
1942 |
|
|
if(( $t_has_write eq "1") and ( $t_create eq "1") )
|
1943 |
|
|
{
|
1944 |
|
|
print OUTFILE " always@(posedge clk)\n if(reset) $t_name <= ";
|
1945 |
|
|
print OUTFILE uc($t_name);
|
1946 |
|
|
print OUTFILE "_RST;\n else\n begin\n";
|
1947 |
|
|
|
1948 |
|
|
if($reg_byte_lanes == 1)
|
1949 |
|
|
{
|
1950 |
|
|
if($pad_size ==1)
|
1951 |
|
|
{
|
1952 |
|
|
print OUTFILE " if(${t_name}_wr_0) ${t_name} <= ${t_name}_wdata ;\n";
|
1953 |
|
|
print OUTFILE " else ${t_name} <= next_${t_name};\n\n";
|
1954 |
|
|
}
|
1955 |
|
|
else
|
1956 |
|
|
{
|
1957 |
|
|
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${pad_size}-1:0] <= ${t_name}_wdata[${pad_size}-1:0] ;\n";
|
1958 |
|
|
print OUTFILE " else ${t_name}[${pad_size}-1:0] <= next_${t_name}[${pad_size}-1:0];\n\n";
|
1959 |
|
|
}
|
1960 |
|
|
|
1961 |
|
|
}
|
1962 |
|
|
elsif($reg_byte_lanes == 2)
|
1963 |
|
|
{
|
1964 |
|
|
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
|
1965 |
|
|
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
|
1966 |
|
|
print OUTFILE " if(${t_name}_wr_1) ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= ${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] ;\n";
|
1967 |
|
|
print OUTFILE " else ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= next_${t_name}[${pad_size}+${byte_size}-1:${byte_size}];\n\n";
|
1968 |
|
|
}
|
1969 |
|
|
elsif($reg_byte_lanes == 3)
|
1970 |
|
|
{
|
1971 |
|
|
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
|
1972 |
|
|
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
|
1973 |
|
|
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
|
1974 |
|
|
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
|
1975 |
|
|
print OUTFILE " if(${t_name}_wr_2) ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= ${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] ;\n";
|
1976 |
|
|
print OUTFILE " else ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= next_${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)];\n\n";
|
1977 |
|
|
}
|
1978 |
|
|
elsif($reg_byte_lanes == 4)
|
1979 |
|
|
{
|
1980 |
|
|
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
|
1981 |
|
|
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
|
1982 |
|
|
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
|
1983 |
|
|
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
|
1984 |
|
|
print OUTFILE " if(${t_name}_wr_2) ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= ${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] ;\n";
|
1985 |
|
|
print OUTFILE " else ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= next_${t_name}[(${byte_size}*3)-1:(${byte_size}*2)];\n\n";
|
1986 |
|
|
print OUTFILE " if(${t_name}_wr_3) ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= ${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] ;\n";
|
1987 |
|
|
print OUTFILE " else ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= next_${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)];\n\n";
|
1988 |
|
|
}
|
1989 |
|
|
|
1990 |
|
|
print OUTFILE "\n end\n\n";
|
1991 |
|
|
|
1992 |
|
|
|
1993 |
|
|
}
|
1994 |
|
|
|
1995 |
|
|
|
1996 |
|
|
|
1997 |
|
|
|
1998 |
|
|
|
1999 |
|
|
|
2000 |
|
|
}
|
2001 |
|
|
|
2002 |
|
|
}
|
2003 |
|
|
|
2004 |
|
|
|
2005 |
|
|
|
2006 |
|
|
|
2007 |
|
|
|
2008 |
|
|
|
2009 |
|
|
|
2010 |
|
|
|
2011 |
|
|
|
2012 |
|
|
|
2013 |
|
|
|
2014 |
|
|
|
2015 |
|
|
|
2016 |
|
|
|
2017 |
|
|
|
2018 |
|
|
|
2019 |
|
|
|
2020 |
|
|
|
2021 |
|
|
|
2022 |
|
|
print OUTFILE "\nendmodule \n";
|
2023 |
|
|
|
2024 |
|
|
|
2025 |
|
|
|
2026 |
|
|
|
2027 |
|
|
|
2028 |
|
|
|
2029 |
|
|
|
2030 |
|
|
close OUTFILE ;
|
2031 |
|
|
|
2032 |
|
|
|
2033 |
|
|
1
|
2034 |
|
|
|
2035 |
|
|
|