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[/] [socgen/] [trunk/] [tools/] [simulation/] [run_sims] - Blame information for rev 129

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Line No. Rev Author Line
1 119 jt_eaton
eval 'exec `which perl` -S $0 ${1+"$@"}'
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   if 0;
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#/**********************************************************************/
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#/*                                                                    */
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#/*             -------                                                */
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#/*            /   SOC  \                                              */
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#/*           /    GEN   \                                             */
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#/*          /    TOOL    \                                            */
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#/*          ==============                                            */
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#/*          |            |                                            */
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#/*          |____________|                                            */
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#/*                                                                    */
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#/*                                                                    */
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#/*                                                                    */
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#/*  Author(s):                                                        */
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#/*      - John Eaton, jt_eaton@opencores.org                          */
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#/*                                                                    */
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#/**********************************************************************/
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#/*                                                                    */
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#/*    Copyright (C) <2010-2011>                */
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#/*                                                                    */
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#/*  This source file may be used and distributed without              */
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#/*  restriction provided that this copyright statement is not         */
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#/*  removed from the file and that any derivative work contains       */
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#/*  the original copyright notice and the associated disclaimer.      */
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#/*                                                                    */
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#/*  This source file is free software; you can redistribute it        */
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#/*  and/or modify it under the terms of the GNU Lesser General        */
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#/*  Public License as published by the Free Software Foundation;      */
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#/*  either version 2.1 of the License, or (at your option) any        */
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#/*  later version.                                                    */
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#/*                                                                    */
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#/*  This source is distributed in the hope that it will be            */
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#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
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#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
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#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
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#/*  details.                                                          */
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#/*                                                                    */
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#/*  You should have received a copy of the GNU Lesser General         */
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#/*  Public License along with this source; if not, download it        */
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#/*  from http://www.opencores.org/lgpl.shtml                          */
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#/*                                                                    */
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#/**********************************************************************/
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############################################################################
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# General PERL config
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############################################################################
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use Getopt::Long;
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use English;
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use File::Basename;
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use Cwd;
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use XML::LibXML;
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use lib './tools';
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use sys::lib;
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use yp::lib;
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$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
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############################################################################
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### Process the options
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############################################################################
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Getopt::Long::config("require_order", "prefix=-");
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GetOptions("h","help",
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) || die "(use '$program_name -h' for help)";
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##############################################################################
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## Help option
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##############################################################################
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if ( $opt_h or $opt_help  )
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  { print "\n run_sims project_name  project_vendor";
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    print "\n";
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    exit 1;
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  }
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#/**********************************************************************/
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#/*  Process each project by finding any ip-xact file in any component */
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#/*                                                                    */
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#/*  Each ip-xact file is parsed and it's filename and the names of any*/
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#/*  modules that it uses are saved.                                   */
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#/*                                                                    */
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#/*                                                                    */
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#/**********************************************************************/
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my $home              = cwd();
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my $vendor ;
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my $project  ;
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$_               = $ARGV[0];
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my $work_site    = $ARGV[1];
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if(/(\S+)__(\S+)/)
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     {
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     $vendor           = $1;
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     $project         = $2;
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     }
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my $parser = XML::LibXML->new();
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123 124 jt_eaton
my @components   = yp::lib::find_components("socgen:componentConfiguration",$vendor,$project);
124 119 jt_eaton
 
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foreach my $component (@components)
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   {
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   my $sogen_file     = $parser->parse_file(yp::lib::find_socgen("socgen:componentConfiguration",$vendor,$project,$component));
128 128 jt_eaton
   my $sim_library_path   = $sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:library_path/text()")->to_literal;
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130 128 jt_eaton
 
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132 119 jt_eaton
   #/*********************************************************************************************/
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   #/   files for simulation                                                                     */
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   #/                                                                                            */
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   #/*********************************************************************************************/
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137 124 jt_eaton
   foreach  my   $i_name ($sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
138 119 jt_eaton
      {
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      my($sim_name)     = $i_name ->findnodes('./text()')->to_literal ;
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      my($sim_configuration)  = $i_name ->findnodes('../socgen:configuration/text()')->to_literal ;
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      my($sim_variant)  = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
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      print "  SIMs     $sim_name        $sim_configuration   $sim_variant   ";
144 128 jt_eaton
      chdir  ".${work_site}/${vendor}__${project}${sim_library_path}/icarus/${sim_name}";
145 119 jt_eaton
 
146 128 jt_eaton
      $cmd ="iverilog   -f ../../testbenches/filelists/${sim_variant}.sim -D VCD  2>   ./${sim_name}_elab.log  | tee >> ./${$sim_name}_elab.log \n";
147 119 jt_eaton
      if (system($cmd)) {}
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      $cmd ="./a.out 2>    ./${sim_name}_sim.log     | tee >> ./${sim_name}_sim.log  \n";
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      if (system($cmd)) {}
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      $cmd ="grep PASSED  ./${sim_name}_sim.log \n";
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      if (system($cmd)) {}
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      $cmd ="rm a.out \n";
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      if (system($cmd)) {}
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      chdir $home;
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      }
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   foreach  my   $i_name ($sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:verilator/socgen:test/socgen:name"))
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      {
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      my($sim_name)     = $i_name ->findnodes('./text()')->to_literal ;
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      my($sim_configuration)  = $i_name ->findnodes('../socgen:configuration/text()')->to_literal ;
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      my($sim_variant)  = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
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      print "  VSIMs     $sim_name        $sim_configuration   $sim_variant   ";
166 128 jt_eaton
      chdir  ".${work_site}/${vendor}__${project}${sim_library_path}/verilator/${sim_name}";
167 126 jt_eaton
      $cmd ="make verilator\n";
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      if (system($cmd)) {}
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      chdir $home;
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      }
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   }
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