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1 130 jt_eaton 
//**************************************************************
2 
//  Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
3 
//  File Name    : unisim_comp.v
4 
//  Library      : unisim uni9000
5 
//  Release      : 10.1
6 
//  Module Count : 1105
7 
//  Generated by : gencomp
8 
//**************************************************************
9 
 
10 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11 
module AND2B1 (O, I0, I1);
12 
output O;
13 
input I0;
14 
input I1;
15 
endmodule
16 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17 
module AND2B2 (O, I0, I1);
18 
output O;
19 
input I0;
20 
input I1;
21 
endmodule
22 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
23 
module AND2 (O, I0, I1);
24 
output O;
25 
input I0;
26 
input I1;
27 
endmodule
28 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
29 
module AND3B1 (O, I0, I1, I2);
30 
output O;
31 
input I0;
32 
input I1;
33 
input I2;
34 
endmodule
35 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
36 
module AND3B2 (O, I0, I1, I2);
37 
output O;
38 
input I0;
39 
input I1;
40 
input I2;
41 
endmodule
42 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
43 
module AND3B3 (O, I0, I1, I2);
44 
output O;
45 
input I0;
46 
input I1;
47 
input I2;
48 
endmodule
49 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
50 
module AND3 (O, I0, I1, I2);
51 
output O;
52 
input I0;
53 
input I1;
54 
input I2;
55 
endmodule
56 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
57 
module AND4B1 (O, I0, I1, I2, I3);
58 
output O;
59 
input I0;
60 
input I1;
61 
input I2;
62 
input I3;
63 
endmodule
64 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
65 
module AND4B2 (O, I0, I1, I2, I3);
66 
output O;
67 
input I0;
68 
input I1;
69 
input I2;
70 
input I3;
71 
endmodule
72 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
73 
module AND4B3 (O, I0, I1, I2, I3);
74 
output O;
75 
input I0;
76 
input I1;
77 
input I2;
78 
input I3;
79 
endmodule
80 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
81 
module AND4B4 (O, I0, I1, I2, I3);
82 
output O;
83 
input I0;
84 
input I1;
85 
input I2;
86 
input I3;
87 
endmodule
88 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
89 
module AND4 (O, I0, I1, I2, I3);
90 
output O;
91 
input I0;
92 
input I1;
93 
input I2;
94 
input I3;
95 
endmodule
96 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
97 
module AND5B1 (O, I0, I1, I2, I3, I4);
98 
output O;
99 
input I0;
100 
input I1;
101 
input I2;
102 
input I3;
103 
input I4;
104 
endmodule
105 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
106 
module AND5B2 (O, I0, I1, I2, I3, I4);
107 
output O;
108 
input I0;
109 
input I1;
110 
input I2;
111 
input I3;
112 
input I4;
113 
endmodule
114 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
115 
module AND5B3 (O, I0, I1, I2, I3, I4);
116 
output O;
117 
input I0;
118 
input I1;
119 
input I2;
120 
input I3;
121 
input I4;
122 
endmodule
123 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
124 
module AND5B4 (O, I0, I1, I2, I3, I4);
125 
output O;
126 
input I0;
127 
input I1;
128 
input I2;
129 
input I3;
130 
input I4;
131 
endmodule
132 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
133 
module AND5B5 (O, I0, I1, I2, I3, I4);
134 
output O;
135 
input I0;
136 
input I1;
137 
input I2;
138 
input I3;
139 
input I4;
140 
endmodule
141 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
142 
module AND5 (O, I0, I1, I2, I3, I4);
143 
output O;
144 
input I0;
145 
input I1;
146 
input I2;
147 
input I3;
148 
input I4;
149 
endmodule
150 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
151 
module AND6 (O, I0, I1, I2, I3, I4, I5);
152 
output O;
153 
input I0;
154 
input I1;
155 
input I2;
156 
input I3;
157 
input I4;
158 
input I5;
159 
endmodule
160 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
161 
module AND7 (O, I0, I1, I2, I3, I4, I5, I6);
162 
output O;
163 
input I0;
164 
input I1;
165 
input I2;
166 
input I3;
167 
input I4;
168 
input I5;
169 
input I6;
170 
endmodule
171 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
172 
module AND8 (O, I0, I1, I2, I3, I4, I5, I6, I7);
173 
output O;
174 
input I0;
175 
input I1;
176 
input I2;
177 
input I3;
178 
input I4;
179 
input I5;
180 
input I6;
181 
input I7;
182 
endmodule
183 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
184 
module BSCAN_FPGACORE (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
185 
output CAPTURE;
186 
output DRCK1;
187 
output DRCK2;
188 
output RESET;
189 
output SEL1;
190 
output SEL2;
191 
output SHIFT;
192 
output TDI;
193 
output UPDATE;
194 
input TDO1;
195 
input TDO2;
196 
endmodule
197 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
198 
module BSCAN_SPARTAN2 (DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
199 
output DRCK1;
200 
output DRCK2;
201 
output RESET;
202 
output SEL1;
203 
output SEL2;
204 
output SHIFT;
205 
output TDI;
206 
output UPDATE;
207 
input TDO1;
208 
input TDO2;
209 
endmodule
210 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
211 
module BSCAN_SPARTAN3A (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2);
212 
output CAPTURE;
213 
output DRCK1;
214 
output DRCK2;
215 
output RESET;
216 
output SEL1;
217 
output SEL2;
218 
output SHIFT;
219 
output TCK;
220 
output TDI;
221 
output TMS;
222 
output UPDATE;
223 
input TDO1;
224 
input TDO2;
225 
endmodule
226 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
227 
module BSCAN_SPARTAN3 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
228 
output CAPTURE;
229 
output DRCK1;
230 
output DRCK2;
231 
output RESET;
232 
output SEL1;
233 
output SEL2;
234 
output SHIFT;
235 
output TDI;
236 
output UPDATE;
237 
input TDO1;
238 
input TDO2;
239 
endmodule
240 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
241 
module BSCAN_VIRTEX2 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
242 
output CAPTURE;
243 
output DRCK1;
244 
output DRCK2;
245 
output RESET;
246 
output SEL1;
247 
output SEL2;
248 
output SHIFT;
249 
output TDI;
250 
output UPDATE;
251 
input TDO1;
252 
input TDO2;
253 
endmodule
254 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
255 
module BSCAN_VIRTEX4 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
256 
parameter integer JTAG_CHAIN = 1;
257 
output CAPTURE;
258 
output DRCK;
259 
output RESET;
260 
output SEL;
261 
output SHIFT;
262 
output TDI;
263 
output UPDATE;
264 
input TDO;
265 
endmodule
266 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
267 
module BSCAN_VIRTEX5 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
268 
parameter integer JTAG_CHAIN = 1;
269 
output CAPTURE;
270 
output DRCK;
271 
output RESET;
272 
output SEL;
273 
output SHIFT;
274 
output TDI;
275 
output UPDATE;
276 
input TDO;
277 
endmodule
278 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
279 
module BSCAN_VIRTEX (DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
280 
output DRCK1;
281 
output DRCK2;
282 
output RESET;
283 
output SEL1;
284 
output SEL2;
285 
output SHIFT;
286 
output TDI;
287 
output UPDATE;
288 
input TDO1;
289 
input TDO2;
290 
endmodule
291 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
292 
module BUFCF (O, I);
293 
output O;
294 
input I;
295 
endmodule
296 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
297 
module BUFE (O, E, I);
298 
output O;
299 
input E;
300 
input I;
301 
endmodule
302 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
303 
module BUFFOE (O, I);
304 
output O;
305 
input I;
306 
endmodule
307 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
308 
module BUFGCE_1 (O, CE, I);
309 
output O;
310 
input CE;
311 
input I;
312 
endmodule
313 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
314 
module BUFGCE (O, CE, I);
315 
output O;
316 
input CE;
317 
input I;
318 
endmodule
319 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
320 
module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1);
321 
parameter integer INIT_OUT = 0;
322 
parameter PRESELECT_I0 = "FALSE";
323 
parameter PRESELECT_I1 = "FALSE";
324 
output O;
325 
input CE0;
326 
input CE1;
327 
input I0;
328 
input I1;
329 
input IGNORE0;
330 
input IGNORE1;
331 
input S0;
332 
input S1;
333 
endmodule
334 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
335 
module BUFGDLL (O, I);
336 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
337 
output O;
338 
input I;
339 
endmodule
340 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
341 
module BUFGMUX_1 (O, I0, I1, S);
342 
output O;
343 
input I0;
344 
input I1;
345 
input S;
346 
endmodule
347 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
348 
module BUFGMUX_CTRL (O, I0, I1, S);
349 
output O;
350 
input I0;
351 
input I1;
352 
input S;
353 
endmodule
354 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
355 
module BUFGMUX (O, I0, I1, S);
356 
output O;
357 
input I0;
358 
input I1;
359 
input S;
360 
endmodule
361 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
362 
module BUFGMUX_VIRTEX4 (O, I0, I1, S);
363 
output O;
364 
input I0;
365 
input I1;
366 
input S;
367 
endmodule
368 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
369 
module BUFGP (O, I);
370 
output O;
371 
input I;
372 
endmodule
373 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
374 
module BUFGSR (O, I);
375 
output O;
376 
input I;
377 
endmodule
378 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
379 
module BUFGTS (O, I);
380 
output O;
381 
input I;
382 
endmodule
383 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
384 
module BUFG (O, I);
385 
output O;
386 
input I;
387 
endmodule
388 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
389 
module BUFIO (O, I);
390 
output O;
391 
input I;
392 
endmodule
393 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
394 
module BUFR (O, CE, CLR, I);
395 
parameter BUFR_DIVIDE = "BYPASS";
396 
parameter SIM_DEVICE = "VIRTEX4";
397 
output O;
398 
input CE;
399 
input CLR;
400 
input I;
401 
endmodule
402 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
403 
module BUFT (O, I, T);
404 
output O;
405 
input I;
406 
input T;
407 
endmodule
408 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
409 
module BUF (O, I);
410 
output O;
411 
input I;
412 
endmodule
413 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
414 
module CAPTURE_FPGACORE (CAP, CLK);
415 
parameter ONESHOT = "FALSE";
416 
input CAP;
417 
input CLK;
418 
endmodule
419 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
420 
module CAPTURE_SPARTAN2 (CAP, CLK);
421 
parameter ONESHOT = "FALSE";
422 
input CAP;
423 
input CLK;
424 
endmodule
425 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
426 
module CAPTURE_SPARTAN3A (CAP, CLK);
427 
parameter ONESHOT = "TRUE";
428 
input CAP;
429 
input CLK;
430 
endmodule
431 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
432 
module CAPTURE_SPARTAN3 (CAP, CLK);
433 
parameter ONESHOT = "FALSE";
434 
input CAP;
435 
input CLK;
436 
endmodule
437 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
438 
module CAPTURE_VIRTEX2 (CAP, CLK);
439 
parameter ONESHOT = "FALSE";
440 
input CAP;
441 
input CLK;
442 
endmodule
443 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
444 
module CAPTURE_VIRTEX4 (CAP, CLK);
445 
parameter ONESHOT = "TRUE";
446 
input CAP;
447 
input CLK;
448 
endmodule
449 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
450 
module CAPTURE_VIRTEX5 (CAP, CLK);
451 
parameter ONESHOT = "TRUE";
452 
input CAP;
453 
input CLK;
454 
endmodule
455 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
456 
module CAPTURE_VIRTEX (CAP, CLK);
457 
parameter ONESHOT = "FALSE";
458 
input CAP;
459 
input CLK;
460 
endmodule
461 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
462 
module CARRY4 (CO, O, CI, CYINIT, DI, S);
463 
output [3:0] CO;
464 
output [3:0] O;
465 
input CI;
466 
input CYINIT;
467 
input [3:0] DI;
468 
input [3:0] S;
469 
endmodule
470 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
471 
module CFGLUT5 (CDO, O5, O6, CDI, CE, CLK, I0, I1, I2, I3, I4);
472 
parameter INIT = 32'h00000000;
473 
output CDO;
474 
output O5;
475 
output O6;
476 
input CDI;
477 
input CE;
478 
input CLK;
479 
input I0;
480 
input I1;
481 
input I2;
482 
input I3;
483 
input I4;
484 
endmodule
485 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
486 
module CLK_DIV10RSD (CLKDV, CDRST, CLKIN);
487 
parameter integer DIVIDE_BY = 10;
488 
parameter integer DIVIDER_DELAY = 1;
489 
output CLKDV;
490 
input CDRST;
491 
input CLKIN;
492 
endmodule
493 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
494 
module CLK_DIV10R (CLKDV, CDRST, CLKIN);
495 
parameter integer DIVIDE_BY = 10;
496 
output CLKDV;
497 
input CDRST;
498 
input CLKIN;
499 
endmodule
500 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
501 
module CLK_DIV10SD (CLKDV, CLKIN);
502 
parameter integer DIVIDE_BY = 10;
503 
parameter integer DIVIDER_DELAY = 1;
504 
output CLKDV;
505 
input CLKIN;
506 
endmodule
507 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
508 
module CLK_DIV10 (CLKDV, CLKIN);
509 
parameter integer DIVIDE_BY = 10;
510 
output CLKDV;
511 
input CLKIN;
512 
endmodule
513 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
514 
module CLK_DIV12RSD (CLKDV, CDRST, CLKIN);
515 
parameter integer DIVIDE_BY = 12;
516 
parameter integer DIVIDER_DELAY = 1;
517 
output CLKDV;
518 
input CDRST;
519 
input CLKIN;
520 
endmodule
521 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
522 
module CLK_DIV12R (CLKDV, CDRST, CLKIN);
523 
parameter integer DIVIDE_BY = 12;
524 
output CLKDV;
525 
input CDRST;
526 
input CLKIN;
527 
endmodule
528 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
529 
module CLK_DIV12SD (CLKDV, CLKIN);
530 
parameter integer DIVIDE_BY = 12;
531 
parameter integer DIVIDER_DELAY = 1;
532 
output CLKDV;
533 
input CLKIN;
534 
endmodule
535 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
536 
module CLK_DIV12 (CLKDV, CLKIN);
537 
parameter integer DIVIDE_BY = 12;
538 
output CLKDV;
539 
input CLKIN;
540 
endmodule
541 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
542 
module CLK_DIV14RSD (CLKDV, CDRST, CLKIN);
543 
parameter integer DIVIDE_BY = 14;
544 
parameter integer DIVIDER_DELAY = 1;
545 
output CLKDV;
546 
input CDRST;
547 
input CLKIN;
548 
endmodule
549 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
550 
module CLK_DIV14R (CLKDV, CDRST, CLKIN);
551 
parameter integer DIVIDE_BY = 14;
552 
output CLKDV;
553 
input CDRST;
554 
input CLKIN;
555 
endmodule
556 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
557 
module CLK_DIV14SD (CLKDV, CLKIN);
558 
parameter integer DIVIDE_BY = 14;
559 
parameter integer DIVIDER_DELAY = 1;
560 
output CLKDV;
561 
input CLKIN;
562 
endmodule
563 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
564 
module CLK_DIV14 (CLKDV, CLKIN);
565 
parameter integer DIVIDE_BY = 14;
566 
output CLKDV;
567 
input CLKIN;
568 
endmodule
569 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
570 
module CLK_DIV16RSD (CLKDV, CDRST, CLKIN);
571 
parameter integer DIVIDE_BY = 16;
572 
parameter integer DIVIDER_DELAY = 1;
573 
output CLKDV;
574 
input CDRST;
575 
input CLKIN;
576 
endmodule
577 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
578 
module CLK_DIV16R (CLKDV, CDRST, CLKIN);
579 
parameter integer DIVIDE_BY = 16;
580 
output CLKDV;
581 
input CDRST;
582 
input CLKIN;
583 
endmodule
584 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
585 
module CLK_DIV16SD (CLKDV, CLKIN);
586 
parameter integer DIVIDE_BY = 16;
587 
parameter integer DIVIDER_DELAY = 1;
588 
output CLKDV;
589 
input CLKIN;
590 
endmodule
591 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
592 
module CLK_DIV16 (CLKDV, CLKIN);
593 
parameter integer DIVIDE_BY = 16;
594 
output CLKDV;
595 
input CLKIN;
596 
endmodule
597 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
598 
module CLK_DIV2RSD (CLKDV, CDRST, CLKIN);
599 
parameter integer DIVIDE_BY = 2;
600 
parameter integer DIVIDER_DELAY = 1;
601 
output CLKDV;
602 
input CDRST;
603 
input CLKIN;
604 
endmodule
605 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
606 
module CLK_DIV2R (CLKDV, CDRST, CLKIN);
607 
parameter integer DIVIDE_BY = 2;
608 
output CLKDV;
609 
input CDRST;
610 
input CLKIN;
611 
endmodule
612 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
613 
module CLK_DIV2SD (CLKDV, CLKIN);
614 
parameter integer DIVIDE_BY = 2;
615 
parameter integer DIVIDER_DELAY = 1;
616 
output CLKDV;
617 
input CLKIN;
618 
endmodule
619 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
620 
module CLK_DIV2 (CLKDV, CLKIN);
621 
parameter integer DIVIDE_BY = 2;
622 
output CLKDV;
623 
input CLKIN;
624 
endmodule
625 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
626 
module CLK_DIV4RSD (CLKDV, CDRST, CLKIN);
627 
parameter integer DIVIDE_BY = 4;
628 
parameter integer DIVIDER_DELAY = 1;
629 
output CLKDV;
630 
input CDRST;
631 
input CLKIN;
632 
endmodule
633 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
634 
module CLK_DIV4R (CLKDV, CDRST, CLKIN);
635 
parameter integer DIVIDE_BY = 4;
636 
output CLKDV;
637 
input CDRST;
638 
input CLKIN;
639 
endmodule
640 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
641 
module CLK_DIV4SD (CLKDV, CLKIN);
642 
parameter integer DIVIDE_BY = 4;
643 
parameter integer DIVIDER_DELAY = 1;
644 
output CLKDV;
645 
input CLKIN;
646 
endmodule
647 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
648 
module CLK_DIV4 (CLKDV, CLKIN);
649 
parameter integer DIVIDE_BY = 4;
650 
output CLKDV;
651 
input CLKIN;
652 
endmodule
653 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
654 
module CLK_DIV6RSD (CLKDV, CDRST, CLKIN);
655 
parameter integer DIVIDE_BY = 6;
656 
parameter integer DIVIDER_DELAY = 1;
657 
output CLKDV;
658 
input CDRST;
659 
input CLKIN;
660 
endmodule
661 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
662 
module CLK_DIV6R (CLKDV, CDRST, CLKIN);
663 
parameter integer DIVIDE_BY = 6;
664 
output CLKDV;
665 
input CDRST;
666 
input CLKIN;
667 
endmodule
668 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
669 
module CLK_DIV6SD (CLKDV, CLKIN);
670 
parameter integer DIVIDE_BY = 6;
671 
parameter integer DIVIDER_DELAY = 1;
672 
output CLKDV;
673 
input CLKIN;
674 
endmodule
675 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
676 
module CLK_DIV6 (CLKIN, CLKDV);
677 
parameter integer DIVIDE_BY = 6;
678 
output CLKDV;
679 
input CLKIN;
680 
endmodule
681 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
682 
module CLK_DIV8RSD (CLKDV, CDRST, CLKIN);
683 
parameter integer DIVIDE_BY = 8;
684 
parameter integer DIVIDER_DELAY = 1;
685 
output CLKDV;
686 
input CDRST;
687 
input CLKIN;
688 
endmodule
689 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
690 
module CLK_DIV8R (CLKDV, CDRST, CLKIN);
691 
parameter integer DIVIDE_BY = 8;
692 
output CLKDV;
693 
input CDRST;
694 
input CLKIN;
695 
endmodule
696 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
697 
module CLK_DIV8SD (CLKDV, CLKIN);
698 
parameter integer DIVIDE_BY = 8;
699 
parameter integer DIVIDER_DELAY = 1;
700 
output CLKDV;
701 
input CLKIN;
702 
endmodule
703 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
704 
module CLK_DIV8 (CLKDV, CLKIN);
705 
parameter integer DIVIDE_BY = 8;
706 
output CLKDV;
707 
input CLKIN;
708 
endmodule
709 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
710 
module CLKDLLE (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED, CLKFB, CLKIN, RST);
711 
parameter real CLKDV_DIVIDE = 2.0;
712 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
713 
parameter FACTORY_JF = 16'hC080;
714 
parameter STARTUP_WAIT = "FALSE";
715 
output CLK0;
716 
output CLK180;
717 
output CLK270;
718 
output CLK2X;
719 
output CLK2X180;
720 
output CLK90;
721 
output CLKDV;
722 
output LOCKED;
723 
input CLKFB;
724 
input CLKIN;
725 
input RST;
726 
endmodule
727 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
728 
module CLKDLLHF (CLK0, CLK180, CLKDV, LOCKED, CLKFB, CLKIN, RST);
729 
parameter real CLKDV_DIVIDE = 2.0;
730 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
731 
parameter FACTORY_JF = 16'hFFF0;
732 
parameter STARTUP_WAIT = "FALSE";
733 
output CLK0;
734 
output CLK180;
735 
output CLKDV;
736 
output LOCKED;
737 
input CLKFB;
738 
input CLKIN;
739 
input RST;
740 
endmodule
741 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
742 
module CLKDLL (CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED, CLKFB, CLKIN, RST);
743 
parameter real CLKDV_DIVIDE = 2.0;
744 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
745 
parameter FACTORY_JF = 16'hC080;
746 
parameter STARTUP_WAIT = "FALSE";
747 
output CLK0;
748 
output CLK180;
749 
output CLK270;
750 
output CLK2X;
751 
output CLK90;
752 
output CLKDV;
753 
output LOCKED;
754 
input CLKFB;
755 
input CLKIN;
756 
input RST;
757 
endmodule
758 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
759 
module CONFIG ();
760 
endmodule
761 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
762 
module CRC32 (CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
763 
parameter CRC_INIT = 32'hFFFFFFFF;
764 
output [31:0] CRCOUT;
765 
input CRCCLK;
766 
input CRCDATAVALID;
767 
input [2:0] CRCDATAWIDTH;
768 
input [31:0] CRCIN;
769 
input CRCRESET;
770 
endmodule
771 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
772 
module CRC64 (CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
773 
parameter CRC_INIT = 32'hFFFFFFFF;
774 
output [31:0] CRCOUT;
775 
input CRCCLK;
776 
input CRCDATAVALID;
777 
input [2:0] CRCDATAWIDTH;
778 
input [63:0] CRCIN;
779 
input CRCRESET;
780 
endmodule
781 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
782 
module DCC_FPGACORE (BCLK, DONEOUT, DOUT0, DOUT1, DOUT2, DOUT3, DOUT4, DOUT5, DOUT6, DOUT7, GSR, GTS, GWE, INITBOUT, TDO, CCLK, CSB, DIN0, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7, DONEIN, LBISTISOLATEB, M0, M1, M2, PROGB, TCK, TDI, TMS, WRITEB);
783 
parameter DEVICE_SIZE = 9'd10;
784 
output BCLK;
785 
output DONEOUT;
786 
output DOUT0;
787 
output DOUT1;
788 
output DOUT2;
789 
output DOUT3;
790 
output DOUT4;
791 
output DOUT5;
792 
output DOUT6;
793 
output DOUT7;
794 
output GSR;
795 
output GTS;
796 
output GWE;
797 
output INITBOUT;
798 
output TDO;
799 
input CCLK;
800 
input CSB;
801 
input DIN0;
802 
input DIN1;
803 
input DIN2;
804 
input DIN3;
805 
input DIN4;
806 
input DIN5;
807 
input DIN6;
808 
input DIN7;
809 
input DONEIN;
810 
input LBISTISOLATEB;
811 
input M0;
812 
input M1;
813 
input M2;
814 
input PROGB;
815 
input TCK;
816 
input TDI;
817 
input TMS;
818 
input WRITEB;
819 
endmodule
820 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
821 
module DCIRESET (LOCKED, RST);
822 
output LOCKED;
823 
input RST;
824 
endmodule
825 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
826 
module DCM_ADV (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, DO, DRDY, LOCKED, PSDONE, CLKFB, CLKIN, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, RST);
827 
parameter real CLKDV_DIVIDE = 2.0;
828 
parameter integer CLKFX_DIVIDE = 1;
829 
parameter integer CLKFX_MULTIPLY = 4;
830 
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
831 
parameter real CLKIN_PERIOD = 10.0;
832 
parameter CLKOUT_PHASE_SHIFT = "NONE";
833 
parameter CLK_FEEDBACK = "1X";
834 
parameter DCM_AUTOCALIBRATION = "TRUE";
835 
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
836 
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
837 
parameter DFS_FREQUENCY_MODE = "LOW";
838 
parameter DLL_FREQUENCY_MODE = "LOW";
839 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
840 
parameter FACTORY_JF = 16'hF0F0;
841 
parameter integer PHASE_SHIFT = 0;
842 
parameter SIM_DEVICE = "VIRTEX4";
843 
parameter STARTUP_WAIT = "FALSE";
844 
output CLK0;
845 
output CLK180;
846 
output CLK270;
847 
output CLK2X;
848 
output CLK2X180;
849 
output CLK90;
850 
output CLKDV;
851 
output CLKFX;
852 
output CLKFX180;
853 
output [15:0] DO;
854 
output DRDY;
855 
output LOCKED;
856 
output PSDONE;
857 
input CLKFB;
858 
input CLKIN;
859 
input [6:0] DADDR;
860 
input DCLK;
861 
input DEN;
862 
input [15:0] DI;
863 
input DWE;
864 
input PSCLK;
865 
input PSEN;
866 
input PSINCDEC;
867 
input RST;
868 
endmodule
869 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
870 
module DCM_BASE (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, CLKFB, CLKIN, RST);
871 
parameter real CLKDV_DIVIDE = 2.0;
872 
parameter integer CLKFX_DIVIDE = 1;
873 
parameter integer CLKFX_MULTIPLY = 4;
874 
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
875 
parameter real CLKIN_PERIOD = 10.0;
876 
parameter CLKOUT_PHASE_SHIFT = "NONE";
877 
parameter CLK_FEEDBACK = "1X";
878 
parameter DCM_AUTOCALIBRATION = "TRUE";
879 
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
880 
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
881 
parameter DFS_FREQUENCY_MODE = "LOW";
882 
parameter DLL_FREQUENCY_MODE = "LOW";
883 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
884 
parameter FACTORY_JF = 16'hF0F0;
885 
parameter integer PHASE_SHIFT = 0;
886 
parameter STARTUP_WAIT = "FALSE";
887 
output CLK0;
888 
output CLK180;
889 
output CLK270;
890 
output CLK2X;
891 
output CLK2X180;
892 
output CLK90;
893 
output CLKDV;
894 
output CLKFX;
895 
output CLKFX180;
896 
output LOCKED;
897 
input CLKFB;
898 
input CLKIN;
899 
input RST;
900 
endmodule
901 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
902 
module DCM_PS (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, DO, LOCKED, PSDONE, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST);
903 
parameter real CLKDV_DIVIDE = 2.0;
904 
parameter integer CLKFX_DIVIDE = 1;
905 
parameter integer CLKFX_MULTIPLY = 4;
906 
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
907 
parameter real CLKIN_PERIOD = 10.0;
908 
parameter CLKOUT_PHASE_SHIFT = "NONE";
909 
parameter CLK_FEEDBACK = "1X";
910 
parameter DCM_AUTOCALIBRATION = "TRUE";
911 
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
912 
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
913 
parameter DFS_FREQUENCY_MODE = "LOW";
914 
parameter DLL_FREQUENCY_MODE = "LOW";
915 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
916 
parameter FACTORY_JF = 16'hF0F0;
917 
parameter integer PHASE_SHIFT = 0;
918 
parameter STARTUP_WAIT = "FALSE";
919 
output CLK0;
920 
output CLK180;
921 
output CLK270;
922 
output CLK2X;
923 
output CLK2X180;
924 
output CLK90;
925 
output CLKDV;
926 
output CLKFX;
927 
output CLKFX180;
928 
output [15:0] DO;
929 
output LOCKED;
930 
output PSDONE;
931 
input CLKFB;
932 
input CLKIN;
933 
input PSCLK;
934 
input PSEN;
935 
input PSINCDEC;
936 
input RST;
937 
endmodule
938 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
939 
module DCM_SP (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
940 
parameter real CLKDV_DIVIDE = 2.0;
941 
parameter integer CLKFX_DIVIDE = 1;
942 
parameter integer CLKFX_MULTIPLY = 4;
943 
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
944 
parameter real CLKIN_PERIOD = 10.0;
945 
parameter CLKOUT_PHASE_SHIFT = "NONE";
946 
parameter CLK_FEEDBACK = "1X";
947 
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
948 
parameter DFS_FREQUENCY_MODE = "LOW";
949 
parameter DLL_FREQUENCY_MODE = "LOW";
950 
parameter DSS_MODE = "NONE";
951 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
952 
parameter FACTORY_JF = 16'hC080;
953 
parameter integer PHASE_SHIFT = 0;
954 
parameter STARTUP_WAIT = "FALSE";
955 
output CLK0;
956 
output CLK180;
957 
output CLK270;
958 
output CLK2X;
959 
output CLK2X180;
960 
output CLK90;
961 
output CLKDV;
962 
output CLKFX;
963 
output CLKFX180;
964 
output LOCKED;
965 
output PSDONE;
966 
output [7:0] STATUS;
967 
input CLKFB;
968 
input CLKIN;
969 
input DSSEN;
970 
input PSCLK;
971 
input PSEN;
972 
input PSINCDEC;
973 
input RST;
974 
endmodule
975 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
976 
module DCM (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
977 
parameter real CLKDV_DIVIDE = 2.0;
978 
parameter integer CLKFX_DIVIDE = 1;
979 
parameter integer CLKFX_MULTIPLY = 4;
980 
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
981 
parameter real CLKIN_PERIOD = 10.0;
982 
parameter CLKOUT_PHASE_SHIFT = "NONE";
983 
parameter CLK_FEEDBACK = "1X";
984 
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
985 
parameter DFS_FREQUENCY_MODE = "LOW";
986 
parameter DLL_FREQUENCY_MODE = "LOW";
987 
parameter DSS_MODE = "NONE";
988 
parameter DUTY_CYCLE_CORRECTION = "TRUE";
989 
parameter FACTORY_JF = 16'hC080;
990 
parameter integer PHASE_SHIFT = 0;
991 
parameter SIM_MODE = "SAFE";
992 
parameter STARTUP_WAIT = "FALSE";
993 
output CLK0;
994 
output CLK180;
995 
output CLK270;
996 
output CLK2X;
997 
output CLK2X180;
998 
output CLK90;
999 
output CLKDV;
1000 
output CLKFX;
1001 
output CLKFX180;
1002 
output LOCKED;
1003 
output PSDONE;
1004 
output [7:0] STATUS;
1005 
input CLKFB;
1006 
input CLKIN;
1007 
input DSSEN;
1008 
input PSCLK;
1009 
input PSEN;
1010 
input PSINCDEC;
1011 
input RST;
1012 
endmodule
1013 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1014 
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
1015 
parameter SIM_DNA_VALUE = 57'h0;
1016 
output DOUT;
1017 
input CLK;
1018 
input DIN;
1019 
input READ;
1020 
input SHIFT;
1021 
endmodule
1022 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1023 
module DSP48A (BCOUT, CARRYOUT, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP);
1024 
parameter integer A0REG = 0;
1025 
parameter integer A1REG = 1;
1026 
parameter integer B0REG = 0;
1027 
parameter integer B1REG = 1;
1028 
parameter integer CARRYINREG = 1;
1029 
parameter CARRYINSEL = "CARRYIN";
1030 
parameter integer CREG = 1;
1031 
parameter integer DREG = 1;
1032 
parameter integer MREG = 1;
1033 
parameter integer OPMODEREG = 1;
1034 
parameter integer PREG = 1;
1035 
parameter RSTTYPE = "SYNC";
1036 
output [17:0] BCOUT;
1037 
output CARRYOUT;
1038 
output [47:0] P;
1039 
output [47:0] PCOUT;
1040 
input [17:0] A;
1041 
input [17:0] B;
1042 
input [47:0] C;
1043 
input CARRYIN;
1044 
input CEA;
1045 
input CEB;
1046 
input CEC;
1047 
input CECARRYIN;
1048 
input CED;
1049 
input CEM;
1050 
input CEOPMODE;
1051 
input CEP;
1052 
input CLK;
1053 
input [17:0] D;
1054 
input [7:0] OPMODE;
1055 
input [47:0] PCIN;
1056 
input RSTA;
1057 
input RSTB;
1058 
input RSTC;
1059 
input RSTCARRYIN;
1060 
input RSTD;
1061 
input RSTM;
1062 
input RSTOPMODE;
1063 
input RSTP;
1064 
endmodule
1065 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1066 
module DSP48E (ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM, RSTP);
1067 
parameter SIM_MODE = "SAFE";
1068 
parameter integer ACASCREG = 1;
1069 
parameter integer ALUMODEREG = 1;
1070 
parameter integer AREG = 1;
1071 
parameter AUTORESET_PATTERN_DETECT = "FALSE";
1072 
parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
1073 
parameter A_INPUT = "DIRECT";
1074 
parameter integer BCASCREG = 1;
1075 
parameter integer BREG = 1;
1076 
parameter B_INPUT = "DIRECT";
1077 
parameter integer CARRYINREG = 1;
1078 
parameter integer CARRYINSELREG = 1;
1079 
parameter integer CREG = 1;
1080 
parameter MASK = 48'h3FFFFFFFFFFF;
1081 
parameter integer MREG = 1;
1082 
parameter integer MULTCARRYINREG = 1;
1083 
parameter integer OPMODEREG = 1;
1084 
parameter PATTERN = 48'h000000000000;
1085 
parameter integer PREG = 1;
1086 
parameter SEL_MASK = "MASK";
1087 
parameter SEL_PATTERN = "PATTERN";
1088 
parameter SEL_ROUNDING_MASK = "SEL_MASK";
1089 
parameter USE_MULT = "MULT_S";
1090 
parameter USE_PATTERN_DETECT = "NO_PATDET";
1091 
parameter USE_SIMD = "ONE48";
1092 
output [29:0] ACOUT;
1093 
output [17:0] BCOUT;
1094 
output CARRYCASCOUT;
1095 
output [3:0] CARRYOUT;
1096 
output MULTSIGNOUT;
1097 
output OVERFLOW;
1098 
output [47:0] P;
1099 
output PATTERNBDETECT;
1100 
output PATTERNDETECT;
1101 
output [47:0] PCOUT;
1102 
output UNDERFLOW;
1103 
input [29:0] A;
1104 
input [29:0] ACIN;
1105 
input [3:0] ALUMODE;
1106 
input [17:0] B;
1107 
input [17:0] BCIN;
1108 
input [47:0] C;
1109 
input CARRYCASCIN;
1110 
input CARRYIN;
1111 
input [2:0] CARRYINSEL;
1112 
input CEA1;
1113 
input CEA2;
1114 
input CEALUMODE;
1115 
input CEB1;
1116 
input CEB2;
1117 
input CEC;
1118 
input CECARRYIN;
1119 
input CECTRL;
1120 
input CEM;
1121 
input CEMULTCARRYIN;
1122 
input CEP;
1123 
input CLK;
1124 
input MULTSIGNIN;
1125 
input [6:0] OPMODE;
1126 
input [47:0] PCIN;
1127 
input RSTA;
1128 
input RSTALLCARRYIN;
1129 
input RSTALUMODE;
1130 
input RSTB;
1131 
input RSTC;
1132 
input RSTCTRL;
1133 
input RSTM;
1134 
input RSTP;
1135 
endmodule
1136 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1137 
module DSP48 (BCOUT, P, PCOUT, A, B, BCIN, C, CARRYIN, CARRYINSEL, CEA, CEB, CEC, CECARRYIN, CECINSUB, CECTRL, CEM, CEP, CLK, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTCTRL, RSTM, RSTP, SUBTRACT);
1138 
parameter integer AREG = 1;
1139 
parameter integer BREG = 1;
1140 
parameter B_INPUT = "DIRECT";
1141 
parameter integer CARRYINREG = 1;
1142 
parameter integer CARRYINSELREG = 1;
1143 
parameter integer CREG = 1;
1144 
parameter LEGACY_MODE = "MULT18X18S";
1145 
parameter integer MREG = 1;
1146 
parameter integer OPMODEREG = 1;
1147 
parameter integer PREG = 1;
1148 
parameter integer SUBTRACTREG = 1;
1149 
output [17:0] BCOUT;
1150 
output [47:0] P;
1151 
output [47:0] PCOUT;
1152 
input [17:0] A;
1153 
input [17:0] B;
1154 
input [17:0] BCIN;
1155 
input [47:0] C;
1156 
input CARRYIN;
1157 
input [1:0] CARRYINSEL;
1158 
input CEA;
1159 
input CEB;
1160 
input CEC;
1161 
input CECARRYIN;
1162 
input CECINSUB;
1163 
input CECTRL;
1164 
input CEM;
1165 
input CEP;
1166 
input CLK;
1167 
input [6:0] OPMODE;
1168 
input [47:0] PCIN;
1169 
input RSTA;
1170 
input RSTB;
1171 
input RSTC;
1172 
input RSTCARRYIN;
1173 
input RSTCTRL;
1174 
input RSTM;
1175 
input RSTP;
1176 
input SUBTRACT;
1177 
endmodule
1178 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1179 
module EMAC (DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXD, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXDVREG6, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATS, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXGMIIMIICLKOUT, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXD, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXD, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXDVREG6, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATS, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXGMIIMIICLKOUT, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXD, EMAC1PHYTXEN, EMAC1PHYTXER, EMACDCRACK, EMACDCRDBUS, HOSTMIIMRDY, HOSTRDDATA, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXD, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE, CLIENTEMAC0TXGMIIMIICLKIN, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXD, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXGMIIMIICLKIN, CLIENTEMAC1TXIFGDELAY, CLIENTEMAC1TXUNDERRUN, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTADDR, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTOPCODE, HOSTREQ, HOSTWRDATA, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0PHYAD, PHYEMAC0RXBUFERR, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCLKCORCNT, PHYEMAC0RXCOMMADET, PHYEMAC0RXD, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXLOSSOFSYNC, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1PHYAD, PHYEMAC1RXBUFERR, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCLKCORCNT, PHYEMAC1RXCOMMADET, PHYEMAC1RXD, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXLOSSOFSYNC, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, RESET, TIEEMAC0CONFIGVEC, TIEEMAC0UNICASTADDR, TIEEMAC1CONFIGVEC, TIEEMAC1UNICASTADDR);
1180 
output DCRHOSTDONEIR;
1181 
output EMAC0CLIENTANINTERRUPT;
1182 
output EMAC0CLIENTRXBADFRAME;
1183 
output EMAC0CLIENTRXCLIENTCLKOUT;
1184 
output [15:0] EMAC0CLIENTRXD;
1185 
output EMAC0CLIENTRXDVLD;
1186 
output EMAC0CLIENTRXDVLDMSW;
1187 
output EMAC0CLIENTRXDVREG6;
1188 
output EMAC0CLIENTRXFRAMEDROP;
1189 
output EMAC0CLIENTRXGOODFRAME;
1190 
output [6:0] EMAC0CLIENTRXSTATS;
1191 
output EMAC0CLIENTRXSTATSBYTEVLD;
1192 
output EMAC0CLIENTRXSTATSVLD;
1193 
output EMAC0CLIENTTXACK;
1194 
output EMAC0CLIENTTXCLIENTCLKOUT;
1195 
output EMAC0CLIENTTXCOLLISION;
1196 
output EMAC0CLIENTTXGMIIMIICLKOUT;
1197 
output EMAC0CLIENTTXRETRANSMIT;
1198 
output EMAC0CLIENTTXSTATS;
1199 
output EMAC0CLIENTTXSTATSBYTEVLD;
1200 
output EMAC0CLIENTTXSTATSVLD;
1201 
output EMAC0PHYENCOMMAALIGN;
1202 
output EMAC0PHYLOOPBACKMSB;
1203 
output EMAC0PHYMCLKOUT;
1204 
output EMAC0PHYMDOUT;
1205 
output EMAC0PHYMDTRI;
1206 
output EMAC0PHYMGTRXRESET;
1207 
output EMAC0PHYMGTTXRESET;
1208 
output EMAC0PHYPOWERDOWN;
1209 
output EMAC0PHYSYNCACQSTATUS;
1210 
output EMAC0PHYTXCHARDISPMODE;
1211 
output EMAC0PHYTXCHARDISPVAL;
1212 
output EMAC0PHYTXCHARISK;
1213 
output EMAC0PHYTXCLK;
1214 
output [7:0] EMAC0PHYTXD;
1215 
output EMAC0PHYTXEN;
1216 
output EMAC0PHYTXER;
1217 
output EMAC1CLIENTANINTERRUPT;
1218 
output EMAC1CLIENTRXBADFRAME;
1219 
output EMAC1CLIENTRXCLIENTCLKOUT;
1220 
output [15:0] EMAC1CLIENTRXD;
1221 
output EMAC1CLIENTRXDVLD;
1222 
output EMAC1CLIENTRXDVLDMSW;
1223 
output EMAC1CLIENTRXDVREG6;
1224 
output EMAC1CLIENTRXFRAMEDROP;
1225 
output EMAC1CLIENTRXGOODFRAME;
1226 
output [6:0] EMAC1CLIENTRXSTATS;
1227 
output EMAC1CLIENTRXSTATSBYTEVLD;
1228 
output EMAC1CLIENTRXSTATSVLD;
1229 
output EMAC1CLIENTTXACK;
1230 
output EMAC1CLIENTTXCLIENTCLKOUT;
1231 
output EMAC1CLIENTTXCOLLISION;
1232 
output EMAC1CLIENTTXGMIIMIICLKOUT;
1233 
output EMAC1CLIENTTXRETRANSMIT;
1234 
output EMAC1CLIENTTXSTATS;
1235 
output EMAC1CLIENTTXSTATSBYTEVLD;
1236 
output EMAC1CLIENTTXSTATSVLD;
1237 
output EMAC1PHYENCOMMAALIGN;
1238 
output EMAC1PHYLOOPBACKMSB;
1239 
output EMAC1PHYMCLKOUT;
1240 
output EMAC1PHYMDOUT;
1241 
output EMAC1PHYMDTRI;
1242 
output EMAC1PHYMGTRXRESET;
1243 
output EMAC1PHYMGTTXRESET;
1244 
output EMAC1PHYPOWERDOWN;
1245 
output EMAC1PHYSYNCACQSTATUS;
1246 
output EMAC1PHYTXCHARDISPMODE;
1247 
output EMAC1PHYTXCHARDISPVAL;
1248 
output EMAC1PHYTXCHARISK;
1249 
output EMAC1PHYTXCLK;
1250 
output [7:0] EMAC1PHYTXD;
1251 
output EMAC1PHYTXEN;
1252 
output EMAC1PHYTXER;
1253 
output EMACDCRACK;
1254 
output [0:31] EMACDCRDBUS;
1255 
output HOSTMIIMRDY;
1256 
output [31:0] HOSTRDDATA;
1257 
input CLIENTEMAC0DCMLOCKED;
1258 
input CLIENTEMAC0PAUSEREQ;
1259 
input [15:0] CLIENTEMAC0PAUSEVAL;
1260 
input CLIENTEMAC0RXCLIENTCLKIN;
1261 
input CLIENTEMAC0TXCLIENTCLKIN;
1262 
input [15:0] CLIENTEMAC0TXD;
1263 
input CLIENTEMAC0TXDVLD;
1264 
input CLIENTEMAC0TXDVLDMSW;
1265 
input CLIENTEMAC0TXFIRSTBYTE;
1266 
input CLIENTEMAC0TXGMIIMIICLKIN;
1267 
input [7:0] CLIENTEMAC0TXIFGDELAY;
1268 
input CLIENTEMAC0TXUNDERRUN;
1269 
input CLIENTEMAC1DCMLOCKED;
1270 
input CLIENTEMAC1PAUSEREQ;
1271 
input [15:0] CLIENTEMAC1PAUSEVAL;
1272 
input CLIENTEMAC1RXCLIENTCLKIN;
1273 
input CLIENTEMAC1TXCLIENTCLKIN;
1274 
input [15:0] CLIENTEMAC1TXD;
1275 
input CLIENTEMAC1TXDVLD;
1276 
input CLIENTEMAC1TXDVLDMSW;
1277 
input CLIENTEMAC1TXFIRSTBYTE;
1278 
input CLIENTEMAC1TXGMIIMIICLKIN;
1279 
input [7:0] CLIENTEMAC1TXIFGDELAY;
1280 
input CLIENTEMAC1TXUNDERRUN;
1281 
input [8:9] DCREMACABUS;
1282 
input DCREMACCLK;
1283 
input [0:31] DCREMACDBUS;
1284 
input DCREMACENABLE;
1285 
input DCREMACREAD;
1286 
input DCREMACWRITE;
1287 
input [9:0] HOSTADDR;
1288 
input HOSTCLK;
1289 
input HOSTEMAC1SEL;
1290 
input HOSTMIIMSEL;
1291 
input [1:0] HOSTOPCODE;
1292 
input HOSTREQ;
1293 
input [31:0] HOSTWRDATA;
1294 
input PHYEMAC0COL;
1295 
input PHYEMAC0CRS;
1296 
input PHYEMAC0GTXCLK;
1297 
input PHYEMAC0MCLKIN;
1298 
input PHYEMAC0MDIN;
1299 
input PHYEMAC0MIITXCLK;
1300 
input [4:0] PHYEMAC0PHYAD;
1301 
input PHYEMAC0RXBUFERR;
1302 
input [1:0] PHYEMAC0RXBUFSTATUS;
1303 
input PHYEMAC0RXCHARISCOMMA;
1304 
input PHYEMAC0RXCHARISK;
1305 
input PHYEMAC0RXCHECKINGCRC;
1306 
input PHYEMAC0RXCLK;
1307 
input [2:0] PHYEMAC0RXCLKCORCNT;
1308 
input PHYEMAC0RXCOMMADET;
1309 
input [7:0] PHYEMAC0RXD;
1310 
input PHYEMAC0RXDISPERR;
1311 
input PHYEMAC0RXDV;
1312 
input PHYEMAC0RXER;
1313 
input [1:0] PHYEMAC0RXLOSSOFSYNC;
1314 
input PHYEMAC0RXNOTINTABLE;
1315 
input PHYEMAC0RXRUNDISP;
1316 
input PHYEMAC0SIGNALDET;
1317 
input PHYEMAC0TXBUFERR;
1318 
input PHYEMAC1COL;
1319 
input PHYEMAC1CRS;
1320 
input PHYEMAC1GTXCLK;
1321 
input PHYEMAC1MCLKIN;
1322 
input PHYEMAC1MDIN;
1323 
input PHYEMAC1MIITXCLK;
1324 
input [4:0] PHYEMAC1PHYAD;
1325 
input PHYEMAC1RXBUFERR;
1326 
input [1:0] PHYEMAC1RXBUFSTATUS;
1327 
input PHYEMAC1RXCHARISCOMMA;
1328 
input PHYEMAC1RXCHARISK;
1329 
input PHYEMAC1RXCHECKINGCRC;
1330 
input PHYEMAC1RXCLK;
1331 
input [2:0] PHYEMAC1RXCLKCORCNT;
1332 
input PHYEMAC1RXCOMMADET;
1333 
input [7:0] PHYEMAC1RXD;
1334 
input PHYEMAC1RXDISPERR;
1335 
input PHYEMAC1RXDV;
1336 
input PHYEMAC1RXER;
1337 
input [1:0] PHYEMAC1RXLOSSOFSYNC;
1338 
input PHYEMAC1RXNOTINTABLE;
1339 
input PHYEMAC1RXRUNDISP;
1340 
input PHYEMAC1SIGNALDET;
1341 
input PHYEMAC1TXBUFERR;
1342 
input RESET;
1343 
input [79:0] TIEEMAC0CONFIGVEC;
1344 
input [47:0] TIEEMAC0UNICASTADDR;
1345 
input [79:0] TIEEMAC1CONFIGVEC;
1346 
input [47:0] TIEEMAC1UNICASTADDR;
1347 
endmodule
1348 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1349 
module FD_1 (Q, C, D);
1350 
parameter INIT = 1'b0;
1351 
output Q;
1352 
input C;
1353 
input D;
1354 
endmodule
1355 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1356 
module FDC_1 (Q, C, CLR, D);
1357 
parameter INIT = 1'b0;
1358 
output Q;
1359 
input C;
1360 
input CLR;
1361 
input D;
1362 
endmodule
1363 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1364 
module FDCE_1 (Q, C, CE, CLR, D);
1365 
parameter INIT = 1'b0;
1366 
output Q;
1367 
input C;
1368 
input CE;
1369 
input CLR;
1370 
input D;
1371 
endmodule
1372 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1373 
module FDCE (Q, C, CE, CLR, D);
1374 
parameter INIT = 1'b0;
1375 
output Q;
1376 
input C;
1377 
input CE;
1378 
input CLR;
1379 
input D;
1380 
endmodule
1381 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1382 
module FDCP_1 (Q, C, CLR, D, PRE);
1383 
parameter INIT = 1'b0;
1384 
output Q;
1385 
input C;
1386 
input CLR;
1387 
input D;
1388 
input PRE;
1389 
endmodule
1390 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1391 
module FDCPE_1 (Q, C, CE, CLR, D, PRE);
1392 
parameter INIT = 1'b0;
1393 
output Q;
1394 
input C;
1395 
input CE;
1396 
input CLR;
1397 
input D;
1398 
input PRE;
1399 
endmodule
1400 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1401 
module FDCPE (Q, C, CE, CLR, D, PRE);
1402 
parameter INIT = 1'b0;
1403 
output Q;
1404 
input C;
1405 
input CE;
1406 
input CLR;
1407 
input D;
1408 
input PRE;
1409 
endmodule
1410 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1411 
module FDCP (Q, C, CLR, D, PRE);
1412 
parameter INIT = 1'b0;
1413 
output Q;
1414 
input C;
1415 
input CLR;
1416 
input D;
1417 
input PRE;
1418 
endmodule
1419 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1420 
module FDCPX1 (Q, C, CLR, D, PRE);
1421 
output Q;
1422 
input C;
1423 
input CLR;
1424 
input D;
1425 
input PRE;
1426 
endmodule
1427 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1428 
module FDC (Q, C, CLR, D);
1429 
parameter INIT = 1'b0;
1430 
output Q;
1431 
input C;
1432 
input CLR;
1433 
input D;
1434 
endmodule
1435 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1436 
module FDDCE (Q, C, CE, CLR, D);
1437 
output Q;
1438 
input C;
1439 
input CE;
1440 
input CLR;
1441 
input D;
1442 
endmodule
1443 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1444 
module FDDCPE (Q, C, CE, CLR, D, PRE);
1445 
output Q;
1446 
input C;
1447 
input CE;
1448 
input CLR;
1449 
input D;
1450 
input PRE;
1451 
endmodule
1452 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1453 
module FDDCP (Q, C, CLR, D, PRE);
1454 
parameter INIT = 1'b0;
1455 
output Q;
1456 
input C;
1457 
input CLR;
1458 
input D;
1459 
input PRE;
1460 
endmodule
1461 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1462 
module FDDC (Q, C, CLR, D);
1463 
parameter INIT = 1'b0;
1464 
output Q;
1465 
input C;
1466 
input CLR;
1467 
input D;
1468 
endmodule
1469 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1470 
module FDDPE (Q, C, CE, D, PRE);
1471 
output Q;
1472 
input C;
1473 
input CE;
1474 
input D;
1475 
input PRE;
1476 
endmodule
1477 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1478 
module FDDP (Q, C, D, PRE);
1479 
parameter INIT = 1'b1;
1480 
output Q;
1481 
input C;
1482 
input D;
1483 
input PRE;
1484 
endmodule
1485 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1486 
module FDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);
1487 
parameter INIT = 1'b0;
1488 
output Q;
1489 
input C0;
1490 
input C1;
1491 
input CE;
1492 
input CLR;
1493 
input D0;
1494 
input D1;
1495 
input PRE;
1496 
endmodule
1497 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1498 
module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
1499 
parameter INIT = 1'b0;
1500 
output Q;
1501 
input C0;
1502 
input C1;
1503 
input CE;
1504 
input D0;
1505 
input D1;
1506 
input R;
1507 
input S;
1508 
endmodule
1509 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1510 
module FDD (Q, C, D);
1511 
parameter INIT = 1'b0;
1512 
output Q;
1513 
input C;
1514 
input D;
1515 
endmodule
1516 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1517 
module FDE_1 (Q, C, CE, D);
1518 
parameter INIT = 1'b0;
1519 
output Q;
1520 
input C;
1521 
input CE;
1522 
input D;
1523 
endmodule
1524 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1525 
module FDE (Q, C, CE, D);
1526 
parameter INIT = 1'b0;
1527 
output Q;
1528 
input C;
1529 
input CE;
1530 
input D;
1531 
endmodule
1532 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1533 
module FDP_1 (Q, C, D, PRE);
1534 
parameter INIT = 1'b1;
1535 
output Q;
1536 
input C;
1537 
input D;
1538 
input PRE;
1539 
endmodule
1540 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1541 
module FDPE_1 (Q, C, CE, D, PRE);
1542 
parameter INIT = 1'b1;
1543 
output Q;
1544 
input C;
1545 
input CE;
1546 
input D;
1547 
input PRE;
1548 
endmodule
1549 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1550 
module FDPE (Q, C, CE, D, PRE);
1551 
parameter INIT = 1'b1;
1552 
output Q;
1553 
input C;
1554 
input CE;
1555 
input D;
1556 
input PRE;
1557 
endmodule
1558 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1559 
module FDP (Q, C, D, PRE);
1560 
parameter INIT = 1'b1;
1561 
output Q;
1562 
input C;
1563 
input D;
1564 
input PRE;
1565 
endmodule
1566 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1567 
module FDR_1 (Q, C, D, R);
1568 
parameter INIT = 1'b0;
1569 
output Q;
1570 
input C;
1571 
input D;
1572 
input R;
1573 
endmodule
1574 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1575 
module FDRE_1 (Q, C, CE, D, R);
1576 
parameter INIT = 1'b0;
1577 
output Q;
1578 
input C;
1579 
input CE;
1580 
input D;
1581 
input R;
1582 
endmodule
1583 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1584 
module FDRE (Q, C, CE, D, R);
1585 
parameter INIT = 1'b0;
1586 
output Q;
1587 
input C;
1588 
input CE;
1589 
input D;
1590 
input R;
1591 
endmodule
1592 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1593 
module FDRS_1 (Q, C, D, R, S);
1594 
parameter INIT = 1'b0;
1595 
output Q;
1596 
input C;
1597 
input D;
1598 
input R;
1599 
input S;
1600 
endmodule
1601 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1602 
module FDRSE_1 (Q, C, CE, D, R, S);
1603 
parameter INIT = 1'b0;
1604 
output Q;
1605 
input C;
1606 
input CE;
1607 
input D;
1608 
input R;
1609 
input S;
1610 
endmodule
1611 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1612 
module FDRSE (Q, C, CE, D, R, S);
1613 
parameter INIT = 1'b0;
1614 
output Q;
1615 
input C;
1616 
input CE;
1617 
input D;
1618 
input R;
1619 
input S;
1620 
endmodule
1621 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1622 
module FDRS (Q, C, D, R, S);
1623 
parameter INIT = 1'b0;
1624 
output Q;
1625 
input C;
1626 
input D;
1627 
input R;
1628 
input S;
1629 
endmodule
1630 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1631 
module FDR (Q, C, D, R);
1632 
parameter INIT = 1'b0;
1633 
output Q;
1634 
input C;
1635 
input D;
1636 
input R;
1637 
endmodule
1638 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1639 
module FDS_1 (Q, C, D, S);
1640 
parameter INIT = 1'b1;
1641 
output Q;
1642 
input C;
1643 
input D;
1644 
input S;
1645 
endmodule
1646 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1647 
module FDSE_1 (Q, C, CE, D, S);
1648 
parameter INIT = 1'b1;
1649 
output Q;
1650 
input C;
1651 
input CE;
1652 
input D;
1653 
input S;
1654 
endmodule
1655 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1656 
module FDSE (Q, C, CE, D, S);
1657 
parameter INIT = 1'b1;
1658 
output Q;
1659 
input C;
1660 
input CE;
1661 
input D;
1662 
input S;
1663 
endmodule
1664 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1665 
module FDS (Q, C, D, S);
1666 
parameter INIT = 1'b1;
1667 
output Q;
1668 
input C;
1669 
input D;
1670 
input S;
1671 
endmodule
1672 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1673 
module FD (Q, C, D);
1674 
parameter INIT = 1'b0;
1675 
output Q;
1676 
input C;
1677 
input D;
1678 
endmodule
1679 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1680 
module FIFO16 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
1681 
parameter ALMOST_FULL_OFFSET = 12'h080;
1682 
parameter ALMOST_EMPTY_OFFSET = 12'h080;
1683 
parameter integer DATA_WIDTH = 36;
1684 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1685 
output ALMOSTEMPTY;
1686 
output ALMOSTFULL;
1687 
output [31:0] DO;
1688 
output [3:0] DOP;
1689 
output EMPTY;
1690 
output FULL;
1691 
output [11:0] RDCOUNT;
1692 
output RDERR;
1693 
output [11:0] WRCOUNT;
1694 
output WRERR;
1695 
input [31:0] DI;
1696 
input [3:0] DIP;
1697 
input RDCLK;
1698 
input RDEN;
1699 
input RST;
1700 
input WRCLK;
1701 
input WREN;
1702 
endmodule
1703 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1704 
module FIFO18_36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
1705 
parameter ALMOST_EMPTY_OFFSET = 9'h080;
1706 
parameter ALMOST_FULL_OFFSET = 9'h080;
1707 
parameter integer DO_REG = 1;
1708 
parameter EN_SYN = "FALSE";
1709 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1710 
parameter SIM_MODE = "SAFE";
1711 
output ALMOSTEMPTY;
1712 
output ALMOSTFULL;
1713 
output [31:0] DO;
1714 
output [3:0] DOP;
1715 
output EMPTY;
1716 
output FULL;
1717 
output [8:0] RDCOUNT;
1718 
output RDERR;
1719 
output [8:0] WRCOUNT;
1720 
output WRERR;
1721 
input [31:0] DI;
1722 
input [3:0] DIP;
1723 
input RDCLK;
1724 
input RDEN;
1725 
input RST;
1726 
input WRCLK;
1727 
input WREN;
1728 
endmodule
1729 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1730 
module FIFO18 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
1731 
parameter ALMOST_EMPTY_OFFSET = 12'h080;
1732 
parameter ALMOST_FULL_OFFSET = 12'h080;
1733 
parameter integer DATA_WIDTH = 4;
1734 
parameter integer DO_REG = 1;
1735 
parameter EN_SYN = "FALSE";
1736 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1737 
parameter SIM_MODE = "SAFE";
1738 
output ALMOSTEMPTY;
1739 
output ALMOSTFULL;
1740 
output [15:0] DO;
1741 
output [1:0] DOP;
1742 
output EMPTY;
1743 
output FULL;
1744 
output [11:0] RDCOUNT;
1745 
output RDERR;
1746 
output [11:0] WRCOUNT;
1747 
output WRERR;
1748 
input [15:0] DI;
1749 
input [1:0] DIP;
1750 
input RDCLK;
1751 
input RDEN;
1752 
input RST;
1753 
input WRCLK;
1754 
input WREN;
1755 
endmodule
1756 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1757 
module FIFO36_72_EXP (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN);
1758 
parameter ALMOST_EMPTY_OFFSET = 9'h080;
1759 
parameter ALMOST_FULL_OFFSET = 9'h080;
1760 
parameter integer DO_REG = 1;
1761 
parameter EN_ECC_WRITE = "FALSE";
1762 
parameter EN_ECC_READ = "FALSE";
1763 
parameter EN_SYN = "FALSE";
1764 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1765 
parameter SIM_MODE = "SAFE";
1766 
output ALMOSTEMPTY;
1767 
output ALMOSTFULL;
1768 
output DBITERR;
1769 
output [63:0] DO;
1770 
output [7:0] DOP;
1771 
output [7:0] ECCPARITY;
1772 
output EMPTY;
1773 
output FULL;
1774 
output [12:0] RDCOUNT;
1775 
output RDERR;
1776 
output SBITERR;
1777 
output [12:0] WRCOUNT;
1778 
output WRERR;
1779 
input [63:0] DI;
1780 
input [7:0] DIP;
1781 
input RDCLKL;
1782 
input RDCLKU;
1783 
input RDEN;
1784 
input RDRCLKL;
1785 
input RDRCLKU;
1786 
input RST;
1787 
input WRCLKL;
1788 
input WRCLKU;
1789 
input WREN;
1790 
endmodule
1791 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1792 
module FIFO36_72 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
1793 
parameter ALMOST_EMPTY_OFFSET = 9'h080;
1794 
parameter ALMOST_FULL_OFFSET = 9'h080;
1795 
parameter integer DO_REG = 1;
1796 
parameter EN_ECC_WRITE = "FALSE";
1797 
parameter EN_ECC_READ = "FALSE";
1798 
parameter EN_SYN = "FALSE";
1799 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1800 
parameter SIM_MODE = "SAFE";
1801 
output ALMOSTEMPTY;
1802 
output ALMOSTFULL;
1803 
output DBITERR;
1804 
output [63:0] DO;
1805 
output [7:0] DOP;
1806 
output [7:0] ECCPARITY;
1807 
output EMPTY;
1808 
output FULL;
1809 
output [8:0] RDCOUNT;
1810 
output RDERR;
1811 
output SBITERR;
1812 
output [8:0] WRCOUNT;
1813 
output WRERR;
1814 
input [63:0] DI;
1815 
input [7:0] DIP;
1816 
input RDCLK;
1817 
input RDEN;
1818 
input RST;
1819 
input WRCLK;
1820 
input WREN;
1821 
endmodule
1822 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1823 
module FIFO36_EXP (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN);
1824 
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
1825 
parameter ALMOST_FULL_OFFSET = 13'h0080;
1826 
parameter integer DATA_WIDTH = 4;
1827 
parameter integer DO_REG = 1;
1828 
parameter EN_SYN = "FALSE";
1829 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1830 
parameter SIM_MODE = "SAFE";
1831 
output ALMOSTEMPTY;
1832 
output ALMOSTFULL;
1833 
output [31:0] DO;
1834 
output [3:0] DOP;
1835 
output EMPTY;
1836 
output FULL;
1837 
output [12:0] RDCOUNT;
1838 
output RDERR;
1839 
output [12:0] WRCOUNT;
1840 
output WRERR;
1841 
input [31:0] DI;
1842 
input [3:0] DIP;
1843 
input RDCLKL;
1844 
input RDCLKU;
1845 
input RDEN;
1846 
input RDRCLKL;
1847 
input RDRCLKU;
1848 
input RST;
1849 
input WRCLKL;
1850 
input WRCLKU;
1851 
input WREN;
1852 
endmodule
1853 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1854 
module FIFO36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
1855 
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
1856 
parameter ALMOST_FULL_OFFSET = 13'h0080;
1857 
parameter integer DATA_WIDTH = 4;
1858 
parameter integer DO_REG = 1;
1859 
parameter EN_SYN = "FALSE";
1860 
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
1861 
parameter SIM_MODE = "SAFE";
1862 
output ALMOSTEMPTY;
1863 
output ALMOSTFULL;
1864 
output [31:0] DO;
1865 
output [3:0] DOP;
1866 
output EMPTY;
1867 
output FULL;
1868 
output [12:0] RDCOUNT;
1869 
output RDERR;
1870 
output [12:0] WRCOUNT;
1871 
output WRERR;
1872 
input [31:0] DI;
1873 
input [3:0] DIP;
1874 
input RDCLK;
1875 
input RDEN;
1876 
input RST;
1877 
input WRCLK;
1878 
input WREN;
1879 
endmodule
1880 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1881 
module FMAP (I1, I2, I3, I4, O);
1882 
input I1;
1883 
input I2;
1884 
input I3;
1885 
input I4;
1886 
input O;
1887 
endmodule
1888 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1889 
module FRAME_ECC_VIRTEX4 (ERROR, SYNDROME, SYNDROMEVALID);
1890 
output ERROR;
1891 
output [11:0] SYNDROME;
1892 
output SYNDROMEVALID;
1893 
endmodule
1894 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1895 
module FRAME_ECC_VIRTEX5 (CRCERROR, ECCERROR, SYNDROME, SYNDROMEVALID);
1896 
output CRCERROR;
1897 
output ECCERROR;
1898 
output [11:0] SYNDROME;
1899 
output SYNDROMEVALID;
1900 
endmodule
1901 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1902 
module FTCP (Q, C, CLR, PRE, T);
1903 
parameter INIT = 1'b0;
1904 
output Q;
1905 
input C;
1906 
input CLR;
1907 
input PRE;
1908 
input T;
1909 
endmodule
1910 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1911 
module FTC (Q, C, CLR, T);
1912 
output Q;
1913 
input C;
1914 
input CLR;
1915 
input T;
1916 
endmodule
1917 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1918 
module FTP (Q, C, PRE, T);
1919 
output Q;
1920 
input C;
1921 
input PRE;
1922 
input T;
1923 
endmodule
1924 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1925 
module GND (G);
1926 
output G;
1927 
endmodule
1928 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
1929 
module GT10_10GE_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
1930 
parameter integer CHAN_BOND_LIMIT = 16;
1931 
parameter CHAN_BOND_MODE = "OFF";
1932 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
1933 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
1934 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
1935 
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
1936 
parameter CHAN_BOND_64B66B_SV = "FALSE";
1937 
parameter integer CLK_COR_MAX_LAT = 36;
1938 
parameter integer CLK_COR_MIN_LAT = 28;
1939 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
1940 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
1941 
parameter CLK_COR_SEQ_2_USE = "TRUE";
1942 
parameter CLK_COR_SEQ_DROP = "FALSE";
1943 
parameter CLK_CORRECT_USE = "TRUE";
1944 
parameter PMA_PWR_CNTRL = 8'b11111111;
1945 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
1946 
parameter PMA_SPEED_USE = "PMA_SPEED";
1947 
parameter RX_BUFFER_USE = "TRUE";
1948 
parameter integer RX_LOS_INVALID_INCR = 1;
1949 
parameter integer RX_LOS_THRESHOLD = 4;
1950 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
1951 
parameter integer SH_CNT_MAX = 64;
1952 
parameter integer SH_INVALID_CNT_MAX = 16;
1953 
parameter TX_BUFFER_USE = "TRUE";
1954 
output CHBONDDONE;
1955 
output [4:0] CHBONDO;
1956 
output PMARXLOCK;
1957 
output [1:0] RXBUFSTATUS;
1958 
output [3:0] RXCHARISCOMMA;
1959 
output [3:0] RXCHARISK;
1960 
output [2:0] RXCLKCORCNT;
1961 
output RXCOMMADET;
1962 
output [31:0] RXDATA;
1963 
output [3:0] RXDISPERR;
1964 
output [1:0] RXLOSSOFSYNC;
1965 
output [3:0] RXNOTINTABLE;
1966 
output RXREALIGN;
1967 
output RXRECCLK;
1968 
output [3:0] RXRUNDISP;
1969 
output TXBUFERR;
1970 
output [3:0] TXKERR;
1971 
output TXN;
1972 
output TXOUTCLK;
1973 
output TXP;
1974 
output [3:0] TXRUNDISP;
1975 
input BREFCLKNIN;
1976 
input BREFCLKPIN;
1977 
input [4:0] CHBONDI;
1978 
input ENCHANSYNC;
1979 
input ENMCOMMAALIGN;
1980 
input ENPCOMMAALIGN;
1981 
input [1:0] LOOPBACK;
1982 
input PMAINIT;
1983 
input [5:0] PMAREGADDR;
1984 
input [7:0] PMAREGDATAIN;
1985 
input PMAREGRW;
1986 
input PMAREGSTROBE;
1987 
input [1:0] PMARXLOCKSEL;
1988 
input POWERDOWN;
1989 
input REFCLK;
1990 
input REFCLK2;
1991 
input REFCLKBSEL;
1992 
input REFCLKSEL;
1993 
input RXBLOCKSYNC64B66BUSE;
1994 
input RXCOMMADETUSE;
1995 
input [1:0] RXDATAWIDTH;
1996 
input RXDEC64B66BUSE;
1997 
input RXDEC8B10BUSE;
1998 
input RXDESCRAM64B66BUSE;
1999 
input RXIGNOREBTF;
2000 
input [1:0] RXINTDATAWIDTH;
2001 
input RXN;
2002 
input RXP;
2003 
input RXPOLARITY;
2004 
input RXRESET;
2005 
input RXSLIDE;
2006 
input RXUSRCLK;
2007 
input RXUSRCLK2;
2008 
input [3:0] TXBYPASS8B10B;
2009 
input [3:0] TXCHARDISPMODE;
2010 
input [3:0] TXCHARDISPVAL;
2011 
input [3:0] TXCHARISK;
2012 
input [31:0] TXDATA;
2013 
input [1:0] TXDATAWIDTH;
2014 
input TXENC64B66BUSE;
2015 
input TXENC8B10BUSE;
2016 
input TXGEARBOX64B66BUSE;
2017 
input TXINHIBIT;
2018 
input [1:0] TXINTDATAWIDTH;
2019 
input TXPOLARITY;
2020 
input TXRESET;
2021 
input TXSCRAM64B66BUSE;
2022 
input TXUSRCLK;
2023 
input TXUSRCLK2;
2024 
endmodule
2025 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2026 
module GT10_10GE_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2027 
parameter integer CHAN_BOND_LIMIT = 16;
2028 
parameter CHAN_BOND_MODE = "OFF";
2029 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2030 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2031 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2032 
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
2033 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2034 
parameter integer CLK_COR_MAX_LAT = 36;
2035 
parameter integer CLK_COR_MIN_LAT = 28;
2036 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2037 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2038 
parameter CLK_COR_SEQ_2_USE = "TRUE";
2039 
parameter CLK_COR_SEQ_DROP = "FALSE";
2040 
parameter CLK_CORRECT_USE = "TRUE";
2041 
parameter PMA_PWR_CNTRL = 8'b11111111;
2042 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2043 
parameter PMA_SPEED_USE = "PMA_SPEED";
2044 
parameter RX_BUFFER_USE = "TRUE";
2045 
parameter integer RX_LOS_INVALID_INCR = 1;
2046 
parameter integer RX_LOS_THRESHOLD = 4;
2047 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2048 
parameter integer SH_CNT_MAX = 64;
2049 
parameter integer SH_INVALID_CNT_MAX = 16;
2050 
parameter TX_BUFFER_USE = "TRUE";
2051 
output CHBONDDONE;
2052 
output [4:0] CHBONDO;
2053 
output PMARXLOCK;
2054 
output [1:0] RXBUFSTATUS;
2055 
output [7:0] RXCHARISCOMMA;
2056 
output [7:0] RXCHARISK;
2057 
output [2:0] RXCLKCORCNT;
2058 
output RXCOMMADET;
2059 
output [63:0] RXDATA;
2060 
output [7:0] RXDISPERR;
2061 
output [1:0] RXLOSSOFSYNC;
2062 
output [7:0] RXNOTINTABLE;
2063 
output RXREALIGN;
2064 
output RXRECCLK;
2065 
output [7:0] RXRUNDISP;
2066 
output TXBUFERR;
2067 
output [7:0] TXKERR;
2068 
output TXN;
2069 
output TXOUTCLK;
2070 
output TXP;
2071 
output [7:0] TXRUNDISP;
2072 
input BREFCLKNIN;
2073 
input BREFCLKPIN;
2074 
input [4:0] CHBONDI;
2075 
input ENCHANSYNC;
2076 
input ENMCOMMAALIGN;
2077 
input ENPCOMMAALIGN;
2078 
input [1:0] LOOPBACK;
2079 
input PMAINIT;
2080 
input [5:0] PMAREGADDR;
2081 
input [7:0] PMAREGDATAIN;
2082 
input PMAREGRW;
2083 
input PMAREGSTROBE;
2084 
input [1:0] PMARXLOCKSEL;
2085 
input POWERDOWN;
2086 
input REFCLK;
2087 
input REFCLK2;
2088 
input REFCLKBSEL;
2089 
input REFCLKSEL;
2090 
input RXBLOCKSYNC64B66BUSE;
2091 
input RXCOMMADETUSE;
2092 
input [1:0] RXDATAWIDTH;
2093 
input RXDEC64B66BUSE;
2094 
input RXDEC8B10BUSE;
2095 
input RXDESCRAM64B66BUSE;
2096 
input RXIGNOREBTF;
2097 
input [1:0] RXINTDATAWIDTH;
2098 
input RXN;
2099 
input RXP;
2100 
input RXPOLARITY;
2101 
input RXRESET;
2102 
input RXSLIDE;
2103 
input RXUSRCLK;
2104 
input RXUSRCLK2;
2105 
input [7:0] TXBYPASS8B10B;
2106 
input [7:0] TXCHARDISPMODE;
2107 
input [7:0] TXCHARDISPVAL;
2108 
input [7:0] TXCHARISK;
2109 
input [63:0] TXDATA;
2110 
input [1:0] TXDATAWIDTH;
2111 
input TXENC64B66BUSE;
2112 
input TXENC8B10BUSE;
2113 
input TXGEARBOX64B66BUSE;
2114 
input TXINHIBIT;
2115 
input [1:0] TXINTDATAWIDTH;
2116 
input TXPOLARITY;
2117 
input TXRESET;
2118 
input TXSCRAM64B66BUSE;
2119 
input TXUSRCLK;
2120 
input TXUSRCLK2;
2121 
endmodule
2122 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2123 
module GT10_10GFC_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2124 
parameter integer CHAN_BOND_LIMIT = 16;
2125 
parameter CHAN_BOND_MODE = "OFF";
2126 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2127 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2128 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2129 
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
2130 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2131 
parameter integer CLK_COR_MAX_LAT = 36;
2132 
parameter integer CLK_COR_MIN_LAT = 28;
2133 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2134 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2135 
parameter CLK_COR_SEQ_2_USE = "TRUE";
2136 
parameter CLK_COR_SEQ_DROP = "FALSE";
2137 
parameter CLK_CORRECT_USE = "TRUE";
2138 
parameter PMA_PWR_CNTRL = 8'b11111111;
2139 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2140 
parameter PMA_SPEED_USE = "PMA_SPEED";
2141 
parameter RX_BUFFER_USE = "TRUE";
2142 
parameter integer RX_LOS_INVALID_INCR = 1;
2143 
parameter integer RX_LOS_THRESHOLD = 4;
2144 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2145 
parameter integer SH_CNT_MAX = 64;
2146 
parameter integer SH_INVALID_CNT_MAX = 16;
2147 
parameter TX_BUFFER_USE = "TRUE";
2148 
output CHBONDDONE;
2149 
output [4:0] CHBONDO;
2150 
output PMARXLOCK;
2151 
output [1:0] RXBUFSTATUS;
2152 
output [3:0] RXCHARISCOMMA;
2153 
output [3:0] RXCHARISK;
2154 
output [2:0] RXCLKCORCNT;
2155 
output RXCOMMADET;
2156 
output [31:0] RXDATA;
2157 
output [3:0] RXDISPERR;
2158 
output [1:0] RXLOSSOFSYNC;
2159 
output [3:0] RXNOTINTABLE;
2160 
output RXREALIGN;
2161 
output RXRECCLK;
2162 
output [3:0] RXRUNDISP;
2163 
output TXBUFERR;
2164 
output [3:0] TXKERR;
2165 
output TXN;
2166 
output TXOUTCLK;
2167 
output TXP;
2168 
output [3:0] TXRUNDISP;
2169 
input BREFCLKNIN;
2170 
input BREFCLKPIN;
2171 
input [4:0] CHBONDI;
2172 
input ENCHANSYNC;
2173 
input ENMCOMMAALIGN;
2174 
input ENPCOMMAALIGN;
2175 
input [1:0] LOOPBACK;
2176 
input PMAINIT;
2177 
input [5:0] PMAREGADDR;
2178 
input [7:0] PMAREGDATAIN;
2179 
input PMAREGRW;
2180 
input PMAREGSTROBE;
2181 
input [1:0] PMARXLOCKSEL;
2182 
input POWERDOWN;
2183 
input REFCLK;
2184 
input REFCLK2;
2185 
input REFCLKBSEL;
2186 
input REFCLKSEL;
2187 
input RXBLOCKSYNC64B66BUSE;
2188 
input RXCOMMADETUSE;
2189 
input [1:0] RXDATAWIDTH;
2190 
input RXDEC64B66BUSE;
2191 
input RXDEC8B10BUSE;
2192 
input RXDESCRAM64B66BUSE;
2193 
input RXIGNOREBTF;
2194 
input [1:0] RXINTDATAWIDTH;
2195 
input RXN;
2196 
input RXP;
2197 
input RXPOLARITY;
2198 
input RXRESET;
2199 
input RXSLIDE;
2200 
input RXUSRCLK;
2201 
input RXUSRCLK2;
2202 
input [3:0] TXBYPASS8B10B;
2203 
input [3:0] TXCHARDISPMODE;
2204 
input [3:0] TXCHARDISPVAL;
2205 
input [3:0] TXCHARISK;
2206 
input [31:0] TXDATA;
2207 
input [1:0] TXDATAWIDTH;
2208 
input TXENC64B66BUSE;
2209 
input TXENC8B10BUSE;
2210 
input TXGEARBOX64B66BUSE;
2211 
input TXINHIBIT;
2212 
input [1:0] TXINTDATAWIDTH;
2213 
input TXPOLARITY;
2214 
input TXRESET;
2215 
input TXSCRAM64B66BUSE;
2216 
input TXUSRCLK;
2217 
input TXUSRCLK2;
2218 
endmodule
2219 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2220 
module GT10_10GFC_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2221 
parameter integer CHAN_BOND_LIMIT = 16;
2222 
parameter CHAN_BOND_MODE = "OFF";
2223 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2224 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2225 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2226 
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
2227 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2228 
parameter integer CLK_COR_MAX_LAT = 36;
2229 
parameter integer CLK_COR_MIN_LAT = 28;
2230 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2231 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2232 
parameter CLK_COR_SEQ_2_USE = "TRUE";
2233 
parameter CLK_COR_SEQ_DROP = "FALSE";
2234 
parameter CLK_CORRECT_USE = "TRUE";
2235 
parameter PMA_PWR_CNTRL = 8'b11111111;
2236 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2237 
parameter PMA_SPEED_USE = "PMA_SPEED";
2238 
parameter RX_BUFFER_USE = "TRUE";
2239 
parameter integer RX_LOS_INVALID_INCR = 1;
2240 
parameter integer RX_LOS_THRESHOLD = 4;
2241 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2242 
parameter integer SH_CNT_MAX = 64;
2243 
parameter integer SH_INVALID_CNT_MAX = 16;
2244 
parameter TX_BUFFER_USE = "TRUE";
2245 
output CHBONDDONE;
2246 
output [4:0] CHBONDO;
2247 
output PMARXLOCK;
2248 
output [1:0] RXBUFSTATUS;
2249 
output [7:0] RXCHARISCOMMA;
2250 
output [7:0] RXCHARISK;
2251 
output [2:0] RXCLKCORCNT;
2252 
output RXCOMMADET;
2253 
output [63:0] RXDATA;
2254 
output [7:0] RXDISPERR;
2255 
output [1:0] RXLOSSOFSYNC;
2256 
output [7:0] RXNOTINTABLE;
2257 
output RXREALIGN;
2258 
output RXRECCLK;
2259 
output [7:0] RXRUNDISP;
2260 
output TXBUFERR;
2261 
output [7:0] TXKERR;
2262 
output TXN;
2263 
output TXOUTCLK;
2264 
output TXP;
2265 
output [7:0] TXRUNDISP;
2266 
input BREFCLKNIN;
2267 
input BREFCLKPIN;
2268 
input [4:0] CHBONDI;
2269 
input ENCHANSYNC;
2270 
input ENMCOMMAALIGN;
2271 
input ENPCOMMAALIGN;
2272 
input [1:0] LOOPBACK;
2273 
input PMAINIT;
2274 
input [5:0] PMAREGADDR;
2275 
input [7:0] PMAREGDATAIN;
2276 
input PMAREGRW;
2277 
input PMAREGSTROBE;
2278 
input [1:0] PMARXLOCKSEL;
2279 
input POWERDOWN;
2280 
input REFCLK;
2281 
input REFCLK2;
2282 
input REFCLKBSEL;
2283 
input REFCLKSEL;
2284 
input RXBLOCKSYNC64B66BUSE;
2285 
input RXCOMMADETUSE;
2286 
input [1:0] RXDATAWIDTH;
2287 
input RXDEC64B66BUSE;
2288 
input RXDEC8B10BUSE;
2289 
input RXDESCRAM64B66BUSE;
2290 
input RXIGNOREBTF;
2291 
input [1:0] RXINTDATAWIDTH;
2292 
input RXN;
2293 
input RXP;
2294 
input RXPOLARITY;
2295 
input RXRESET;
2296 
input RXSLIDE;
2297 
input RXUSRCLK;
2298 
input RXUSRCLK2;
2299 
input [7:0] TXBYPASS8B10B;
2300 
input [7:0] TXCHARDISPMODE;
2301 
input [7:0] TXCHARDISPVAL;
2302 
input [7:0] TXCHARISK;
2303 
input [63:0] TXDATA;
2304 
input [1:0] TXDATAWIDTH;
2305 
input TXENC64B66BUSE;
2306 
input TXENC8B10BUSE;
2307 
input TXGEARBOX64B66BUSE;
2308 
input TXINHIBIT;
2309 
input [1:0] TXINTDATAWIDTH;
2310 
input TXPOLARITY;
2311 
input TXRESET;
2312 
input TXSCRAM64B66BUSE;
2313 
input TXUSRCLK;
2314 
input TXUSRCLK2;
2315 
endmodule
2316 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2317 
module GT10_AURORA_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2318 
parameter integer ALIGN_COMMA_WORD = 1;
2319 
parameter integer CHAN_BOND_LIMIT = 16;
2320 
parameter CHAN_BOND_MODE = "OFF";
2321 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2322 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2323 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2324 
parameter CLK_COR_8B10B_DE = "FALSE";
2325 
parameter integer CLK_COR_MAX_LAT = 36;
2326 
parameter integer CLK_COR_MIN_LAT = 28;
2327 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2328 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2329 
parameter CLK_COR_SEQ_DROP = "FALSE";
2330 
parameter CLK_CORRECT_USE = "TRUE";
2331 
parameter PMA_PWR_CNTRL = 8'b11111111;
2332 
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32263068090104a628;
2333 
parameter PMA_SPEED_USE = "PMA_SPEED";
2334 
parameter RX_BUFFER_USE = "TRUE";
2335 
parameter integer RX_LOS_INVALID_INCR = 1;
2336 
parameter integer RX_LOS_THRESHOLD = 4;
2337 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2338 
parameter TX_BUFFER_USE = "TRUE";
2339 
output CHBONDDONE;
2340 
output [4:0] CHBONDO;
2341 
output PMARXLOCK;
2342 
output [1:0] RXBUFSTATUS;
2343 
output [0:0] RXCHARISCOMMA;
2344 
output [0:0] RXCHARISK;
2345 
output [2:0] RXCLKCORCNT;
2346 
output RXCOMMADET;
2347 
output [7:0] RXDATA;
2348 
output [0:0] RXDISPERR;
2349 
output [1:0] RXLOSSOFSYNC;
2350 
output [0:0] RXNOTINTABLE;
2351 
output RXREALIGN;
2352 
output RXRECCLK;
2353 
output [0:0] RXRUNDISP;
2354 
output TXBUFERR;
2355 
output [0:0] TXKERR;
2356 
output TXN;
2357 
output TXOUTCLK;
2358 
output TXP;
2359 
output [0:0] TXRUNDISP;
2360 
input BREFCLKNIN;
2361 
input BREFCLKPIN;
2362 
input [4:0] CHBONDI;
2363 
input ENCHANSYNC;
2364 
input ENMCOMMAALIGN;
2365 
input ENPCOMMAALIGN;
2366 
input [1:0] LOOPBACK;
2367 
input PMAINIT;
2368 
input [5:0] PMAREGADDR;
2369 
input [7:0] PMAREGDATAIN;
2370 
input PMAREGRW;
2371 
input PMAREGSTROBE;
2372 
input [1:0] PMARXLOCKSEL;
2373 
input POWERDOWN;
2374 
input REFCLK;
2375 
input REFCLK2;
2376 
input REFCLKBSEL;
2377 
input REFCLKSEL;
2378 
input RXBLOCKSYNC64B66BUSE;
2379 
input RXCOMMADETUSE;
2380 
input [1:0] RXDATAWIDTH;
2381 
input RXDEC64B66BUSE;
2382 
input RXDEC8B10BUSE;
2383 
input RXDESCRAM64B66BUSE;
2384 
input RXIGNOREBTF;
2385 
input [1:0] RXINTDATAWIDTH;
2386 
input RXN;
2387 
input RXP;
2388 
input RXPOLARITY;
2389 
input RXRESET;
2390 
input RXSLIDE;
2391 
input RXUSRCLK;
2392 
input RXUSRCLK2;
2393 
input [0:0] TXBYPASS8B10B;
2394 
input [0:0] TXCHARDISPMODE;
2395 
input [0:0] TXCHARDISPVAL;
2396 
input [0:0] TXCHARISK;
2397 
input [7:0] TXDATA;
2398 
input [1:0] TXDATAWIDTH;
2399 
input TXENC64B66BUSE;
2400 
input TXENC8B10BUSE;
2401 
input TXGEARBOX64B66BUSE;
2402 
input TXINHIBIT;
2403 
input [1:0] TXINTDATAWIDTH;
2404 
input TXPOLARITY;
2405 
input TXRESET;
2406 
input TXSCRAM64B66BUSE;
2407 
input TXUSRCLK;
2408 
input TXUSRCLK2;
2409 
endmodule
2410 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2411 
module GT10_AURORA_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2412 
parameter integer ALIGN_COMMA_WORD = 1;
2413 
parameter integer CHAN_BOND_LIMIT = 16;
2414 
parameter CHAN_BOND_MODE = "OFF";
2415 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2416 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2417 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2418 
parameter CLK_COR_8B10B_DE = "FALSE";
2419 
parameter integer CLK_COR_MAX_LAT = 36;
2420 
parameter integer CLK_COR_MIN_LAT = 28;
2421 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2422 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2423 
parameter CLK_COR_SEQ_DROP = "FALSE";
2424 
parameter CLK_CORRECT_USE = "TRUE";
2425 
parameter PMA_PWR_CNTRL = 8'b11111111;
2426 
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32663068090105a628;
2427 
parameter PMA_SPEED_USE = "PMA_SPEED";
2428 
parameter RX_BUFFER_USE = "TRUE";
2429 
parameter integer RX_LOS_INVALID_INCR = 1;
2430 
parameter integer RX_LOS_THRESHOLD = 4;
2431 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2432 
parameter TX_BUFFER_USE = "TRUE";
2433 
output CHBONDDONE;
2434 
output [4:0] CHBONDO;
2435 
output PMARXLOCK;
2436 
output [1:0] RXBUFSTATUS;
2437 
output [1:0] RXCHARISCOMMA;
2438 
output [1:0] RXCHARISK;
2439 
output [2:0] RXCLKCORCNT;
2440 
output RXCOMMADET;
2441 
output [15:0] RXDATA;
2442 
output [1:0] RXDISPERR;
2443 
output [1:0] RXLOSSOFSYNC;
2444 
output [1:0] RXNOTINTABLE;
2445 
output RXREALIGN;
2446 
output RXRECCLK;
2447 
output [1:0] RXRUNDISP;
2448 
output TXBUFERR;
2449 
output [1:0] TXKERR;
2450 
output TXN;
2451 
output TXOUTCLK;
2452 
output TXP;
2453 
output [1:0] TXRUNDISP;
2454 
input BREFCLKNIN;
2455 
input BREFCLKPIN;
2456 
input [4:0] CHBONDI;
2457 
input ENCHANSYNC;
2458 
input ENMCOMMAALIGN;
2459 
input ENPCOMMAALIGN;
2460 
input [1:0] LOOPBACK;
2461 
input PMAINIT;
2462 
input [5:0] PMAREGADDR;
2463 
input [7:0] PMAREGDATAIN;
2464 
input PMAREGRW;
2465 
input PMAREGSTROBE;
2466 
input [1:0] PMARXLOCKSEL;
2467 
input POWERDOWN;
2468 
input REFCLK;
2469 
input REFCLK2;
2470 
input REFCLKBSEL;
2471 
input REFCLKSEL;
2472 
input RXBLOCKSYNC64B66BUSE;
2473 
input RXCOMMADETUSE;
2474 
input [1:0] RXDATAWIDTH;
2475 
input RXDEC64B66BUSE;
2476 
input RXDEC8B10BUSE;
2477 
input RXDESCRAM64B66BUSE;
2478 
input RXIGNOREBTF;
2479 
input [1:0] RXINTDATAWIDTH;
2480 
input RXN;
2481 
input RXP;
2482 
input RXPOLARITY;
2483 
input RXRESET;
2484 
input RXSLIDE;
2485 
input RXUSRCLK;
2486 
input RXUSRCLK2;
2487 
input [1:0] TXBYPASS8B10B;
2488 
input [1:0] TXCHARDISPMODE;
2489 
input [1:0] TXCHARDISPVAL;
2490 
input [1:0] TXCHARISK;
2491 
input [15:0] TXDATA;
2492 
input [1:0] TXDATAWIDTH;
2493 
input TXENC64B66BUSE;
2494 
input TXENC8B10BUSE;
2495 
input TXGEARBOX64B66BUSE;
2496 
input TXINHIBIT;
2497 
input [1:0] TXINTDATAWIDTH;
2498 
input TXPOLARITY;
2499 
input TXRESET;
2500 
input TXSCRAM64B66BUSE;
2501 
input TXUSRCLK;
2502 
input TXUSRCLK2;
2503 
endmodule
2504 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2505 
module GT10_AURORA_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2506 
parameter integer ALIGN_COMMA_WORD = 1;
2507 
parameter integer CHAN_BOND_LIMIT = 16;
2508 
parameter CHAN_BOND_MODE = "OFF";
2509 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2510 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2511 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2512 
parameter CLK_COR_8B10B_DE = "FALSE";
2513 
parameter integer CLK_COR_MAX_LAT = 36;
2514 
parameter integer CLK_COR_MIN_LAT = 28;
2515 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2516 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2517 
parameter CLK_COR_SEQ_DROP = "FALSE";
2518 
parameter CLK_CORRECT_USE = "TRUE";
2519 
parameter PMA_PWR_CNTRL = 8'b11111111;
2520 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a628;
2521 
parameter PMA_SPEED_USE = "PMA_SPEED";
2522 
parameter RX_BUFFER_USE = "TRUE";
2523 
parameter integer RX_LOS_INVALID_INCR = 1;
2524 
parameter integer RX_LOS_THRESHOLD = 4;
2525 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2526 
parameter TX_BUFFER_USE = "TRUE";
2527 
output CHBONDDONE;
2528 
output [4:0] CHBONDO;
2529 
output PMARXLOCK;
2530 
output [1:0] RXBUFSTATUS;
2531 
output [3:0] RXCHARISCOMMA;
2532 
output [3:0] RXCHARISK;
2533 
output [2:0] RXCLKCORCNT;
2534 
output RXCOMMADET;
2535 
output [31:0] RXDATA;
2536 
output [3:0] RXDISPERR;
2537 
output [1:0] RXLOSSOFSYNC;
2538 
output [3:0] RXNOTINTABLE;
2539 
output RXREALIGN;
2540 
output RXRECCLK;
2541 
output [3:0] RXRUNDISP;
2542 
output TXBUFERR;
2543 
output [3:0] TXKERR;
2544 
output TXN;
2545 
output TXOUTCLK;
2546 
output TXP;
2547 
output [3:0] TXRUNDISP;
2548 
input BREFCLKNIN;
2549 
input BREFCLKPIN;
2550 
input [4:0] CHBONDI;
2551 
input ENCHANSYNC;
2552 
input ENMCOMMAALIGN;
2553 
input ENPCOMMAALIGN;
2554 
input [1:0] LOOPBACK;
2555 
input PMAINIT;
2556 
input [5:0] PMAREGADDR;
2557 
input [7:0] PMAREGDATAIN;
2558 
input PMAREGRW;
2559 
input PMAREGSTROBE;
2560 
input [1:0] PMARXLOCKSEL;
2561 
input POWERDOWN;
2562 
input REFCLK;
2563 
input REFCLK2;
2564 
input REFCLKBSEL;
2565 
input REFCLKSEL;
2566 
input RXBLOCKSYNC64B66BUSE;
2567 
input RXCOMMADETUSE;
2568 
input [1:0] RXDATAWIDTH;
2569 
input RXDEC64B66BUSE;
2570 
input RXDEC8B10BUSE;
2571 
input RXDESCRAM64B66BUSE;
2572 
input RXIGNOREBTF;
2573 
input [1:0] RXINTDATAWIDTH;
2574 
input RXN;
2575 
input RXP;
2576 
input RXPOLARITY;
2577 
input RXRESET;
2578 
input RXSLIDE;
2579 
input RXUSRCLK;
2580 
input RXUSRCLK2;
2581 
input [3:0] TXBYPASS8B10B;
2582 
input [3:0] TXCHARDISPMODE;
2583 
input [3:0] TXCHARDISPVAL;
2584 
input [3:0] TXCHARISK;
2585 
input [31:0] TXDATA;
2586 
input [1:0] TXDATAWIDTH;
2587 
input TXENC64B66BUSE;
2588 
input TXENC8B10BUSE;
2589 
input TXGEARBOX64B66BUSE;
2590 
input TXINHIBIT;
2591 
input [1:0] TXINTDATAWIDTH;
2592 
input TXPOLARITY;
2593 
input TXRESET;
2594 
input TXSCRAM64B66BUSE;
2595 
input TXUSRCLK;
2596 
input TXUSRCLK2;
2597 
endmodule
2598 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2599 
module GT10_AURORAX_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2600 
parameter integer CHAN_BOND_LIMIT = 16;
2601 
parameter CHAN_BOND_MODE = "OFF";
2602 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2603 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2604 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2605 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2606 
parameter integer CLK_COR_MAX_LAT = 36;
2607 
parameter integer CLK_COR_MIN_LAT = 28;
2608 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2609 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2610 
parameter CLK_COR_SEQ_DROP = "FALSE";
2611 
parameter CLK_CORRECT_USE = "TRUE";
2612 
parameter PMA_PWR_CNTRL = 8'b11111111;
2613 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2614 
parameter PMA_SPEED_USE = "PMA_SPEED";
2615 
parameter RX_BUFFER_USE = "TRUE";
2616 
parameter integer RX_LOS_INVALID_INCR = 1;
2617 
parameter integer RX_LOS_THRESHOLD = 4;
2618 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2619 
parameter integer SH_CNT_MAX = 64;
2620 
parameter integer SH_INVALID_CNT_MAX = 16;
2621 
parameter TX_BUFFER_USE = "TRUE";
2622 
output CHBONDDONE;
2623 
output [4:0] CHBONDO;
2624 
output PMARXLOCK;
2625 
output [1:0] RXBUFSTATUS;
2626 
output [3:0] RXCHARISCOMMA;
2627 
output [3:0] RXCHARISK;
2628 
output [2:0] RXCLKCORCNT;
2629 
output RXCOMMADET;
2630 
output [31:0] RXDATA;
2631 
output [3:0] RXDISPERR;
2632 
output [1:0] RXLOSSOFSYNC;
2633 
output [3:0] RXNOTINTABLE;
2634 
output RXREALIGN;
2635 
output RXRECCLK;
2636 
output [3:0] RXRUNDISP;
2637 
output TXBUFERR;
2638 
output [3:0] TXKERR;
2639 
output TXN;
2640 
output TXOUTCLK;
2641 
output TXP;
2642 
output [3:0] TXRUNDISP;
2643 
input BREFCLKNIN;
2644 
input BREFCLKPIN;
2645 
input [4:0] CHBONDI;
2646 
input ENCHANSYNC;
2647 
input ENMCOMMAALIGN;
2648 
input ENPCOMMAALIGN;
2649 
input [1:0] LOOPBACK;
2650 
input PMAINIT;
2651 
input [5:0] PMAREGADDR;
2652 
input [7:0] PMAREGDATAIN;
2653 
input PMAREGRW;
2654 
input PMAREGSTROBE;
2655 
input [1:0] PMARXLOCKSEL;
2656 
input POWERDOWN;
2657 
input REFCLK;
2658 
input REFCLK2;
2659 
input REFCLKBSEL;
2660 
input REFCLKSEL;
2661 
input RXBLOCKSYNC64B66BUSE;
2662 
input RXCOMMADETUSE;
2663 
input [1:0] RXDATAWIDTH;
2664 
input RXDEC64B66BUSE;
2665 
input RXDEC8B10BUSE;
2666 
input RXDESCRAM64B66BUSE;
2667 
input RXIGNOREBTF;
2668 
input [1:0] RXINTDATAWIDTH;
2669 
input RXN;
2670 
input RXP;
2671 
input RXPOLARITY;
2672 
input RXRESET;
2673 
input RXSLIDE;
2674 
input RXUSRCLK;
2675 
input RXUSRCLK2;
2676 
input [3:0] TXBYPASS8B10B;
2677 
input [3:0] TXCHARDISPMODE;
2678 
input [3:0] TXCHARDISPVAL;
2679 
input [3:0] TXCHARISK;
2680 
input [31:0] TXDATA;
2681 
input [1:0] TXDATAWIDTH;
2682 
input TXENC64B66BUSE;
2683 
input TXENC8B10BUSE;
2684 
input TXGEARBOX64B66BUSE;
2685 
input TXINHIBIT;
2686 
input [1:0] TXINTDATAWIDTH;
2687 
input TXPOLARITY;
2688 
input TXRESET;
2689 
input TXSCRAM64B66BUSE;
2690 
input TXUSRCLK;
2691 
input TXUSRCLK2;
2692 
endmodule
2693 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2694 
module GT10_AURORAX_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2695 
parameter integer CHAN_BOND_LIMIT = 16;
2696 
parameter CHAN_BOND_MODE = "OFF";
2697 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2698 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2699 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2700 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2701 
parameter integer CLK_COR_MAX_LAT = 36;
2702 
parameter integer CLK_COR_MIN_LAT = 28;
2703 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2704 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2705 
parameter CLK_COR_SEQ_DROP = "FALSE";
2706 
parameter CLK_CORRECT_USE = "TRUE";
2707 
parameter PMA_PWR_CNTRL = 8'b11111111;
2708 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2709 
parameter PMA_SPEED_USE = "PMA_SPEED";
2710 
parameter RX_BUFFER_USE = "TRUE";
2711 
parameter integer RX_LOS_INVALID_INCR = 1;
2712 
parameter integer RX_LOS_THRESHOLD = 4;
2713 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2714 
parameter integer SH_CNT_MAX = 64;
2715 
parameter integer SH_INVALID_CNT_MAX = 16;
2716 
parameter TX_BUFFER_USE = "TRUE";
2717 
output CHBONDDONE;
2718 
output [4:0] CHBONDO;
2719 
output PMARXLOCK;
2720 
output [1:0] RXBUFSTATUS;
2721 
output [7:0] RXCHARISCOMMA;
2722 
output [7:0] RXCHARISK;
2723 
output [2:0] RXCLKCORCNT;
2724 
output RXCOMMADET;
2725 
output [63:0] RXDATA;
2726 
output [7:0] RXDISPERR;
2727 
output [1:0] RXLOSSOFSYNC;
2728 
output [7:0] RXNOTINTABLE;
2729 
output RXREALIGN;
2730 
output RXRECCLK;
2731 
output [7:0] RXRUNDISP;
2732 
output TXBUFERR;
2733 
output [7:0] TXKERR;
2734 
output TXN;
2735 
output TXOUTCLK;
2736 
output TXP;
2737 
output [7:0] TXRUNDISP;
2738 
input BREFCLKNIN;
2739 
input BREFCLKPIN;
2740 
input [4:0] CHBONDI;
2741 
input ENCHANSYNC;
2742 
input ENMCOMMAALIGN;
2743 
input ENPCOMMAALIGN;
2744 
input [1:0] LOOPBACK;
2745 
input PMAINIT;
2746 
input [5:0] PMAREGADDR;
2747 
input [7:0] PMAREGDATAIN;
2748 
input PMAREGRW;
2749 
input PMAREGSTROBE;
2750 
input [1:0] PMARXLOCKSEL;
2751 
input POWERDOWN;
2752 
input REFCLK;
2753 
input REFCLK2;
2754 
input REFCLKBSEL;
2755 
input REFCLKSEL;
2756 
input RXBLOCKSYNC64B66BUSE;
2757 
input RXCOMMADETUSE;
2758 
input [1:0] RXDATAWIDTH;
2759 
input RXDEC64B66BUSE;
2760 
input RXDEC8B10BUSE;
2761 
input RXDESCRAM64B66BUSE;
2762 
input RXIGNOREBTF;
2763 
input [1:0] RXINTDATAWIDTH;
2764 
input RXN;
2765 
input RXP;
2766 
input RXPOLARITY;
2767 
input RXRESET;
2768 
input RXSLIDE;
2769 
input RXUSRCLK;
2770 
input RXUSRCLK2;
2771 
input [7:0] TXBYPASS8B10B;
2772 
input [7:0] TXCHARDISPMODE;
2773 
input [7:0] TXCHARDISPVAL;
2774 
input [7:0] TXCHARISK;
2775 
input [63:0] TXDATA;
2776 
input [1:0] TXDATAWIDTH;
2777 
input TXENC64B66BUSE;
2778 
input TXENC8B10BUSE;
2779 
input TXGEARBOX64B66BUSE;
2780 
input TXINHIBIT;
2781 
input [1:0] TXINTDATAWIDTH;
2782 
input TXPOLARITY;
2783 
input TXRESET;
2784 
input TXSCRAM64B66BUSE;
2785 
input TXUSRCLK;
2786 
input TXUSRCLK2;
2787 
endmodule
2788 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2789 
module GT10_CUSTOM (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2790 
parameter integer ALIGN_COMMA_WORD = 1;
2791 
parameter integer CHAN_BOND_LIMIT = 16;
2792 
parameter CHAN_BOND_MODE = "OFF";
2793 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2794 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
2795 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
2796 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
2797 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
2798 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2799 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
2800 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
2801 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
2802 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
2803 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2804 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
2805 
parameter integer CHAN_BOND_SEQ_LEN = 1;
2806 
parameter CHAN_BOND_64B66B_SV = "FALSE";
2807 
parameter CLK_COR_8B10B_DE = "FALSE";
2808 
parameter integer CLK_COR_MAX_LAT = 36;
2809 
parameter integer CLK_COR_MIN_LAT = 28;
2810 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
2811 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
2812 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
2813 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
2814 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2815 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
2816 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
2817 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
2818 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
2819 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2820 
parameter CLK_COR_SEQ_2_USE = "FALSE";
2821 
parameter CLK_COR_SEQ_DROP = "FALSE";
2822 
parameter integer CLK_COR_SEQ_LEN = 1;
2823 
parameter CLK_CORRECT_USE = "TRUE";
2824 
parameter COMMA_10B_MASK = 10'b0001111111;
2825 
parameter DEC_MCOMMA_DETECT = "TRUE";
2826 
parameter DEC_PCOMMA_DETECT = "TRUE";
2827 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
2828 
parameter MCOMMA_10B_VALUE = 10'b1010000011;
2829 
parameter MCOMMA_DETECT = "TRUE";
2830 
parameter PCOMMA_10B_VALUE = 10'b0101111100;
2831 
parameter PCOMMA_DETECT = "TRUE";
2832 
parameter PMA_PWR_CNTRL = 8'b11111111;
2833 
parameter PMA_SPEED = "0_32";
2834 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
2835 
parameter PMA_SPEED_USE = "PMA_SPEED";
2836 
parameter RX_BUFFER_USE = "TRUE";
2837 
parameter integer RX_LOS_INVALID_INCR = 1;
2838 
parameter integer RX_LOS_THRESHOLD = 4;
2839 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2840 
parameter integer SH_CNT_MAX = 64;
2841 
parameter integer SH_INVALID_CNT_MAX = 16;
2842 
parameter TX_BUFFER_USE = "TRUE";
2843 
output CHBONDDONE;
2844 
output [4:0] CHBONDO;
2845 
output PMARXLOCK;
2846 
output [1:0] RXBUFSTATUS;
2847 
output [7:0] RXCHARISCOMMA;
2848 
output [7:0] RXCHARISK;
2849 
output [2:0] RXCLKCORCNT;
2850 
output RXCOMMADET;
2851 
output [63:0] RXDATA;
2852 
output [7:0] RXDISPERR;
2853 
output [1:0] RXLOSSOFSYNC;
2854 
output [7:0] RXNOTINTABLE;
2855 
output RXREALIGN;
2856 
output RXRECCLK;
2857 
output [7:0] RXRUNDISP;
2858 
output TXBUFERR;
2859 
output [7:0] TXKERR;
2860 
output TXN;
2861 
output TXOUTCLK;
2862 
output TXP;
2863 
output [7:0] TXRUNDISP;
2864 
input BREFCLKNIN;
2865 
input BREFCLKPIN;
2866 
input [4:0] CHBONDI;
2867 
input ENCHANSYNC;
2868 
input ENMCOMMAALIGN;
2869 
input ENPCOMMAALIGN;
2870 
input [1:0] LOOPBACK;
2871 
input PMAINIT;
2872 
input [5:0] PMAREGADDR;
2873 
input [7:0] PMAREGDATAIN;
2874 
input PMAREGRW;
2875 
input PMAREGSTROBE;
2876 
input [1:0] PMARXLOCKSEL;
2877 
input POWERDOWN;
2878 
input REFCLK;
2879 
input REFCLK2;
2880 
input REFCLKBSEL;
2881 
input REFCLKSEL;
2882 
input RXBLOCKSYNC64B66BUSE;
2883 
input RXCOMMADETUSE;
2884 
input [1:0] RXDATAWIDTH;
2885 
input RXDEC64B66BUSE;
2886 
input RXDEC8B10BUSE;
2887 
input RXDESCRAM64B66BUSE;
2888 
input RXIGNOREBTF;
2889 
input [1:0] RXINTDATAWIDTH;
2890 
input RXN;
2891 
input RXP;
2892 
input RXPOLARITY;
2893 
input RXRESET;
2894 
input RXSLIDE;
2895 
input RXUSRCLK;
2896 
input RXUSRCLK2;
2897 
input [7:0] TXBYPASS8B10B;
2898 
input [7:0] TXCHARDISPMODE;
2899 
input [7:0] TXCHARDISPVAL;
2900 
input [7:0] TXCHARISK;
2901 
input [63:0] TXDATA;
2902 
input [1:0] TXDATAWIDTH;
2903 
input TXENC64B66BUSE;
2904 
input TXENC8B10BUSE;
2905 
input TXGEARBOX64B66BUSE;
2906 
input TXINHIBIT;
2907 
input [1:0] TXINTDATAWIDTH;
2908 
input TXPOLARITY;
2909 
input TXRESET;
2910 
input TXSCRAM64B66BUSE;
2911 
input TXUSRCLK;
2912 
input TXUSRCLK2;
2913 
endmodule
2914 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
2915 
module GT10_INFINIBAND_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
2916 
parameter integer ALIGN_COMMA_WORD = 2;
2917 
parameter integer CHAN_BOND_LIMIT = 16;
2918 
parameter CHAN_BOND_MODE = "OFF";
2919 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
2920 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
2921 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
2922 
parameter integer CHAN_BOND_SEQ_LEN = 2;
2923 
parameter CLK_COR_8B10B_DE = "FALSE";
2924 
parameter integer CLK_COR_MAX_LAT = 36;
2925 
parameter integer CLK_COR_MIN_LAT = 28;
2926 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
2927 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
2928 
parameter CLK_COR_SEQ_2_USE = "FALSE";
2929 
parameter CLK_COR_SEQ_DROP = "FALSE";
2930 
parameter integer CLK_COR_SEQ_LEN = 2;
2931 
parameter CLK_CORRECT_USE = "TRUE";
2932 
parameter DEC_MCOMMA_DETECT = "TRUE";
2933 
parameter DEC_PCOMMA_DETECT = "TRUE";
2934 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
2935 
parameter LANE_ID = 11'b00000000000;
2936 
parameter PMA_PWR_CNTRL = 8'b11111111;
2937 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132263068090104a620;
2938 
parameter PMA_SPEED_USE = "PMA_SPEED";
2939 
parameter RX_BUFFER_USE = "TRUE";
2940 
parameter integer RX_LOS_INVALID_INCR = 1;
2941 
parameter integer RX_LOS_THRESHOLD = 4;
2942 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
2943 
parameter TX_BUFFER_USE = "TRUE";
2944 
output CHBONDDONE;
2945 
output [4:0] CHBONDO;
2946 
output PMARXLOCK;
2947 
output [1:0] RXBUFSTATUS;
2948 
output [0:0] RXCHARISCOMMA;
2949 
output [0:0] RXCHARISK;
2950 
output [2:0] RXCLKCORCNT;
2951 
output RXCOMMADET;
2952 
output [7:0] RXDATA;
2953 
output [0:0] RXDISPERR;
2954 
output [1:0] RXLOSSOFSYNC;
2955 
output [0:0] RXNOTINTABLE;
2956 
output RXREALIGN;
2957 
output RXRECCLK;
2958 
output [0:0] RXRUNDISP;
2959 
output TXBUFERR;
2960 
output [0:0] TXKERR;
2961 
output TXN;
2962 
output TXOUTCLK;
2963 
output TXP;
2964 
output [0:0] TXRUNDISP;
2965 
input BREFCLKNIN;
2966 
input BREFCLKPIN;
2967 
input [4:0] CHBONDI;
2968 
input ENCHANSYNC;
2969 
input ENMCOMMAALIGN;
2970 
input ENPCOMMAALIGN;
2971 
input [1:0] LOOPBACK;
2972 
input PMAINIT;
2973 
input [5:0] PMAREGADDR;
2974 
input [7:0] PMAREGDATAIN;
2975 
input PMAREGRW;
2976 
input PMAREGSTROBE;
2977 
input [1:0] PMARXLOCKSEL;
2978 
input POWERDOWN;
2979 
input REFCLK;
2980 
input REFCLK2;
2981 
input REFCLKBSEL;
2982 
input REFCLKSEL;
2983 
input RXBLOCKSYNC64B66BUSE;
2984 
input RXCOMMADETUSE;
2985 
input [1:0] RXDATAWIDTH;
2986 
input RXDEC64B66BUSE;
2987 
input RXDEC8B10BUSE;
2988 
input RXDESCRAM64B66BUSE;
2989 
input RXIGNOREBTF;
2990 
input [1:0] RXINTDATAWIDTH;
2991 
input RXN;
2992 
input RXP;
2993 
input RXPOLARITY;
2994 
input RXRESET;
2995 
input RXSLIDE;
2996 
input RXUSRCLK;
2997 
input RXUSRCLK2;
2998 
input [0:0] TXBYPASS8B10B;
2999 
input [0:0] TXCHARDISPMODE;
3000 
input [0:0] TXCHARDISPVAL;
3001 
input [0:0] TXCHARISK;
3002 
input [7:0] TXDATA;
3003 
input [1:0] TXDATAWIDTH;
3004 
input TXENC64B66BUSE;
3005 
input TXENC8B10BUSE;
3006 
input TXGEARBOX64B66BUSE;
3007 
input TXINHIBIT;
3008 
input [1:0] TXINTDATAWIDTH;
3009 
input TXPOLARITY;
3010 
input TXRESET;
3011 
input TXSCRAM64B66BUSE;
3012 
input TXUSRCLK;
3013 
input TXUSRCLK2;
3014 
endmodule
3015 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3016 
module GT10_INFINIBAND_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3017 
parameter integer ALIGN_COMMA_WORD = 2;
3018 
parameter integer CHAN_BOND_LIMIT = 16;
3019 
parameter CHAN_BOND_MODE = "OFF";
3020 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3021 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3022 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3023 
parameter integer CHAN_BOND_SEQ_LEN = 2;
3024 
parameter CLK_COR_8B10B_DE = "FALSE";
3025 
parameter integer CLK_COR_MAX_LAT = 36;
3026 
parameter integer CLK_COR_MIN_LAT = 28;
3027 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3028 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3029 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3030 
parameter CLK_COR_SEQ_DROP = "FALSE";
3031 
parameter integer CLK_COR_SEQ_LEN = 2;
3032 
parameter CLK_CORRECT_USE = "TRUE";
3033 
parameter DEC_MCOMMA_DETECT = "TRUE";
3034 
parameter DEC_PCOMMA_DETECT = "TRUE";
3035 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3036 
parameter LANE_ID = 11'b00000000000;
3037 
parameter PMA_PWR_CNTRL = 8'b11111111;
3038 
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f32663068090105a620;
3039 
parameter PMA_SPEED_USE = "PMA_SPEED";
3040 
parameter RX_BUFFER_USE = "TRUE";
3041 
parameter integer RX_LOS_INVALID_INCR = 1;
3042 
parameter integer RX_LOS_THRESHOLD = 4;
3043 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3044 
parameter TX_BUFFER_USE = "TRUE";
3045 
output CHBONDDONE;
3046 
output [4:0] CHBONDO;
3047 
output PMARXLOCK;
3048 
output [1:0] RXBUFSTATUS;
3049 
output [1:0] RXCHARISCOMMA;
3050 
output [1:0] RXCHARISK;
3051 
output [2:0] RXCLKCORCNT;
3052 
output RXCOMMADET;
3053 
output [15:0] RXDATA;
3054 
output [1:0] RXDISPERR;
3055 
output [1:0] RXLOSSOFSYNC;
3056 
output [1:0] RXNOTINTABLE;
3057 
output RXREALIGN;
3058 
output RXRECCLK;
3059 
output [1:0] RXRUNDISP;
3060 
output TXBUFERR;
3061 
output [1:0] TXKERR;
3062 
output TXN;
3063 
output TXOUTCLK;
3064 
output TXP;
3065 
output [1:0] TXRUNDISP;
3066 
input BREFCLKNIN;
3067 
input BREFCLKPIN;
3068 
input [4:0] CHBONDI;
3069 
input ENCHANSYNC;
3070 
input ENMCOMMAALIGN;
3071 
input ENPCOMMAALIGN;
3072 
input [1:0] LOOPBACK;
3073 
input PMAINIT;
3074 
input [5:0] PMAREGADDR;
3075 
input [7:0] PMAREGDATAIN;
3076 
input PMAREGRW;
3077 
input PMAREGSTROBE;
3078 
input [1:0] PMARXLOCKSEL;
3079 
input POWERDOWN;
3080 
input REFCLK;
3081 
input REFCLK2;
3082 
input REFCLKBSEL;
3083 
input REFCLKSEL;
3084 
input RXBLOCKSYNC64B66BUSE;
3085 
input RXCOMMADETUSE;
3086 
input [1:0] RXDATAWIDTH;
3087 
input RXDEC64B66BUSE;
3088 
input RXDEC8B10BUSE;
3089 
input RXDESCRAM64B66BUSE;
3090 
input RXIGNOREBTF;
3091 
input [1:0] RXINTDATAWIDTH;
3092 
input RXN;
3093 
input RXP;
3094 
input RXPOLARITY;
3095 
input RXRESET;
3096 
input RXSLIDE;
3097 
input RXUSRCLK;
3098 
input RXUSRCLK2;
3099 
input [1:0] TXBYPASS8B10B;
3100 
input [1:0] TXCHARDISPMODE;
3101 
input [1:0] TXCHARDISPVAL;
3102 
input [1:0] TXCHARISK;
3103 
input [15:0] TXDATA;
3104 
input [1:0] TXDATAWIDTH;
3105 
input TXENC64B66BUSE;
3106 
input TXENC8B10BUSE;
3107 
input TXGEARBOX64B66BUSE;
3108 
input TXINHIBIT;
3109 
input [1:0] TXINTDATAWIDTH;
3110 
input TXPOLARITY;
3111 
input TXRESET;
3112 
input TXSCRAM64B66BUSE;
3113 
input TXUSRCLK;
3114 
input TXUSRCLK2;
3115 
endmodule
3116 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3117 
module GT10_INFINIBAND_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3118 
parameter integer ALIGN_COMMA_WORD = 2;
3119 
parameter integer CHAN_BOND_LIMIT = 16;
3120 
parameter CHAN_BOND_MODE = "OFF";
3121 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3122 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3123 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3124 
parameter integer CHAN_BOND_SEQ_LEN = 2;
3125 
parameter CLK_COR_8B10B_DE = "FALSE";
3126 
parameter integer CLK_COR_MAX_LAT = 36;
3127 
parameter integer CLK_COR_MIN_LAT = 28;
3128 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3129 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3130 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3131 
parameter CLK_COR_SEQ_DROP = "FALSE";
3132 
parameter integer CLK_COR_SEQ_LEN = 2;
3133 
parameter CLK_CORRECT_USE = "TRUE";
3134 
parameter DEC_MCOMMA_DETECT = "TRUE";
3135 
parameter DEC_PCOMMA_DETECT = "TRUE";
3136 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3137 
parameter LANE_ID = 11'b00000000000;
3138 
parameter PMA_PWR_CNTRL = 8'b11111111;
3139 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a620;
3140 
parameter PMA_SPEED_USE = "PMA_SPEED";
3141 
parameter RX_BUFFER_USE = "TRUE";
3142 
parameter integer RX_LOS_INVALID_INCR = 1;
3143 
parameter integer RX_LOS_THRESHOLD = 4;
3144 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3145 
parameter TX_BUFFER_USE = "TRUE";
3146 
output CHBONDDONE;
3147 
output [4:0] CHBONDO;
3148 
output PMARXLOCK;
3149 
output [1:0] RXBUFSTATUS;
3150 
output [3:0] RXCHARISCOMMA;
3151 
output [3:0] RXCHARISK;
3152 
output [2:0] RXCLKCORCNT;
3153 
output RXCOMMADET;
3154 
output [31:0] RXDATA;
3155 
output [3:0] RXDISPERR;
3156 
output [1:0] RXLOSSOFSYNC;
3157 
output [3:0] RXNOTINTABLE;
3158 
output RXREALIGN;
3159 
output RXRECCLK;
3160 
output [3:0] RXRUNDISP;
3161 
output TXBUFERR;
3162 
output [3:0] TXKERR;
3163 
output TXN;
3164 
output TXOUTCLK;
3165 
output TXP;
3166 
output [3:0] TXRUNDISP;
3167 
input BREFCLKNIN;
3168 
input BREFCLKPIN;
3169 
input [4:0] CHBONDI;
3170 
input ENCHANSYNC;
3171 
input ENMCOMMAALIGN;
3172 
input ENPCOMMAALIGN;
3173 
input [1:0] LOOPBACK;
3174 
input PMAINIT;
3175 
input [5:0] PMAREGADDR;
3176 
input [7:0] PMAREGDATAIN;
3177 
input PMAREGRW;
3178 
input PMAREGSTROBE;
3179 
input [1:0] PMARXLOCKSEL;
3180 
input POWERDOWN;
3181 
input REFCLK;
3182 
input REFCLK2;
3183 
input REFCLKBSEL;
3184 
input REFCLKSEL;
3185 
input RXBLOCKSYNC64B66BUSE;
3186 
input RXCOMMADETUSE;
3187 
input [1:0] RXDATAWIDTH;
3188 
input RXDEC64B66BUSE;
3189 
input RXDEC8B10BUSE;
3190 
input RXDESCRAM64B66BUSE;
3191 
input RXIGNOREBTF;
3192 
input [1:0] RXINTDATAWIDTH;
3193 
input RXN;
3194 
input RXP;
3195 
input RXPOLARITY;
3196 
input RXRESET;
3197 
input RXSLIDE;
3198 
input RXUSRCLK;
3199 
input RXUSRCLK2;
3200 
input [3:0] TXBYPASS8B10B;
3201 
input [3:0] TXCHARDISPMODE;
3202 
input [3:0] TXCHARDISPVAL;
3203 
input [3:0] TXCHARISK;
3204 
input [31:0] TXDATA;
3205 
input [1:0] TXDATAWIDTH;
3206 
input TXENC64B66BUSE;
3207 
input TXENC8B10BUSE;
3208 
input TXGEARBOX64B66BUSE;
3209 
input TXINHIBIT;
3210 
input [1:0] TXINTDATAWIDTH;
3211 
input TXPOLARITY;
3212 
input TXRESET;
3213 
input TXSCRAM64B66BUSE;
3214 
input TXUSRCLK;
3215 
input TXUSRCLK2;
3216 
endmodule
3217 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3218 
module GT10_OC192_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLKBSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3219 
parameter integer ALIGN_COMMA_WORD = 1;
3220 
parameter DEC_MCOMMA_DETECT = "TRUE";
3221 
parameter DEC_PCOMMA_DETECT = "TRUE";
3222 
parameter MCOMMA_10B_VALUE = 10'b0010101010;
3223 
parameter MCOMMA_DETECT = "TRUE";
3224 
parameter PCOMMA_10B_VALUE = 10'b0010101010;
3225 
parameter PCOMMA_DETECT = "TRUE";
3226 
parameter PMA_PWR_CNTRL = 8'b11111111;
3227 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504c00208c9050d0068;
3228 
parameter PMA_SPEED_USE = "PMA_SPEED";
3229 
parameter RX_BUFFER_USE = "TRUE";
3230 
parameter integer RX_LOS_INVALID_INCR = 1;
3231 
parameter integer RX_LOS_THRESHOLD = 4;
3232 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3233 
parameter TX_BUFFER_USE = "TRUE";
3234 
output CHBONDDONE;
3235 
output [4:0] CHBONDO;
3236 
output PMARXLOCK;
3237 
output [1:0] RXBUFSTATUS;
3238 
output [3:0] RXCHARISCOMMA;
3239 
output [3:0] RXCHARISK;
3240 
output [2:0] RXCLKCORCNT;
3241 
output RXCOMMADET;
3242 
output [31:0] RXDATA;
3243 
output [3:0] RXDISPERR;
3244 
output [1:0] RXLOSSOFSYNC;
3245 
output [3:0] RXNOTINTABLE;
3246 
output RXREALIGN;
3247 
output RXRECCLK;
3248 
output [3:0] RXRUNDISP;
3249 
output TXBUFERR;
3250 
output [3:0] TXKERR;
3251 
output TXN;
3252 
output TXOUTCLK;
3253 
output TXP;
3254 
output [3:0] TXRUNDISP;
3255 
input BREFCLKNIN;
3256 
input BREFCLKPIN;
3257 
input [4:0] CHBONDI;
3258 
input ENCHANSYNC;
3259 
input ENMCOMMAALIGN;
3260 
input ENPCOMMAALIGN;
3261 
input [1:0] LOOPBACK;
3262 
input PMAINIT;
3263 
input [5:0] PMAREGADDR;
3264 
input [7:0] PMAREGDATAIN;
3265 
input PMAREGRW;
3266 
input PMAREGSTROBE;
3267 
input [1:0] PMARXLOCKSEL;
3268 
input POWERDOWN;
3269 
input REFCLKBSEL;
3270 
input RXBLOCKSYNC64B66BUSE;
3271 
input RXCOMMADETUSE;
3272 
input [1:0] RXDATAWIDTH;
3273 
input RXDEC64B66BUSE;
3274 
input RXDEC8B10BUSE;
3275 
input RXDESCRAM64B66BUSE;
3276 
input RXIGNOREBTF;
3277 
input [1:0] RXINTDATAWIDTH;
3278 
input RXN;
3279 
input RXP;
3280 
input RXPOLARITY;
3281 
input RXRESET;
3282 
input RXSLIDE;
3283 
input RXUSRCLK;
3284 
input RXUSRCLK2;
3285 
input [3:0] TXBYPASS8B10B;
3286 
input [3:0] TXCHARDISPMODE;
3287 
input [3:0] TXCHARDISPVAL;
3288 
input [3:0] TXCHARISK;
3289 
input [31:0] TXDATA;
3290 
input [1:0] TXDATAWIDTH;
3291 
input TXENC64B66BUSE;
3292 
input TXENC8B10BUSE;
3293 
input TXGEARBOX64B66BUSE;
3294 
input TXINHIBIT;
3295 
input [1:0] TXINTDATAWIDTH;
3296 
input TXPOLARITY;
3297 
input TXRESET;
3298 
input TXSCRAM64B66BUSE;
3299 
input TXUSRCLK;
3300 
input TXUSRCLK2;
3301 
endmodule
3302 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3303 
module GT10_OC192_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLKBSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3304 
parameter integer ALIGN_COMMA_WORD = 1;
3305 
parameter DEC_MCOMMA_DETECT = "TRUE";
3306 
parameter DEC_PCOMMA_DETECT = "TRUE";
3307 
parameter MCOMMA_10B_VALUE = 10'b0010101010;
3308 
parameter MCOMMA_DETECT = "TRUE";
3309 
parameter PCOMMA_10B_VALUE = 10'b0010101010;
3310 
parameter PCOMMA_DETECT = "TRUE";
3311 
parameter PMA_PWR_CNTRL = 8'b11111111;
3312 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504c00208c9050d0068;
3313 
parameter PMA_SPEED_USE = "PMA_SPEED";
3314 
parameter RX_BUFFER_USE = "TRUE";
3315 
parameter integer RX_LOS_INVALID_INCR = 1;
3316 
parameter integer RX_LOS_THRESHOLD = 4;
3317 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3318 
parameter TX_BUFFER_USE = "TRUE";
3319 
output CHBONDDONE;
3320 
output [4:0] CHBONDO;
3321 
output PMARXLOCK;
3322 
output [1:0] RXBUFSTATUS;
3323 
output [7:0] RXCHARISCOMMA;
3324 
output [7:0] RXCHARISK;
3325 
output [2:0] RXCLKCORCNT;
3326 
output RXCOMMADET;
3327 
output [63:0] RXDATA;
3328 
output [7:0] RXDISPERR;
3329 
output [1:0] RXLOSSOFSYNC;
3330 
output [7:0] RXNOTINTABLE;
3331 
output RXREALIGN;
3332 
output RXRECCLK;
3333 
output [7:0] RXRUNDISP;
3334 
output TXBUFERR;
3335 
output [7:0] TXKERR;
3336 
output TXN;
3337 
output TXOUTCLK;
3338 
output TXP;
3339 
output [7:0] TXRUNDISP;
3340 
input BREFCLKNIN;
3341 
input BREFCLKPIN;
3342 
input [4:0] CHBONDI;
3343 
input ENCHANSYNC;
3344 
input ENMCOMMAALIGN;
3345 
input ENPCOMMAALIGN;
3346 
input [1:0] LOOPBACK;
3347 
input PMAINIT;
3348 
input [5:0] PMAREGADDR;
3349 
input [7:0] PMAREGDATAIN;
3350 
input PMAREGRW;
3351 
input PMAREGSTROBE;
3352 
input [1:0] PMARXLOCKSEL;
3353 
input POWERDOWN;
3354 
input REFCLKBSEL;
3355 
input RXBLOCKSYNC64B66BUSE;
3356 
input RXCOMMADETUSE;
3357 
input [1:0] RXDATAWIDTH;
3358 
input RXDEC64B66BUSE;
3359 
input RXDEC8B10BUSE;
3360 
input RXDESCRAM64B66BUSE;
3361 
input RXIGNOREBTF;
3362 
input [1:0] RXINTDATAWIDTH;
3363 
input RXN;
3364 
input RXP;
3365 
input RXPOLARITY;
3366 
input RXRESET;
3367 
input RXSLIDE;
3368 
input RXUSRCLK;
3369 
input RXUSRCLK2;
3370 
input [7:0] TXBYPASS8B10B;
3371 
input [7:0] TXCHARDISPMODE;
3372 
input [7:0] TXCHARDISPVAL;
3373 
input [7:0] TXCHARISK;
3374 
input [63:0] TXDATA;
3375 
input [1:0] TXDATAWIDTH;
3376 
input TXENC64B66BUSE;
3377 
input TXENC8B10BUSE;
3378 
input TXGEARBOX64B66BUSE;
3379 
input TXINHIBIT;
3380 
input [1:0] TXINTDATAWIDTH;
3381 
input TXPOLARITY;
3382 
input TXRESET;
3383 
input TXSCRAM64B66BUSE;
3384 
input TXUSRCLK;
3385 
input TXUSRCLK2;
3386 
endmodule
3387 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3388 
module GT10_OC48_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3389 
parameter integer ALIGN_COMMA_WORD = 1;
3390 
parameter DEC_MCOMMA_DETECT = "TRUE";
3391 
parameter DEC_PCOMMA_DETECT = "TRUE";
3392 
parameter MCOMMA_10B_VALUE = 10'b0010101010;
3393 
parameter MCOMMA_DETECT = "TRUE";
3394 
parameter PCOMMA_10B_VALUE = 10'b0010101010;
3395 
parameter PCOMMA_DETECT = "TRUE";
3396 
parameter PMA_PWR_CNTRL = 8'b11111111;
3397 
parameter PMA_SPEED_HEX = 120'h00ffcd500b01300830680901040820;
3398 
parameter PMA_SPEED_USE = "PMA_SPEED";
3399 
parameter RX_BUFFER_USE = "TRUE";
3400 
parameter integer RX_LOS_INVALID_INCR = 1;
3401 
parameter integer RX_LOS_THRESHOLD = 4;
3402 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3403 
parameter TX_BUFFER_USE = "TRUE";
3404 
output CHBONDDONE;
3405 
output [4:0] CHBONDO;
3406 
output PMARXLOCK;
3407 
output [1:0] RXBUFSTATUS;
3408 
output [0:0] RXCHARISCOMMA;
3409 
output [0:0] RXCHARISK;
3410 
output [2:0] RXCLKCORCNT;
3411 
output RXCOMMADET;
3412 
output [7:0] RXDATA;
3413 
output [0:0] RXDISPERR;
3414 
output [1:0] RXLOSSOFSYNC;
3415 
output [0:0] RXNOTINTABLE;
3416 
output RXREALIGN;
3417 
output RXRECCLK;
3418 
output [0:0] RXRUNDISP;
3419 
output TXBUFERR;
3420 
output [0:0] TXKERR;
3421 
output TXN;
3422 
output TXOUTCLK;
3423 
output TXP;
3424 
output [0:0] TXRUNDISP;
3425 
input BREFCLKNIN;
3426 
input BREFCLKPIN;
3427 
input [4:0] CHBONDI;
3428 
input ENCHANSYNC;
3429 
input ENMCOMMAALIGN;
3430 
input ENPCOMMAALIGN;
3431 
input [1:0] LOOPBACK;
3432 
input PMAINIT;
3433 
input [5:0] PMAREGADDR;
3434 
input [7:0] PMAREGDATAIN;
3435 
input PMAREGRW;
3436 
input PMAREGSTROBE;
3437 
input [1:0] PMARXLOCKSEL;
3438 
input POWERDOWN;
3439 
input REFCLK;
3440 
input REFCLK2;
3441 
input REFCLKBSEL;
3442 
input REFCLKSEL;
3443 
input RXBLOCKSYNC64B66BUSE;
3444 
input RXCOMMADETUSE;
3445 
input [1:0] RXDATAWIDTH;
3446 
input RXDEC64B66BUSE;
3447 
input RXDEC8B10BUSE;
3448 
input RXDESCRAM64B66BUSE;
3449 
input RXIGNOREBTF;
3450 
input [1:0] RXINTDATAWIDTH;
3451 
input RXN;
3452 
input RXP;
3453 
input RXPOLARITY;
3454 
input RXRESET;
3455 
input RXSLIDE;
3456 
input RXUSRCLK;
3457 
input RXUSRCLK2;
3458 
input [0:0] TXBYPASS8B10B;
3459 
input [0:0] TXCHARDISPMODE;
3460 
input [0:0] TXCHARDISPVAL;
3461 
input [0:0] TXCHARISK;
3462 
input [7:0] TXDATA;
3463 
input [1:0] TXDATAWIDTH;
3464 
input TXENC64B66BUSE;
3465 
input TXENC8B10BUSE;
3466 
input TXGEARBOX64B66BUSE;
3467 
input TXINHIBIT;
3468 
input [1:0] TXINTDATAWIDTH;
3469 
input TXPOLARITY;
3470 
input TXRESET;
3471 
input TXSCRAM64B66BUSE;
3472 
input TXUSRCLK;
3473 
input TXUSRCLK2;
3474 
endmodule
3475 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3476 
module GT10_OC48_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3477 
parameter integer ALIGN_COMMA_WORD = 1;
3478 
parameter DEC_MCOMMA_DETECT = "TRUE";
3479 
parameter DEC_PCOMMA_DETECT = "TRUE";
3480 
parameter MCOMMA_10B_VALUE = 10'b0010101010;
3481 
parameter MCOMMA_DETECT = "TRUE";
3482 
parameter PCOMMA_10B_VALUE = 10'b0010101010;
3483 
parameter PCOMMA_DETECT = "TRUE";
3484 
parameter PMA_PWR_CNTRL = 8'b11111111;
3485 
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f304830680901050820;
3486 
parameter PMA_SPEED_USE = "PMA_SPEED";
3487 
parameter RX_BUFFER_USE = "TRUE";
3488 
parameter integer RX_LOS_INVALID_INCR = 1;
3489 
parameter integer RX_LOS_THRESHOLD = 4;
3490 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3491 
parameter TX_BUFFER_USE = "TRUE";
3492 
output CHBONDDONE;
3493 
output [4:0] CHBONDO;
3494 
output PMARXLOCK;
3495 
output [1:0] RXBUFSTATUS;
3496 
output [1:0] RXCHARISCOMMA;
3497 
output [1:0] RXCHARISK;
3498 
output [2:0] RXCLKCORCNT;
3499 
output RXCOMMADET;
3500 
output [15:0] RXDATA;
3501 
output [1:0] RXDISPERR;
3502 
output [1:0] RXLOSSOFSYNC;
3503 
output [1:0] RXNOTINTABLE;
3504 
output RXREALIGN;
3505 
output RXRECCLK;
3506 
output [1:0] RXRUNDISP;
3507 
output TXBUFERR;
3508 
output [1:0] TXKERR;
3509 
output TXN;
3510 
output TXOUTCLK;
3511 
output TXP;
3512 
output [1:0] TXRUNDISP;
3513 
input BREFCLKNIN;
3514 
input BREFCLKPIN;
3515 
input [4:0] CHBONDI;
3516 
input ENCHANSYNC;
3517 
input ENMCOMMAALIGN;
3518 
input ENPCOMMAALIGN;
3519 
input [1:0] LOOPBACK;
3520 
input PMAINIT;
3521 
input [5:0] PMAREGADDR;
3522 
input [7:0] PMAREGDATAIN;
3523 
input PMAREGRW;
3524 
input PMAREGSTROBE;
3525 
input [1:0] PMARXLOCKSEL;
3526 
input POWERDOWN;
3527 
input REFCLK;
3528 
input REFCLK2;
3529 
input REFCLKBSEL;
3530 
input REFCLKSEL;
3531 
input RXBLOCKSYNC64B66BUSE;
3532 
input RXCOMMADETUSE;
3533 
input [1:0] RXDATAWIDTH;
3534 
input RXDEC64B66BUSE;
3535 
input RXDEC8B10BUSE;
3536 
input RXDESCRAM64B66BUSE;
3537 
input RXIGNOREBTF;
3538 
input [1:0] RXINTDATAWIDTH;
3539 
input RXN;
3540 
input RXP;
3541 
input RXPOLARITY;
3542 
input RXRESET;
3543 
input RXSLIDE;
3544 
input RXUSRCLK;
3545 
input RXUSRCLK2;
3546 
input [1:0] TXBYPASS8B10B;
3547 
input [1:0] TXCHARDISPMODE;
3548 
input [1:0] TXCHARDISPVAL;
3549 
input [1:0] TXCHARISK;
3550 
input [15:0] TXDATA;
3551 
input [1:0] TXDATAWIDTH;
3552 
input TXENC64B66BUSE;
3553 
input TXENC8B10BUSE;
3554 
input TXGEARBOX64B66BUSE;
3555 
input TXINHIBIT;
3556 
input [1:0] TXINTDATAWIDTH;
3557 
input TXPOLARITY;
3558 
input TXRESET;
3559 
input TXSCRAM64B66BUSE;
3560 
input TXUSRCLK;
3561 
input TXUSRCLK2;
3562 
endmodule
3563 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3564 
module GT10_OC48_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3565 
parameter integer ALIGN_COMMA_WORD = 1;
3566 
parameter DEC_MCOMMA_DETECT = "TRUE";
3567 
parameter DEC_PCOMMA_DETECT = "TRUE";
3568 
parameter MCOMMA_10B_VALUE = 10'b0010101010;
3569 
parameter MCOMMA_DETECT = "TRUE";
3570 
parameter PCOMMA_10B_VALUE = 10'b0010101010;
3571 
parameter PCOMMA_DETECT = "TRUE";
3572 
parameter PMA_PWR_CNTRL = 8'b11111111;
3573 
parameter PMA_SPEED_HEX = 120'h00ffcd500b01304830680901050820;
3574 
parameter PMA_SPEED_USE = "PMA_SPEED";
3575 
parameter RX_BUFFER_USE = "TRUE";
3576 
parameter integer RX_LOS_INVALID_INCR = 1;
3577 
parameter integer RX_LOS_THRESHOLD = 4;
3578 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3579 
parameter TX_BUFFER_USE = "TRUE";
3580 
output CHBONDDONE;
3581 
output [4:0] CHBONDO;
3582 
output PMARXLOCK;
3583 
output [1:0] RXBUFSTATUS;
3584 
output [3:0] RXCHARISCOMMA;
3585 
output [3:0] RXCHARISK;
3586 
output [2:0] RXCLKCORCNT;
3587 
output RXCOMMADET;
3588 
output [31:0] RXDATA;
3589 
output [3:0] RXDISPERR;
3590 
output [1:0] RXLOSSOFSYNC;
3591 
output [3:0] RXNOTINTABLE;
3592 
output RXREALIGN;
3593 
output RXRECCLK;
3594 
output [3:0] RXRUNDISP;
3595 
output TXBUFERR;
3596 
output [3:0] TXKERR;
3597 
output TXN;
3598 
output TXOUTCLK;
3599 
output TXP;
3600 
output [3:0] TXRUNDISP;
3601 
input BREFCLKNIN;
3602 
input BREFCLKPIN;
3603 
input [4:0] CHBONDI;
3604 
input ENCHANSYNC;
3605 
input ENMCOMMAALIGN;
3606 
input ENPCOMMAALIGN;
3607 
input [1:0] LOOPBACK;
3608 
input PMAINIT;
3609 
input [5:0] PMAREGADDR;
3610 
input [7:0] PMAREGDATAIN;
3611 
input PMAREGRW;
3612 
input PMAREGSTROBE;
3613 
input [1:0] PMARXLOCKSEL;
3614 
input POWERDOWN;
3615 
input REFCLK;
3616 
input REFCLK2;
3617 
input REFCLKBSEL;
3618 
input REFCLKSEL;
3619 
input RXBLOCKSYNC64B66BUSE;
3620 
input RXCOMMADETUSE;
3621 
input [1:0] RXDATAWIDTH;
3622 
input RXDEC64B66BUSE;
3623 
input RXDEC8B10BUSE;
3624 
input RXDESCRAM64B66BUSE;
3625 
input RXIGNOREBTF;
3626 
input [1:0] RXINTDATAWIDTH;
3627 
input RXN;
3628 
input RXP;
3629 
input RXPOLARITY;
3630 
input RXRESET;
3631 
input RXSLIDE;
3632 
input RXUSRCLK;
3633 
input RXUSRCLK2;
3634 
input [3:0] TXBYPASS8B10B;
3635 
input [3:0] TXCHARDISPMODE;
3636 
input [3:0] TXCHARDISPVAL;
3637 
input [3:0] TXCHARISK;
3638 
input [31:0] TXDATA;
3639 
input [1:0] TXDATAWIDTH;
3640 
input TXENC64B66BUSE;
3641 
input TXENC8B10BUSE;
3642 
input TXGEARBOX64B66BUSE;
3643 
input TXINHIBIT;
3644 
input [1:0] TXINTDATAWIDTH;
3645 
input TXPOLARITY;
3646 
input TXRESET;
3647 
input TXSCRAM64B66BUSE;
3648 
input TXUSRCLK;
3649 
input TXUSRCLK2;
3650 
endmodule
3651 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3652 
module GT10_PCI_EXPRESS_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3653 
parameter integer ALIGN_COMMA_WORD = 2;
3654 
parameter integer CHAN_BOND_LIMIT = 16;
3655 
parameter CHAN_BOND_MODE = "OFF";
3656 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3657 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3658 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3659 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
3660 
parameter integer CHAN_BOND_SEQ_LEN = 2;
3661 
parameter CLK_COR_8B10B_DE = "FALSE";
3662 
parameter integer CLK_COR_MAX_LAT = 36;
3663 
parameter integer CLK_COR_MIN_LAT = 28;
3664 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3665 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3666 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3667 
parameter CLK_COR_SEQ_DROP = "FALSE";
3668 
parameter integer CLK_COR_SEQ_LEN = 2;
3669 
parameter CLK_CORRECT_USE = "TRUE";
3670 
parameter DEC_MCOMMA_DETECT = "TRUE";
3671 
parameter DEC_PCOMMA_DETECT = "TRUE";
3672 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3673 
parameter PMA_PWR_CNTRL = 8'b11111111;
3674 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132263068090104a620;
3675 
parameter PMA_SPEED_USE = "PMA_SPEED";
3676 
parameter RX_BUFFER_USE = "TRUE";
3677 
parameter integer RX_LOS_INVALID_INCR = 1;
3678 
parameter integer RX_LOS_THRESHOLD = 4;
3679 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3680 
parameter TX_BUFFER_USE = "TRUE";
3681 
output CHBONDDONE;
3682 
output [4:0] CHBONDO;
3683 
output PMARXLOCK;
3684 
output [1:0] RXBUFSTATUS;
3685 
output [0:0] RXCHARISCOMMA;
3686 
output [0:0] RXCHARISK;
3687 
output [2:0] RXCLKCORCNT;
3688 
output RXCOMMADET;
3689 
output [7:0] RXDATA;
3690 
output [0:0] RXDISPERR;
3691 
output [1:0] RXLOSSOFSYNC;
3692 
output [0:0] RXNOTINTABLE;
3693 
output RXREALIGN;
3694 
output RXRECCLK;
3695 
output [0:0] RXRUNDISP;
3696 
output TXBUFERR;
3697 
output [0:0] TXKERR;
3698 
output TXN;
3699 
output TXOUTCLK;
3700 
output TXP;
3701 
output [0:0] TXRUNDISP;
3702 
input BREFCLKNIN;
3703 
input BREFCLKPIN;
3704 
input [4:0] CHBONDI;
3705 
input ENCHANSYNC;
3706 
input ENMCOMMAALIGN;
3707 
input ENPCOMMAALIGN;
3708 
input [1:0] LOOPBACK;
3709 
input PMAINIT;
3710 
input [5:0] PMAREGADDR;
3711 
input [7:0] PMAREGDATAIN;
3712 
input PMAREGRW;
3713 
input PMAREGSTROBE;
3714 
input [1:0] PMARXLOCKSEL;
3715 
input POWERDOWN;
3716 
input REFCLK;
3717 
input REFCLK2;
3718 
input REFCLKBSEL;
3719 
input REFCLKSEL;
3720 
input RXBLOCKSYNC64B66BUSE;
3721 
input RXCOMMADETUSE;
3722 
input [1:0] RXDATAWIDTH;
3723 
input RXDEC64B66BUSE;
3724 
input RXDEC8B10BUSE;
3725 
input RXDESCRAM64B66BUSE;
3726 
input RXIGNOREBTF;
3727 
input [1:0] RXINTDATAWIDTH;
3728 
input RXN;
3729 
input RXP;
3730 
input RXPOLARITY;
3731 
input RXRESET;
3732 
input RXSLIDE;
3733 
input RXUSRCLK;
3734 
input RXUSRCLK2;
3735 
input [0:0] TXBYPASS8B10B;
3736 
input [0:0] TXCHARDISPMODE;
3737 
input [0:0] TXCHARDISPVAL;
3738 
input [0:0] TXCHARISK;
3739 
input [7:0] TXDATA;
3740 
input [1:0] TXDATAWIDTH;
3741 
input TXENC64B66BUSE;
3742 
input TXENC8B10BUSE;
3743 
input TXGEARBOX64B66BUSE;
3744 
input TXINHIBIT;
3745 
input [1:0] TXINTDATAWIDTH;
3746 
input TXPOLARITY;
3747 
input TXRESET;
3748 
input TXSCRAM64B66BUSE;
3749 
input TXUSRCLK;
3750 
input TXUSRCLK2;
3751 
endmodule
3752 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3753 
module GT10_PCI_EXPRESS_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3754 
parameter integer ALIGN_COMMA_WORD = 2;
3755 
parameter integer CHAN_BOND_LIMIT = 16;
3756 
parameter CHAN_BOND_MODE = "OFF";
3757 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3758 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3759 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3760 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
3761 
parameter integer CHAN_BOND_SEQ_LEN = 2;
3762 
parameter CLK_COR_8B10B_DE = "FALSE";
3763 
parameter integer CLK_COR_MAX_LAT = 36;
3764 
parameter integer CLK_COR_MIN_LAT = 28;
3765 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3766 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3767 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3768 
parameter CLK_COR_SEQ_DROP = "FALSE";
3769 
parameter integer CLK_COR_SEQ_LEN = 2;
3770 
parameter CLK_CORRECT_USE = "TRUE";
3771 
parameter DEC_MCOMMA_DETECT = "TRUE";
3772 
parameter DEC_PCOMMA_DETECT = "TRUE";
3773 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3774 
parameter PMA_PWR_CNTRL = 8'b11111111;
3775 
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f32663068090105a620;
3776 
parameter PMA_SPEED_USE = "PMA_SPEED";
3777 
parameter RX_BUFFER_USE = "TRUE";
3778 
parameter integer RX_LOS_INVALID_INCR = 1;
3779 
parameter integer RX_LOS_THRESHOLD = 4;
3780 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3781 
parameter TX_BUFFER_USE = "TRUE";
3782 
output CHBONDDONE;
3783 
output [4:0] CHBONDO;
3784 
output PMARXLOCK;
3785 
output [1:0] RXBUFSTATUS;
3786 
output [1:0] RXCHARISCOMMA;
3787 
output [1:0] RXCHARISK;
3788 
output [2:0] RXCLKCORCNT;
3789 
output RXCOMMADET;
3790 
output [15:0] RXDATA;
3791 
output [1:0] RXDISPERR;
3792 
output [1:0] RXLOSSOFSYNC;
3793 
output [1:0] RXNOTINTABLE;
3794 
output RXREALIGN;
3795 
output RXRECCLK;
3796 
output [1:0] RXRUNDISP;
3797 
output TXBUFERR;
3798 
output [1:0] TXKERR;
3799 
output TXN;
3800 
output TXOUTCLK;
3801 
output TXP;
3802 
output [1:0] TXRUNDISP;
3803 
input BREFCLKNIN;
3804 
input BREFCLKPIN;
3805 
input [4:0] CHBONDI;
3806 
input ENCHANSYNC;
3807 
input ENMCOMMAALIGN;
3808 
input ENPCOMMAALIGN;
3809 
input [1:0] LOOPBACK;
3810 
input PMAINIT;
3811 
input [5:0] PMAREGADDR;
3812 
input [7:0] PMAREGDATAIN;
3813 
input PMAREGRW;
3814 
input PMAREGSTROBE;
3815 
input [1:0] PMARXLOCKSEL;
3816 
input POWERDOWN;
3817 
input REFCLK;
3818 
input REFCLK2;
3819 
input REFCLKBSEL;
3820 
input REFCLKSEL;
3821 
input RXBLOCKSYNC64B66BUSE;
3822 
input RXCOMMADETUSE;
3823 
input [1:0] RXDATAWIDTH;
3824 
input RXDEC64B66BUSE;
3825 
input RXDEC8B10BUSE;
3826 
input RXDESCRAM64B66BUSE;
3827 
input RXIGNOREBTF;
3828 
input [1:0] RXINTDATAWIDTH;
3829 
input RXN;
3830 
input RXP;
3831 
input RXPOLARITY;
3832 
input RXRESET;
3833 
input RXSLIDE;
3834 
input RXUSRCLK;
3835 
input RXUSRCLK2;
3836 
input [1:0] TXBYPASS8B10B;
3837 
input [1:0] TXCHARDISPMODE;
3838 
input [1:0] TXCHARDISPVAL;
3839 
input [1:0] TXCHARISK;
3840 
input [15:0] TXDATA;
3841 
input [1:0] TXDATAWIDTH;
3842 
input TXENC64B66BUSE;
3843 
input TXENC8B10BUSE;
3844 
input TXGEARBOX64B66BUSE;
3845 
input TXINHIBIT;
3846 
input [1:0] TXINTDATAWIDTH;
3847 
input TXPOLARITY;
3848 
input TXRESET;
3849 
input TXSCRAM64B66BUSE;
3850 
input TXUSRCLK;
3851 
input TXUSRCLK2;
3852 
endmodule
3853 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3854 
module GT10_PCI_EXPRESS_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3855 
parameter integer ALIGN_COMMA_WORD = 2;
3856 
parameter integer CHAN_BOND_LIMIT = 16;
3857 
parameter CHAN_BOND_MODE = "OFF";
3858 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3859 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3860 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3861 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
3862 
parameter integer CHAN_BOND_SEQ_LEN = 2;
3863 
parameter CLK_COR_8B10B_DE = "FALSE";
3864 
parameter integer CLK_COR_MAX_LAT = 36;
3865 
parameter integer CLK_COR_MIN_LAT = 28;
3866 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3867 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3868 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3869 
parameter CLK_COR_SEQ_DROP = "FALSE";
3870 
parameter integer CLK_COR_SEQ_LEN = 2;
3871 
parameter CLK_CORRECT_USE = "TRUE";
3872 
parameter DEC_MCOMMA_DETECT = "TRUE";
3873 
parameter DEC_PCOMMA_DETECT = "TRUE";
3874 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3875 
parameter PMA_PWR_CNTRL = 8'b11111111;
3876 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a620;
3877 
parameter PMA_SPEED_USE = "PMA_SPEED";
3878 
parameter RX_BUFFER_USE = "TRUE";
3879 
parameter integer RX_LOS_INVALID_INCR = 1;
3880 
parameter integer RX_LOS_THRESHOLD = 4;
3881 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
3882 
parameter TX_BUFFER_USE = "TRUE";
3883 
output CHBONDDONE;
3884 
output [4:0] CHBONDO;
3885 
output PMARXLOCK;
3886 
output [1:0] RXBUFSTATUS;
3887 
output [3:0] RXCHARISCOMMA;
3888 
output [3:0] RXCHARISK;
3889 
output [2:0] RXCLKCORCNT;
3890 
output RXCOMMADET;
3891 
output [31:0] RXDATA;
3892 
output [3:0] RXDISPERR;
3893 
output [1:0] RXLOSSOFSYNC;
3894 
output [3:0] RXNOTINTABLE;
3895 
output RXREALIGN;
3896 
output RXRECCLK;
3897 
output [3:0] RXRUNDISP;
3898 
output TXBUFERR;
3899 
output [3:0] TXKERR;
3900 
output TXN;
3901 
output TXOUTCLK;
3902 
output TXP;
3903 
output [3:0] TXRUNDISP;
3904 
input BREFCLKNIN;
3905 
input BREFCLKPIN;
3906 
input [4:0] CHBONDI;
3907 
input ENCHANSYNC;
3908 
input ENMCOMMAALIGN;
3909 
input ENPCOMMAALIGN;
3910 
input [1:0] LOOPBACK;
3911 
input PMAINIT;
3912 
input [5:0] PMAREGADDR;
3913 
input [7:0] PMAREGDATAIN;
3914 
input PMAREGRW;
3915 
input PMAREGSTROBE;
3916 
input [1:0] PMARXLOCKSEL;
3917 
input POWERDOWN;
3918 
input REFCLK;
3919 
input REFCLK2;
3920 
input REFCLKBSEL;
3921 
input REFCLKSEL;
3922 
input RXBLOCKSYNC64B66BUSE;
3923 
input RXCOMMADETUSE;
3924 
input [1:0] RXDATAWIDTH;
3925 
input RXDEC64B66BUSE;
3926 
input RXDEC8B10BUSE;
3927 
input RXDESCRAM64B66BUSE;
3928 
input RXIGNOREBTF;
3929 
input [1:0] RXINTDATAWIDTH;
3930 
input RXN;
3931 
input RXP;
3932 
input RXPOLARITY;
3933 
input RXRESET;
3934 
input RXSLIDE;
3935 
input RXUSRCLK;
3936 
input RXUSRCLK2;
3937 
input [3:0] TXBYPASS8B10B;
3938 
input [3:0] TXCHARDISPMODE;
3939 
input [3:0] TXCHARDISPVAL;
3940 
input [3:0] TXCHARISK;
3941 
input [31:0] TXDATA;
3942 
input [1:0] TXDATAWIDTH;
3943 
input TXENC64B66BUSE;
3944 
input TXENC8B10BUSE;
3945 
input TXGEARBOX64B66BUSE;
3946 
input TXINHIBIT;
3947 
input [1:0] TXINTDATAWIDTH;
3948 
input TXPOLARITY;
3949 
input TXRESET;
3950 
input TXSCRAM64B66BUSE;
3951 
input TXUSRCLK;
3952 
input TXUSRCLK2;
3953 
endmodule
3954 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
3955 
module GT10 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
3956 
parameter integer ALIGN_COMMA_WORD = 1;
3957 
parameter integer CHAN_BOND_LIMIT = 16;
3958 
parameter CHAN_BOND_MODE = "OFF";
3959 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
3960 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
3961 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
3962 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
3963 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
3964 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
3965 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
3966 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
3967 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
3968 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
3969 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
3970 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
3971 
parameter integer CHAN_BOND_SEQ_LEN = 1;
3972 
parameter CHAN_BOND_64B66B_SV = "FALSE";
3973 
parameter CLK_COR_8B10B_DE = "FALSE";
3974 
parameter integer CLK_COR_MAX_LAT = 36;
3975 
parameter integer CLK_COR_MIN_LAT = 28;
3976 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
3977 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
3978 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
3979 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
3980 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
3981 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
3982 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
3983 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
3984 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
3985 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
3986 
parameter CLK_COR_SEQ_2_USE = "FALSE";
3987 
parameter CLK_COR_SEQ_DROP = "FALSE";
3988 
parameter integer CLK_COR_SEQ_LEN = 1;
3989 
parameter CLK_CORRECT_USE = "TRUE";
3990 
parameter COMMA_10B_MASK = 10'b0001111111;
3991 
parameter DEC_MCOMMA_DETECT = "TRUE";
3992 
parameter DEC_PCOMMA_DETECT = "TRUE";
3993 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
3994 
parameter MCOMMA_10B_VALUE = 10'b1010000011;
3995 
parameter MCOMMA_DETECT = "TRUE";
3996 
parameter PCOMMA_10B_VALUE = 10'b0101111100;
3997 
parameter PCOMMA_DETECT = "TRUE";
3998 
parameter PMA_PWR_CNTRL = 8'b11111111;
3999 
parameter PMA_SPEED = "0_32";
4000 
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
4001 
parameter PMA_SPEED_USE = "PMA_SPEED";
4002 
parameter RX_BUFFER_USE = "TRUE";
4003 
parameter integer RX_LOS_INVALID_INCR = 1;
4004 
parameter integer RX_LOS_THRESHOLD = 4;
4005 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
4006 
parameter integer SH_CNT_MAX = 64;
4007 
parameter integer SH_INVALID_CNT_MAX = 16;
4008 
parameter TX_BUFFER_USE = "TRUE";
4009 
output CHBONDDONE;
4010 
output [4:0] CHBONDO;
4011 
output PMARXLOCK;
4012 
output [1:0] RXBUFSTATUS;
4013 
output [7:0] RXCHARISCOMMA;
4014 
output [7:0] RXCHARISK;
4015 
output [2:0] RXCLKCORCNT;
4016 
output RXCOMMADET;
4017 
output [63:0] RXDATA;
4018 
output [7:0] RXDISPERR;
4019 
output [1:0] RXLOSSOFSYNC;
4020 
output [7:0] RXNOTINTABLE;
4021 
output RXREALIGN;
4022 
output RXRECCLK;
4023 
output [7:0] RXRUNDISP;
4024 
output TXBUFERR;
4025 
output [7:0] TXKERR;
4026 
output TXN;
4027 
output TXOUTCLK;
4028 
output TXP;
4029 
output [7:0] TXRUNDISP;
4030 
input BREFCLKNIN;
4031 
input BREFCLKPIN;
4032 
input [4:0] CHBONDI;
4033 
input ENCHANSYNC;
4034 
input ENMCOMMAALIGN;
4035 
input ENPCOMMAALIGN;
4036 
input [1:0] LOOPBACK;
4037 
input PMAINIT;
4038 
input [5:0] PMAREGADDR;
4039 
input [7:0] PMAREGDATAIN;
4040 
input PMAREGRW;
4041 
input PMAREGSTROBE;
4042 
input [1:0] PMARXLOCKSEL;
4043 
input POWERDOWN;
4044 
input REFCLK;
4045 
input REFCLK2;
4046 
input REFCLKBSEL;
4047 
input REFCLKSEL;
4048 
input RXBLOCKSYNC64B66BUSE;
4049 
input RXCOMMADETUSE;
4050 
input [1:0] RXDATAWIDTH;
4051 
input RXDEC64B66BUSE;
4052 
input RXDEC8B10BUSE;
4053 
input RXDESCRAM64B66BUSE;
4054 
input RXIGNOREBTF;
4055 
input [1:0] RXINTDATAWIDTH;
4056 
input RXN;
4057 
input RXP;
4058 
input RXPOLARITY;
4059 
input RXRESET;
4060 
input RXSLIDE;
4061 
input RXUSRCLK;
4062 
input RXUSRCLK2;
4063 
input [7:0] TXBYPASS8B10B;
4064 
input [7:0] TXCHARDISPMODE;
4065 
input [7:0] TXCHARDISPVAL;
4066 
input [7:0] TXCHARISK;
4067 
input [63:0] TXDATA;
4068 
input [1:0] TXDATAWIDTH;
4069 
input TXENC64B66BUSE;
4070 
input TXENC8B10BUSE;
4071 
input TXGEARBOX64B66BUSE;
4072 
input TXINHIBIT;
4073 
input [1:0] TXINTDATAWIDTH;
4074 
input TXPOLARITY;
4075 
input TXRESET;
4076 
input TXSCRAM64B66BUSE;
4077 
input TXUSRCLK;
4078 
input TXUSRCLK2;
4079 
endmodule
4080 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4081 
module GT10_XAUI_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
4082 
parameter integer ALIGN_COMMA_WORD = 2;
4083 
parameter integer CHAN_BOND_LIMIT = 16;
4084 
parameter CHAN_BOND_MODE = "OFF";
4085 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
4086 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
4087 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
4088 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
4089 
parameter integer CHAN_BOND_SEQ_LEN = 2;
4090 
parameter CLK_COR_8B10B_DE = "FALSE";
4091 
parameter integer CLK_COR_MAX_LAT = 36;
4092 
parameter integer CLK_COR_MIN_LAT = 28;
4093 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
4094 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
4095 
parameter CLK_COR_SEQ_2_USE = "FALSE";
4096 
parameter CLK_COR_SEQ_DROP = "FALSE";
4097 
parameter integer CLK_COR_SEQ_LEN = 2;
4098 
parameter CLK_CORRECT_USE = "TRUE";
4099 
parameter DEC_MCOMMA_DETECT = "TRUE";
4100 
parameter DEC_PCOMMA_DETECT = "TRUE";
4101 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
4102 
parameter PMA_PWR_CNTRL = 8'b11111111;
4103 
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32263068090104a628;
4104 
parameter PMA_SPEED_USE = "PMA_SPEED";
4105 
parameter RX_BUFFER_USE = "TRUE";
4106 
parameter integer RX_LOS_INVALID_INCR = 1;
4107 
parameter integer RX_LOS_THRESHOLD = 4;
4108 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
4109 
parameter TX_BUFFER_USE = "TRUE";
4110 
output CHBONDDONE;
4111 
output [4:0] CHBONDO;
4112 
output PMARXLOCK;
4113 
output [1:0] RXBUFSTATUS;
4114 
output [0:0] RXCHARISCOMMA;
4115 
output [0:0] RXCHARISK;
4116 
output [2:0] RXCLKCORCNT;
4117 
output RXCOMMADET;
4118 
output [7:0] RXDATA;
4119 
output [0:0] RXDISPERR;
4120 
output [1:0] RXLOSSOFSYNC;
4121 
output [0:0] RXNOTINTABLE;
4122 
output RXREALIGN;
4123 
output RXRECCLK;
4124 
output [0:0] RXRUNDISP;
4125 
output TXBUFERR;
4126 
output [0:0] TXKERR;
4127 
output TXN;
4128 
output TXOUTCLK;
4129 
output TXP;
4130 
output [0:0] TXRUNDISP;
4131 
input BREFCLKNIN;
4132 
input BREFCLKPIN;
4133 
input [4:0] CHBONDI;
4134 
input ENCHANSYNC;
4135 
input ENMCOMMAALIGN;
4136 
input ENPCOMMAALIGN;
4137 
input [1:0] LOOPBACK;
4138 
input PMAINIT;
4139 
input [5:0] PMAREGADDR;
4140 
input [7:0] PMAREGDATAIN;
4141 
input PMAREGRW;
4142 
input PMAREGSTROBE;
4143 
input [1:0] PMARXLOCKSEL;
4144 
input POWERDOWN;
4145 
input REFCLK;
4146 
input REFCLK2;
4147 
input REFCLKBSEL;
4148 
input REFCLKSEL;
4149 
input RXBLOCKSYNC64B66BUSE;
4150 
input RXCOMMADETUSE;
4151 
input [1:0] RXDATAWIDTH;
4152 
input RXDEC64B66BUSE;
4153 
input RXDEC8B10BUSE;
4154 
input RXDESCRAM64B66BUSE;
4155 
input RXIGNOREBTF;
4156 
input [1:0] RXINTDATAWIDTH;
4157 
input RXN;
4158 
input RXP;
4159 
input RXPOLARITY;
4160 
input RXRESET;
4161 
input RXSLIDE;
4162 
input RXUSRCLK;
4163 
input RXUSRCLK2;
4164 
input [0:0] TXBYPASS8B10B;
4165 
input [0:0] TXCHARDISPMODE;
4166 
input [0:0] TXCHARDISPVAL;
4167 
input [0:0] TXCHARISK;
4168 
input [7:0] TXDATA;
4169 
input [1:0] TXDATAWIDTH;
4170 
input TXENC64B66BUSE;
4171 
input TXENC8B10BUSE;
4172 
input TXGEARBOX64B66BUSE;
4173 
input TXINHIBIT;
4174 
input [1:0] TXINTDATAWIDTH;
4175 
input TXPOLARITY;
4176 
input TXRESET;
4177 
input TXSCRAM64B66BUSE;
4178 
input TXUSRCLK;
4179 
input TXUSRCLK2;
4180 
endmodule
4181 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4182 
module GT10_XAUI_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
4183 
parameter integer ALIGN_COMMA_WORD = 2;
4184 
parameter integer CHAN_BOND_LIMIT = 16;
4185 
parameter CHAN_BOND_MODE = "OFF";
4186 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
4187 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
4188 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
4189 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
4190 
parameter integer CHAN_BOND_SEQ_LEN = 2;
4191 
parameter CLK_COR_8B10B_DE = "FALSE";
4192 
parameter integer CLK_COR_MAX_LAT = 36;
4193 
parameter integer CLK_COR_MIN_LAT = 28;
4194 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
4195 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
4196 
parameter CLK_COR_SEQ_2_USE = "FALSE";
4197 
parameter CLK_COR_SEQ_DROP = "FALSE";
4198 
parameter integer CLK_COR_SEQ_LEN = 2;
4199 
parameter CLK_CORRECT_USE = "TRUE";
4200 
parameter DEC_MCOMMA_DETECT = "TRUE";
4201 
parameter DEC_PCOMMA_DETECT = "TRUE";
4202 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
4203 
parameter PMA_PWR_CNTRL = 8'b11111111;
4204 
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32663068090105a628;
4205 
parameter PMA_SPEED_USE = "PMA_SPEED";
4206 
parameter RX_BUFFER_USE = "TRUE";
4207 
parameter integer RX_LOS_INVALID_INCR = 1;
4208 
parameter integer RX_LOS_THRESHOLD = 4;
4209 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
4210 
parameter TX_BUFFER_USE = "TRUE";
4211 
output CHBONDDONE;
4212 
output [4:0] CHBONDO;
4213 
output PMARXLOCK;
4214 
output [1:0] RXBUFSTATUS;
4215 
output [1:0] RXCHARISCOMMA;
4216 
output [1:0] RXCHARISK;
4217 
output [2:0] RXCLKCORCNT;
4218 
output RXCOMMADET;
4219 
output [15:0] RXDATA;
4220 
output [1:0] RXDISPERR;
4221 
output [1:0] RXLOSSOFSYNC;
4222 
output [1:0] RXNOTINTABLE;
4223 
output RXREALIGN;
4224 
output RXRECCLK;
4225 
output [1:0] RXRUNDISP;
4226 
output TXBUFERR;
4227 
output [1:0] TXKERR;
4228 
output TXN;
4229 
output TXOUTCLK;
4230 
output TXP;
4231 
output [1:0] TXRUNDISP;
4232 
input BREFCLKNIN;
4233 
input BREFCLKPIN;
4234 
input [4:0] CHBONDI;
4235 
input ENCHANSYNC;
4236 
input ENMCOMMAALIGN;
4237 
input ENPCOMMAALIGN;
4238 
input [1:0] LOOPBACK;
4239 
input PMAINIT;
4240 
input [5:0] PMAREGADDR;
4241 
input [7:0] PMAREGDATAIN;
4242 
input PMAREGRW;
4243 
input PMAREGSTROBE;
4244 
input [1:0] PMARXLOCKSEL;
4245 
input POWERDOWN;
4246 
input REFCLK;
4247 
input REFCLK2;
4248 
input REFCLKBSEL;
4249 
input REFCLKSEL;
4250 
input RXBLOCKSYNC64B66BUSE;
4251 
input RXCOMMADETUSE;
4252 
input [1:0] RXDATAWIDTH;
4253 
input RXDEC64B66BUSE;
4254 
input RXDEC8B10BUSE;
4255 
input RXDESCRAM64B66BUSE;
4256 
input RXIGNOREBTF;
4257 
input [1:0] RXINTDATAWIDTH;
4258 
input RXN;
4259 
input RXP;
4260 
input RXPOLARITY;
4261 
input RXRESET;
4262 
input RXSLIDE;
4263 
input RXUSRCLK;
4264 
input RXUSRCLK2;
4265 
input [1:0] TXBYPASS8B10B;
4266 
input [1:0] TXCHARDISPMODE;
4267 
input [1:0] TXCHARDISPVAL;
4268 
input [1:0] TXCHARISK;
4269 
input [15:0] TXDATA;
4270 
input [1:0] TXDATAWIDTH;
4271 
input TXENC64B66BUSE;
4272 
input TXENC8B10BUSE;
4273 
input TXGEARBOX64B66BUSE;
4274 
input TXINHIBIT;
4275 
input [1:0] TXINTDATAWIDTH;
4276 
input TXPOLARITY;
4277 
input TXRESET;
4278 
input TXSCRAM64B66BUSE;
4279 
input TXUSRCLK;
4280 
input TXUSRCLK2;
4281 
endmodule
4282 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4283 
module GT10_XAUI_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
4284 
parameter integer ALIGN_COMMA_WORD = 2;
4285 
parameter integer CHAN_BOND_LIMIT = 16;
4286 
parameter CHAN_BOND_MODE = "OFF";
4287 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
4288 
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
4289 
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
4290 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
4291 
parameter integer CHAN_BOND_SEQ_LEN = 2;
4292 
parameter CLK_COR_8B10B_DE = "FALSE";
4293 
parameter integer CLK_COR_MAX_LAT = 36;
4294 
parameter integer CLK_COR_MIN_LAT = 28;
4295 
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
4296 
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
4297 
parameter CLK_COR_SEQ_2_USE = "FALSE";
4298 
parameter CLK_COR_SEQ_DROP = "FALSE";
4299 
parameter integer CLK_COR_SEQ_LEN = 2;
4300 
parameter CLK_CORRECT_USE = "TRUE";
4301 
parameter DEC_MCOMMA_DETECT = "TRUE";
4302 
parameter DEC_PCOMMA_DETECT = "TRUE";
4303 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
4304 
parameter PMA_PWR_CNTRL = 8'b11111111;
4305 
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a628;
4306 
parameter PMA_SPEED_USE = "PMA_SPEED";
4307 
parameter RX_BUFFER_USE = "TRUE";
4308 
parameter integer RX_LOS_INVALID_INCR = 1;
4309 
parameter integer RX_LOS_THRESHOLD = 4;
4310 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
4311 
parameter TX_BUFFER_USE = "TRUE";
4312 
output CHBONDDONE;
4313 
output [4:0] CHBONDO;
4314 
output PMARXLOCK;
4315 
output [1:0] RXBUFSTATUS;
4316 
output [3:0] RXCHARISCOMMA;
4317 
output [3:0] RXCHARISK;
4318 
output [2:0] RXCLKCORCNT;
4319 
output RXCOMMADET;
4320 
output [31:0] RXDATA;
4321 
output [3:0] RXDISPERR;
4322 
output [1:0] RXLOSSOFSYNC;
4323 
output [3:0] RXNOTINTABLE;
4324 
output RXREALIGN;
4325 
output RXRECCLK;
4326 
output [3:0] RXRUNDISP;
4327 
output TXBUFERR;
4328 
output [3:0] TXKERR;
4329 
output TXN;
4330 
output TXOUTCLK;
4331 
output TXP;
4332 
output [3:0] TXRUNDISP;
4333 
input BREFCLKNIN;
4334 
input BREFCLKPIN;
4335 
input [4:0] CHBONDI;
4336 
input ENCHANSYNC;
4337 
input ENMCOMMAALIGN;
4338 
input ENPCOMMAALIGN;
4339 
input [1:0] LOOPBACK;
4340 
input PMAINIT;
4341 
input [5:0] PMAREGADDR;
4342 
input [7:0] PMAREGDATAIN;
4343 
input PMAREGRW;
4344 
input PMAREGSTROBE;
4345 
input [1:0] PMARXLOCKSEL;
4346 
input POWERDOWN;
4347 
input REFCLK;
4348 
input REFCLK2;
4349 
input REFCLKBSEL;
4350 
input REFCLKSEL;
4351 
input RXBLOCKSYNC64B66BUSE;
4352 
input RXCOMMADETUSE;
4353 
input [1:0] RXDATAWIDTH;
4354 
input RXDEC64B66BUSE;
4355 
input RXDEC8B10BUSE;
4356 
input RXDESCRAM64B66BUSE;
4357 
input RXIGNOREBTF;
4358 
input [1:0] RXINTDATAWIDTH;
4359 
input RXN;
4360 
input RXP;
4361 
input RXPOLARITY;
4362 
input RXRESET;
4363 
input RXSLIDE;
4364 
input RXUSRCLK;
4365 
input RXUSRCLK2;
4366 
input [3:0] TXBYPASS8B10B;
4367 
input [3:0] TXCHARDISPMODE;
4368 
input [3:0] TXCHARDISPVAL;
4369 
input [3:0] TXCHARISK;
4370 
input [31:0] TXDATA;
4371 
input [1:0] TXDATAWIDTH;
4372 
input TXENC64B66BUSE;
4373 
input TXENC8B10BUSE;
4374 
input TXGEARBOX64B66BUSE;
4375 
input TXINHIBIT;
4376 
input [1:0] TXINTDATAWIDTH;
4377 
input TXPOLARITY;
4378 
input TXRESET;
4379 
input TXSCRAM64B66BUSE;
4380 
input TXUSRCLK;
4381 
input TXUSRCLK2;
4382 
endmodule
4383 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4384 
module GT11CLK_MGT (SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP);
4385 
parameter SYNCLK1OUTEN = "ENABLE";
4386 
parameter SYNCLK2OUTEN = "DISABLE";
4387 
output SYNCLK1OUT;
4388 
output SYNCLK2OUT;
4389 
input MGTCLKN;
4390 
input MGTCLKP;
4391 
endmodule
4392 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4393 
module GT11CLK (SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP, REFCLK, RXBCLK, SYNCLK1IN, SYNCLK2IN);
4394 
parameter REFCLKSEL = "MGTCLK";
4395 
parameter SYNCLK1OUTEN = "ENABLE";
4396 
parameter SYNCLK2OUTEN = "DISABLE";
4397 
output SYNCLK1OUT;
4398 
output SYNCLK2OUT;
4399 
input MGTCLKN;
4400 
input MGTCLKP;
4401 
input REFCLK;
4402 
input RXBCLK;
4403 
input SYNCLK1IN;
4404 
input SYNCLK2IN;
4405 
endmodule
4406 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4407 
module GT11_CUSTOM (CHBONDO, DO, DRDY, RXBUFERR, RXCALFAIL, RXCHARISCOMMA, RXCHARISK, RXCOMMADET, RXCRCOUT, RXCYCLELIMIT, RXDATA, RXDISPERR, RXLOCK, RXLOSSOFSYNC, RXMCLK, RXNOTINTABLE, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXRUNDISP, RXSIGDET, RXSTATUS, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCRCOUT, TXCYCLELIMIT, TXKERR, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT, TXRUNDISP, CHBONDI, DADDR, DCLK, DEN, DI, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK, LOOPBACK, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCDATAWIDTH, RXCRCIN, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXPMARESET, RXPOLARITY, RXRESET, RXSLIDE, RXSYNC, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCDATAWIDTH, TXCRCIN, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC, TXUSRCLK, TXUSRCLK2);
4408 
parameter BANDGAPSEL = "FALSE";
4409 
parameter BIASRESSEL = "FALSE";
4410 
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
4411 
parameter CHAN_BOND_MODE = "NONE";
4412 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
4413 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
4414 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
4415 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
4416 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
4417 
parameter CHAN_BOND_SEQ_1_MASK = 4'b1110;
4418 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
4419 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
4420 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
4421 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
4422 
parameter CHAN_BOND_SEQ_2_MASK = 4'b1110;
4423 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
4424 
parameter CLK_CORRECT_USE = "FALSE";
4425 
parameter CLK_COR_8B10B_DE = "FALSE";
4426 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
4427 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
4428 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
4429 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
4430 
parameter CLK_COR_SEQ_1_MASK = 4'b1110;
4431 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
4432 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
4433 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
4434 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
4435 
parameter CLK_COR_SEQ_2_MASK = 4'b1110;
4436 
parameter CLK_COR_SEQ_2_USE = "FALSE";
4437 
parameter CLK_COR_SEQ_DROP = "FALSE";
4438 
parameter COMMA32 = "FALSE";
4439 
parameter COMMA_10B_MASK = 10'h3FF;
4440 
parameter CYCLE_LIMIT_SEL = 2'b00;
4441 
parameter DCDR_FILTER = 3'b010;
4442 
parameter DEC_MCOMMA_DETECT = "TRUE";
4443 
parameter DEC_PCOMMA_DETECT = "TRUE";
4444 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
4445 
parameter DIGRX_FWDCLK = 2'b00;
4446 
parameter DIGRX_SYNC_MODE = "FALSE";
4447 
parameter ENABLE_DCDR = "FALSE";
4448 
parameter FDET_HYS_CAL = 3'b010;
4449 
parameter FDET_HYS_SEL = 3'b100;
4450 
parameter FDET_LCK_CAL = 3'b100;
4451 
parameter FDET_LCK_SEL = 3'b001;
4452 
parameter IREFBIASMODE = 2'b11;
4453 
parameter LOOPCAL_WAIT = 2'b00;
4454 
parameter MCOMMA_32B_VALUE = 32'h00000000;
4455 
parameter MCOMMA_DETECT = "TRUE";
4456 
parameter OPPOSITE_SELECT = "FALSE";
4457 
parameter PCOMMA_32B_VALUE = 32'h00000000;
4458 
parameter PCOMMA_DETECT = "TRUE";
4459 
parameter PCS_BIT_SLIP = "FALSE";
4460 
parameter PMACLKENABLE = "TRUE";
4461 
parameter PMACOREPWRENABLE = "TRUE";
4462 
parameter PMAIREFTRIM = 4'b0111;
4463 
parameter PMAVBGCTRL = 5'b00000;
4464 
parameter PMAVREFTRIM = 4'b0111;
4465 
parameter PMA_BIT_SLIP = "FALSE";
4466 
parameter POWER_ENABLE = "TRUE";
4467 
parameter REPEATER = "FALSE";
4468 
parameter RXACTST = "FALSE";
4469 
parameter RXAFEEQ = 9'b000000000;
4470 
parameter RXAFEPD = "FALSE";
4471 
parameter RXAFETST = "FALSE";
4472 
parameter RXAPD = "FALSE";
4473 
parameter RXAREGCTRL = 5'b00000;
4474 
parameter RXASYNCDIVIDE = 2'b11;
4475 
parameter RXBY_32 = "FALSE";
4476 
parameter RXCDRLOS = 6'b000000;
4477 
parameter RXCLK0_FORCE_PMACLK = "FALSE";
4478 
parameter RXCLKMODE = 6'b110001;
4479 
parameter RXCLMODE = 2'b00;
4480 
parameter RXCMADJ = 2'b01;
4481 
parameter RXCPSEL = "TRUE";
4482 
parameter RXCPTST = "FALSE";
4483 
parameter RXCRCCLOCKDOUBLE = "FALSE";
4484 
parameter RXCRCENABLE = "FALSE";
4485 
parameter RXCRCINITVAL = 32'h00000000;
4486 
parameter RXCRCINVERTGEN = "FALSE";
4487 
parameter RXCRCSAMECLOCK = "FALSE";
4488 
parameter RXCTRL1 = 10'h200;
4489 
parameter RXCYCLE_LIMIT_SEL = 2'b00;
4490 
parameter RXDATA_SEL = 2'b00;
4491 
parameter RXDCCOUPLE = "FALSE";
4492 
parameter RXDIGRESET = "FALSE";
4493 
parameter RXDIGRX = "FALSE";
4494 
parameter RXEQ = 64'h4000000000000000;
4495 
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
4496 
parameter RXFDET_HYS_CAL = 3'b010;
4497 
parameter RXFDET_HYS_SEL = 3'b100;
4498 
parameter RXFDET_LCK_CAL = 3'b100;
4499 
parameter RXFDET_LCK_SEL = 3'b001;
4500 
parameter RXFECONTROL1 = 2'b00;
4501 
parameter RXFECONTROL2 = 3'b000;
4502 
parameter RXFETUNE = 2'b01;
4503 
parameter RXLB = "FALSE";
4504 
parameter RXLKADJ = 5'b00000;
4505 
parameter RXLKAPD = "FALSE";
4506 
parameter RXLOOPCAL_WAIT = 2'b00;
4507 
parameter RXLOOPFILT = 4'b0111;
4508 
parameter RXMODE = 6'b000000;
4509 
parameter RXPD = "FALSE";
4510 
parameter RXPDDTST = "TRUE";
4511 
parameter RXPMACLKSEL = "REFCLK1";
4512 
parameter RXRCPADJ = 3'b011;
4513 
parameter RXRCPPD = "FALSE";
4514 
parameter RXRECCLK1_USE_SYNC = "FALSE";
4515 
parameter RXRIBADJ = 2'b11;
4516 
parameter RXRPDPD = "FALSE";
4517 
parameter RXRSDPD = "FALSE";
4518 
parameter RXSLOWDOWN_CAL = 2'b00;
4519 
parameter RXTUNE = 13'h0000;
4520 
parameter RXVCODAC_INIT = 10'b1010000000;
4521 
parameter RXVCO_CTRL_ENABLE = "FALSE";
4522 
parameter RX_BUFFER_USE = "TRUE";
4523 
parameter RX_CLOCK_DIVIDER = 2'b00;
4524 
parameter SAMPLE_8X = "FALSE";
4525 
parameter SLOWDOWN_CAL = 2'b00;
4526 
parameter TXABPMACLKSEL = "REFCLK1";
4527 
parameter TXAPD = "FALSE";
4528 
parameter TXAREFBIASSEL = "TRUE";
4529 
parameter TXASYNCDIVIDE = 2'b11;
4530 
parameter TXCLK0_FORCE_PMACLK = "FALSE";
4531 
parameter TXCLKMODE = 4'b1001;
4532 
parameter TXCLMODE = 2'b00;
4533 
parameter TXCPSEL = "TRUE";
4534 
parameter TXCRCCLOCKDOUBLE = "FALSE";
4535 
parameter TXCRCENABLE = "FALSE";
4536 
parameter TXCRCINITVAL = 32'h00000000;
4537 
parameter TXCRCINVERTGEN = "FALSE";
4538 
parameter TXCRCSAMECLOCK = "FALSE";
4539 
parameter TXCTRL1 = 10'h200;
4540 
parameter TXDATA_SEL = 2'b00;
4541 
parameter TXDAT_PRDRV_DAC = 3'b111;
4542 
parameter TXDAT_TAP_DAC = 5'b10110;
4543 
parameter TXDIGPD = "FALSE";
4544 
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
4545 
parameter TXHIGHSIGNALEN = "TRUE";
4546 
parameter TXLOOPFILT = 4'b0111;
4547 
parameter TXLVLSHFTPD = "FALSE";
4548 
parameter TXOUTCLK1_USE_SYNC = "FALSE";
4549 
parameter TXPD = "FALSE";
4550 
parameter TXPHASESEL = "FALSE";
4551 
parameter TXPOST_PRDRV_DAC = 3'b111;
4552 
parameter TXPOST_TAP_DAC = 5'b01110;
4553 
parameter TXPOST_TAP_PD = "TRUE";
4554 
parameter TXPRE_PRDRV_DAC = 3'b111;
4555 
parameter TXPRE_TAP_DAC = 5'b00000;
4556 
parameter TXPRE_TAP_PD = "TRUE";
4557 
parameter TXSLEWRATE = "FALSE";
4558 
parameter TXTERMTRIM = 4'b1100;
4559 
parameter TXTUNE = 13'h0000;
4560 
parameter TX_BUFFER_USE = "TRUE";
4561 
parameter TX_CLOCK_DIVIDER = 2'b00;
4562 
parameter VCODAC_INIT = 10'b1010000000;
4563 
parameter VCO_CTRL_ENABLE = "FALSE";
4564 
parameter VREFBIASMODE = 2'b11;
4565 
parameter integer ALIGN_COMMA_WORD = 4;
4566 
parameter integer CHAN_BOND_LIMIT = 16;
4567 
parameter integer CHAN_BOND_SEQ_LEN = 1;
4568 
parameter integer CLK_COR_MAX_LAT = 48;
4569 
parameter integer CLK_COR_MIN_LAT = 36;
4570 
parameter integer CLK_COR_SEQ_LEN = 1;
4571 
parameter integer RXOUTDIV2SEL = 1;
4572 
parameter integer RXPLLNDIVSEL = 8;
4573 
parameter integer RXUSRDIVISOR = 1;
4574 
parameter integer SH_CNT_MAX = 64;
4575 
parameter integer SH_INVALID_CNT_MAX = 16;
4576 
parameter integer TXOUTDIV2SEL = 1;
4577 
parameter integer TXPLLNDIVSEL = 8;
4578 
output [4:0] CHBONDO;
4579 
output [15:0] DO;
4580 
output DRDY;
4581 
output RXBUFERR;
4582 
output RXCALFAIL;
4583 
output [7:0] RXCHARISCOMMA;
4584 
output [7:0] RXCHARISK;
4585 
output RXCOMMADET;
4586 
output [31:0] RXCRCOUT;
4587 
output RXCYCLELIMIT;
4588 
output [63:0] RXDATA;
4589 
output [7:0] RXDISPERR;
4590 
output RXLOCK;
4591 
output [1:0] RXLOSSOFSYNC;
4592 
output RXMCLK;
4593 
output [7:0] RXNOTINTABLE;
4594 
output RXPCSHCLKOUT;
4595 
output RXREALIGN;
4596 
output RXRECCLK1;
4597 
output RXRECCLK2;
4598 
output [7:0] RXRUNDISP;
4599 
output RXSIGDET;
4600 
output [5:0] RXSTATUS;
4601 
output TX1N;
4602 
output TX1P;
4603 
output TXBUFERR;
4604 
output TXCALFAIL;
4605 
output [31:0] TXCRCOUT;
4606 
output TXCYCLELIMIT;
4607 
output [7:0] TXKERR;
4608 
output TXLOCK;
4609 
output TXOUTCLK1;
4610 
output TXOUTCLK2;
4611 
output TXPCSHCLKOUT;
4612 
output [7:0] TXRUNDISP;
4613 
input [4:0] CHBONDI;
4614 
input [7:0] DADDR;
4615 
input DCLK;
4616 
input DEN;
4617 
input [15:0] DI;
4618 
input DWE;
4619 
input ENCHANSYNC;
4620 
input ENMCOMMAALIGN;
4621 
input ENPCOMMAALIGN;
4622 
input GREFCLK;
4623 
input [1:0] LOOPBACK;
4624 
input POWERDOWN;
4625 
input REFCLK1;
4626 
input REFCLK2;
4627 
input RX1N;
4628 
input RX1P;
4629 
input RXBLOCKSYNC64B66BUSE;
4630 
input RXCLKSTABLE;
4631 
input RXCOMMADETUSE;
4632 
input RXCRCCLK;
4633 
input RXCRCDATAVALID;
4634 
input [2:0] RXCRCDATAWIDTH;
4635 
input [63:0] RXCRCIN;
4636 
input RXCRCINIT;
4637 
input RXCRCINTCLK;
4638 
input RXCRCPD;
4639 
input RXCRCRESET;
4640 
input [1:0] RXDATAWIDTH;
4641 
input RXDEC64B66BUSE;
4642 
input RXDEC8B10BUSE;
4643 
input RXDESCRAM64B66BUSE;
4644 
input RXIGNOREBTF;
4645 
input [1:0] RXINTDATAWIDTH;
4646 
input RXPMARESET;
4647 
input RXPOLARITY;
4648 
input RXRESET;
4649 
input RXSLIDE;
4650 
input RXSYNC;
4651 
input RXUSRCLK;
4652 
input RXUSRCLK2;
4653 
input [7:0] TXBYPASS8B10B;
4654 
input [7:0] TXCHARDISPMODE;
4655 
input [7:0] TXCHARDISPVAL;
4656 
input [7:0] TXCHARISK;
4657 
input TXCLKSTABLE;
4658 
input TXCRCCLK;
4659 
input TXCRCDATAVALID;
4660 
input [2:0] TXCRCDATAWIDTH;
4661 
input [63:0] TXCRCIN;
4662 
input TXCRCINIT;
4663 
input TXCRCINTCLK;
4664 
input TXCRCPD;
4665 
input TXCRCRESET;
4666 
input [63:0] TXDATA;
4667 
input [1:0] TXDATAWIDTH;
4668 
input TXENC64B66BUSE;
4669 
input TXENC8B10BUSE;
4670 
input TXENOOB;
4671 
input TXGEARBOX64B66BUSE;
4672 
input TXINHIBIT;
4673 
input [1:0] TXINTDATAWIDTH;
4674 
input TXPMARESET;
4675 
input TXPOLARITY;
4676 
input TXRESET;
4677 
input TXSCRAM64B66BUSE;
4678 
input TXSYNC;
4679 
input TXUSRCLK;
4680 
input TXUSRCLK2;
4681 
endmodule
4682 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
4683 
module GT11_DUAL (CHBONDOA, CHBONDOB, DOA, DOB, DRDYA, DRDYB, RXBUFERRA, RXBUFERRB, RXCALFAILA, RXCALFAILB, RXCHARISCOMMAA, RXCHARISCOMMAB, RXCHARISKA, RXCHARISKB, RXCOMMADETA, RXCOMMADETB, RXCRCOUTA, RXCRCOUTB, RXCYCLELIMITA, RXCYCLELIMITB, RXDATAA, RXDATAB, RXDISPERRA, RXDISPERRB, RXLOCKA, RXLOCKB, RXLOSSOFSYNCA, RXLOSSOFSYNCB, RXMCLKA, RXMCLKB, RXNOTINTABLEA, RXNOTINTABLEB, RXPCSHCLKOUTA, RXPCSHCLKOUTB, RXREALIGNA, RXREALIGNB, RXRECCLK1A, RXRECCLK1B, RXRECCLK2A, RXRECCLK2B, RXRUNDISPA, RXRUNDISPB, RXSIGDETA, RXSIGDETB, RXSTATUSA, RXSTATUSB, TX1NA, TX1NB, TX1PA, TX1PB, TXBUFERRA, TXBUFERRB, TXCALFAILA, TXCALFAILB, TXCRCOUTA, TXCRCOUTB, TXCYCLELIMITA, TXCYCLELIMITB, TXKERRA, TXKERRB, TXLOCKA, TXLOCKB, TXOUTCLK1A, TXOUTCLK1B, TXOUTCLK2A, TXOUTCLK2B, TXPCSHCLKOUTA, TXPCSHCLKOUTB, TXRUNDISPA, TXRUNDISPB, CHBONDIA, CHBONDIB, DADDRA, DADDRB, DCLKA, DCLKB, DENA, DENB, DIA, DIB, DWEA, DWEB, ENCHANSYNCA, ENCHANSYNCB, ENMCOMMAALIGNA, ENMCOMMAALIGNB, ENPCOMMAALIGNA, ENPCOMMAALIGNB, GREFCLKA, GREFCLKB, LOOPBACKA, LOOPBACKB, POWERDOWNA, POWERDOWNB, REFCLK1A, REFCLK1B, REFCLK2A, REFCLK2B, RX1NA, RX1NB, RX1PA, RX1PB, RXBLOCKSYNC64B66BUSEA, RXBLOCKSYNC64B66BUSEB, RXCLKSTABLEA, RXCLKSTABLEB, RXCOMMADETUSEA, RXCOMMADETUSEB, RXCRCCLKA, RXCRCCLKB, RXCRCDATAVALIDA, RXCRCDATAVALIDB, RXCRCDATAWIDTHA, RXCRCDATAWIDTHB, RXCRCINA, RXCRCINB, RXCRCINITA, RXCRCINITB, RXCRCINTCLKA, RXCRCINTCLKB, RXCRCPDA, RXCRCPDB, RXCRCRESETA, RXCRCRESETB, RXDATAWIDTHA, RXDATAWIDTHB, RXDEC64B66BUSEA, RXDEC64B66BUSEB, RXDEC8B10BUSEA, RXDEC8B10BUSEB, RXDESCRAM64B66BUSEA, RXDESCRAM64B66BUSEB, RXIGNOREBTFA, RXIGNOREBTFB, RXINTDATAWIDTHA, RXINTDATAWIDTHB, RXPMARESETA, RXPMARESETB, RXPOLARITYA, RXPOLARITYB, RXRESETA, RXRESETB, RXSLIDEA, RXSLIDEB, RXSYNCA, RXSYNCB, RXUSRCLK2A, RXUSRCLK2B, RXUSRCLKA, RXUSRCLKB, TXBYPASS8B10BA, TXBYPASS8B10BB, TXCHARDISPMODEA, TXCHARDISPMODEB, TXCHARDISPVALA, TXCHARDISPVALB, TXCHARISKA, TXCHARISKB, TXCLKSTABLEA, TXCLKSTABLEB, TXCRCCLKA, TXCRCCLKB, TXCRCDATAVALIDA, TXCRCDATAVALIDB, TXCRCDATAWIDTHA, TXCRCDATAWIDTHB, TXCRCINA, TXCRCINB, TXCRCINITA, TXCRCINITB, TXCRCINTCLKA, TXCRCINTCLKB, TXCRCPDA, TXCRCPDB, TXCRCRESETA, TXCRCRESETB, TXDATAA, TXDATAB, TXDATAWIDTHA, TXDATAWIDTHB, TXENC64B66BUSEA, TXENC64B66BUSEB, TXENC8B10BUSEA, TXENC8B10BUSEB, TXENOOBA, TXENOOBB, TXGEARBOX64B66BUSEA, TXGEARBOX64B66BUSEB, TXINHIBITA, TXINHIBITB, TXINTDATAWIDTHA, TXINTDATAWIDTHB, TXPMARESETA, TXPMARESETB, TXPOLARITYA, TXPOLARITYB, TXRESETA, TXRESETB, TXSCRAM64B66BUSEA, TXSCRAM64B66BUSEB, TXSYNCA, TXSYNCB, TXUSRCLK2A, TXUSRCLK2B, TXUSRCLKA, TXUSRCLKB);
4684 
parameter BANDGAPSEL_A = "FALSE";
4685 
parameter BANDGAPSEL_B = "FALSE";
4686 
parameter BIASRESSEL_A = "FALSE";
4687 
parameter BIASRESSEL_B = "FALSE";
4688 
parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE";
4689 
parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE";
4690 
parameter CHAN_BOND_MODE_A = "NONE";
4691 
parameter CHAN_BOND_MODE_B = "NONE";
4692 
parameter CHAN_BOND_ONE_SHOT_A = "FALSE";
4693 
parameter CHAN_BOND_ONE_SHOT_B = "FALSE";
4694 
parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000;
4695 
parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000;
4696 
parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000;
4697 
parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000;
4698 
parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000;
4699 
parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000;
4700 
parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000;
4701 
parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000;
4702 
parameter CHAN_BOND_SEQ_1_MASK_A = 4'b1110;
4703 
parameter CHAN_BOND_SEQ_1_MASK_B = 4'b1110;
4704 
parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000;
4705 
parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000;
4706 
parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000;
4707 
parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000;
4708 
parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000;
4709 
parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000;
4710 
parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000;
4711 
parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000;
4712 
parameter CHAN_BOND_SEQ_2_MASK_A = 4'b1110;
4713 
parameter CHAN_BOND_SEQ_2_MASK_B = 4'b1110;
4714 
parameter CHAN_BOND_SEQ_2_USE_A = "FALSE";
4715 
parameter CHAN_BOND_SEQ_2_USE_B = "FALSE";
4716 
parameter CLK_CORRECT_USE_A = "FALSE";
4717 
parameter CLK_CORRECT_USE_B = "FALSE";
4718 
parameter CLK_COR_8B10B_DE_A = "FALSE";
4719 
parameter CLK_COR_8B10B_DE_B = "FALSE";
4720 
parameter CLK_COR_SEQ_1_1_A = 11'b00000000000;
4721 
parameter CLK_COR_SEQ_1_1_B = 11'b00000000000;
4722 
parameter CLK_COR_SEQ_1_2_A = 11'b00000000000;
4723 
parameter CLK_COR_SEQ_1_2_B = 11'b00000000000;
4724 
parameter CLK_COR_SEQ_1_3_A = 11'b00000000000;
4725 
parameter CLK_COR_SEQ_1_3_B = 11'b00000000000;
4726 
parameter CLK_COR_SEQ_1_4_A = 11'b00000000000;
4727 
parameter CLK_COR_SEQ_1_4_B = 11'b00000000000;
4728 
parameter CLK_COR_SEQ_1_MASK_A = 4'b1110;
4729 
parameter CLK_COR_SEQ_1_MASK_B = 4'b1110;
4730 
parameter CLK_COR_SEQ_2_1_A = 11'b00000000000;
4731 
parameter CLK_COR_SEQ_2_1_B = 11'b00000000000;
4732 
parameter CLK_COR_SEQ_2_2_A = 11'b00000000000;
4733 
parameter CLK_COR_SEQ_2_2_B = 11'b00000000000;
4734 
parameter CLK_COR_SEQ_2_3_A = 11'b00000000000;
4735 
parameter CLK_COR_SEQ_2_3_B = 11'b00000000000;
4736 
parameter CLK_COR_SEQ_2_4_A = 11'b00000000000;
4737 
parameter CLK_COR_SEQ_2_4_B = 11'b00000000000;
4738 
parameter CLK_COR_SEQ_2_MASK_A = 4'b1110;
4739 
parameter CLK_COR_SEQ_2_MASK_B = 4'b1110;
4740 
parameter CLK_COR_SEQ_2_USE_A = "FALSE";
4741 
parameter CLK_COR_SEQ_2_USE_B = "FALSE";
4742 
parameter CLK_COR_SEQ_DROP_A = "FALSE";
4743 
parameter CLK_COR_SEQ_DROP_B = "FALSE";
4744 
parameter COMMA32_A = "FALSE";
4745 
parameter COMMA32_B = "FALSE";
4746 
parameter COMMA_10B_MASK_A = 10'h3FF;
4747 
parameter COMMA_10B_MASK_B = 10'h3FF;
4748 
parameter CYCLE_LIMIT_SEL_A = 2'b00;
4749 
parameter CYCLE_LIMIT_SEL_B = 2'b00;
4750 
parameter DCDR_FILTER_A = 3'b010;
4751 
parameter DCDR_FILTER_B = 3'b010;
4752 
parameter DEC_MCOMMA_DETECT_A = "TRUE";
4753 
parameter DEC_MCOMMA_DETECT_B = "TRUE";
4754 
parameter DEC_PCOMMA_DETECT_A = "TRUE";
4755 
parameter DEC_PCOMMA_DETECT_B = "TRUE";
4756 
parameter DEC_VALID_COMMA_ONLY_A = "TRUE";
4757 
parameter DEC_VALID_COMMA_ONLY_B = "TRUE";
4758 
parameter DIGRX_FWDCLK_A = 2'b00;
4759 
parameter DIGRX_FWDCLK_B = 2'b00;
4760 
parameter DIGRX_SYNC_MODE_A = "FALSE";
4761 
parameter DIGRX_SYNC_MODE_B = "FALSE";
4762 
parameter ENABLE_DCDR_A = "FALSE";
4763 
parameter ENABLE_DCDR_B = "FALSE";
4764 
parameter FDET_HYS_CAL_A = 3'b010;
4765 
parameter FDET_HYS_CAL_B = 3'b010;
4766 
parameter FDET_HYS_SEL_A = 3'b100;
4767 
parameter FDET_HYS_SEL_B = 3'b100;
4768 
parameter FDET_LCK_CAL_A = 3'b100;
4769 
parameter FDET_LCK_CAL_B = 3'b100;
4770 
parameter FDET_LCK_SEL_A = 3'b001;
4771 
parameter FDET_LCK_SEL_B = 3'b001;
4772 
parameter IREFBIASMODE_A = 2'b11;
4773 
parameter IREFBIASMODE_B = 2'b11;
4774 
parameter LOOPCAL_WAIT_A = 2'b00;
4775 
parameter LOOPCAL_WAIT_B = 2'b00;
4776 
parameter MCOMMA_32B_VALUE_A = 32'h00000000;
4777 
parameter MCOMMA_32B_VALUE_B = 32'h00000000;
4778 
parameter MCOMMA_DETECT_A = "TRUE";
4779 
parameter MCOMMA_DETECT_B = "TRUE";
4780 
parameter OPPOSITE_SELECT_A = "FALSE";
4781 
parameter OPPOSITE_SELECT_B = "FALSE";
4782 
parameter PCOMMA_32B_VALUE_A = 32'h00000000;
4783 
parameter PCOMMA_32B_VALUE_B = 32'h00000000;
4784 
parameter PCOMMA_DETECT_A = "TRUE";
4785 
parameter PCOMMA_DETECT_B = "TRUE";
4786 
parameter PCS_BIT_SLIP_A = "FALSE";
4787 
parameter PCS_BIT_SLIP_B = "FALSE";
4788 
parameter PMACLKENABLE_A = "TRUE";
4789 
parameter PMACLKENABLE_B = "TRUE";
4790 
parameter PMACOREPWRENABLE_A = "TRUE";
4791 
parameter PMACOREPWRENABLE_B = "TRUE";
4792 
parameter PMAIREFTRIM_A = 4'b0111;
4793 
parameter PMAIREFTRIM_B = 4'b0111;
4794 
parameter PMAVBGCTRL_A = 5'b00000;
4795 
parameter PMAVBGCTRL_B = 5'b00000;
4796 
parameter PMAVREFTRIM_A = 4'b0111;
4797 
parameter PMAVREFTRIM_B = 4'b0111;
4798 
parameter PMA_BIT_SLIP_A = "FALSE";
4799 
parameter PMA_BIT_SLIP_B = "FALSE";
4800 
parameter POWER_ENABLE_A = "TRUE";
4801 
parameter POWER_ENABLE_B = "TRUE";
4802 
parameter REPEATER_A = "FALSE";
4803 
parameter REPEATER_B = "FALSE";
4804 
parameter RXACTST_A = "FALSE";
4805 
parameter RXACTST_B = "FALSE";
4806 
parameter RXAFEEQ_A = 9'b000000000;
4807 
parameter RXAFEEQ_B = 9'b000000000;
4808 
parameter RXAFEPD_A = "FALSE";
4809 
parameter RXAFEPD_B = "FALSE";
4810 
parameter RXAFETST_A = "FALSE";
4811 
parameter RXAFETST_B = "FALSE";
4812 
parameter RXAPD_A = "FALSE";
4813 
parameter RXAPD_B = "FALSE";
4814 
parameter RXAREGCTRL_A = 5'b00000;
4815 
parameter RXAREGCTRL_B = 5'b00000;
4816 
parameter RXASYNCDIVIDE_A = 2'b11;
4817 
parameter RXASYNCDIVIDE_B = 2'b11;
4818 
parameter RXBY_32_A = "FALSE";
4819 
parameter RXBY_32_B = "FALSE";
4820 
parameter RXCDRLOS_A = 6'b000000;
4821 
parameter RXCDRLOS_B = 6'b000000;
4822 
parameter RXCLK0_FORCE_PMACLK_A = "FALSE";
4823 
parameter RXCLK0_FORCE_PMACLK_B = "FALSE";
4824 
parameter RXCLKMODE_A = 6'b110001;
4825 
parameter RXCLKMODE_B = 6'b110001;
4826 
parameter RXCLMODE_A = 2'b00;
4827 
parameter RXCLMODE_B = 2'b00;
4828 
parameter RXCMADJ_A = 2'b01;
4829 
parameter RXCMADJ_B = 2'b01;
4830 
parameter RXCPSEL_A = "TRUE";
4831 
parameter RXCPSEL_B = "TRUE";
4832 
parameter RXCPTST_A = "FALSE";
4833 
parameter RXCPTST_B = "FALSE";
4834 
parameter RXCRCCLOCKDOUBLE_A = "FALSE";
4835 
parameter RXCRCCLOCKDOUBLE_B = "FALSE";
4836 
parameter RXCRCENABLE_A = "FALSE";
4837 
parameter RXCRCENABLE_B = "FALSE";
4838 
parameter RXCRCINITVAL_A = 32'h00000000;
4839 
parameter RXCRCINITVAL_B = 32'h00000000;
4840 
parameter RXCRCINVERTGEN_A = "FALSE";
4841 
parameter RXCRCINVERTGEN_B = "FALSE";
4842 
parameter RXCRCSAMECLOCK_A = "FALSE";
4843 
parameter RXCRCSAMECLOCK_B = "FALSE";
4844 
parameter RXCTRL1_A = 10'h200;
4845 
parameter RXCTRL1_B = 10'h200;
4846 
parameter RXCYCLE_LIMIT_SEL_A = 2'b00;
4847 
parameter RXCYCLE_LIMIT_SEL_B = 2'b00;
4848 
parameter RXDATA_SEL_A = 2'b00;
4849 
parameter RXDATA_SEL_B = 2'b00;
4850 
parameter RXDCCOUPLE_A = "FALSE";
4851 
parameter RXDCCOUPLE_B = "FALSE";
4852 
parameter RXDIGRESET_A = "FALSE";
4853 
parameter RXDIGRESET_B = "FALSE";
4854 
parameter RXDIGRX_A = "FALSE";
4855 
parameter RXDIGRX_B = "FALSE";
4856 
parameter RXEQ_A = 64'h4000000000000000;
4857 
parameter RXEQ_B = 64'h4000000000000000;
4858 
parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE";
4859 
parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE";
4860 
parameter RXFDET_HYS_CAL_A = 3'b010;
4861 
parameter RXFDET_HYS_CAL_B = 3'b010;
4862 
parameter RXFDET_HYS_SEL_A = 3'b100;
4863 
parameter RXFDET_HYS_SEL_B = 3'b100;
4864 
parameter RXFDET_LCK_CAL_A = 3'b100;
4865 
parameter RXFDET_LCK_CAL_B = 3'b100;
4866 
parameter RXFDET_LCK_SEL_A = 3'b001;
4867 
parameter RXFDET_LCK_SEL_B = 3'b001;
4868 
parameter RXFECONTROL1_A = 2'b00;
4869 
parameter RXFECONTROL1_B = 2'b00;
4870 
parameter RXFECONTROL2_A = 3'b000;
4871 
parameter RXFECONTROL2_B = 3'b000;
4872 
parameter RXFETUNE_A = 2'b01;
4873 
parameter RXFETUNE_B = 2'b01;
4874 
parameter RXLB_A = "FALSE";
4875 
parameter RXLB_B = "FALSE";
4876 
parameter RXLKADJ_A = 5'b00000;
4877 
parameter RXLKADJ_B = 5'b00000;
4878 
parameter RXLKAPD_A = "FALSE";
4879 
parameter RXLKAPD_B = "FALSE";
4880 
parameter RXLOOPCAL_WAIT_A = 2'b00;
4881 
parameter RXLOOPCAL_WAIT_B = 2'b00;
4882 
parameter RXLOOPFILT_A = 4'b0111;
4883 
parameter RXLOOPFILT_B = 4'b0111;
4884 
parameter RXMODE_A = 6'b000000;
4885 
parameter RXMODE_B = 6'b000000;
4886 
parameter RXPDDTST_A = "TRUE";
4887 
parameter RXPDDTST_B = "TRUE";
4888 
parameter RXPD_A = "FALSE";
4889 
parameter RXPD_B = "FALSE";
4890 
parameter RXPMACLKSEL_A = "REFCLK1";
4891 
parameter RXPMACLKSEL_B = "REFCLK1";
4892 
parameter RXRCPADJ_A = 3'b011;
4893 
parameter RXRCPADJ_B = 3'b011;
4894 
parameter RXRCPPD_A = "FALSE";
4895 
parameter RXRCPPD_B = "FALSE";
4896 
parameter RXRECCLK1_USE_SYNC_A = "FALSE";
4897 
parameter RXRECCLK1_USE_SYNC_B = "FALSE";
4898 
parameter RXRIBADJ_A = 2'b11;
4899 
parameter RXRIBADJ_B = 2'b11;
4900 
parameter RXRPDPD_A = "FALSE";
4901 
parameter RXRPDPD_B = "FALSE";
4902 
parameter RXRSDPD_A = "FALSE";
4903 
parameter RXRSDPD_B = "FALSE";
4904 
parameter RXSLOWDOWN_CAL_A = 2'b00;
4905 
parameter RXSLOWDOWN_CAL_B = 2'b00;
4906 
parameter RXTUNE_A = 13'h0000;
4907 
parameter RXTUNE_B = 13'h0000;
4908 
parameter RXVCODAC_INIT_A = 10'b1010000000;
4909 
parameter RXVCODAC_INIT_B = 10'b1010000000;
4910 
parameter RXVCO_CTRL_ENABLE_A = "FALSE";
4911 
parameter RXVCO_CTRL_ENABLE_B = "FALSE";
4912 
parameter RX_BUFFER_USE_A = "TRUE";
4913 
parameter RX_BUFFER_USE_B = "TRUE";
4914 
parameter RX_CLOCK_DIVIDER_A = 2'b00;
4915 
parameter RX_CLOCK_DIVIDER_B = 2'b00;
4916 
parameter SAMPLE_8X_A = "FALSE";
4917 
parameter SAMPLE_8X_B = "FALSE";
4918 
parameter SLOWDOWN_CAL_A = 2'b00;
4919 
parameter SLOWDOWN_CAL_B = 2'b00;
4920 
parameter TXABPMACLKSEL_A = "REFCLK1";
4921 
parameter TXABPMACLKSEL_B = "REFCLK1";
4922 
parameter TXAPD_A = "FALSE";
4923 
parameter TXAPD_B = "FALSE";
4924 
parameter TXAREFBIASSEL_A = "TRUE";
4925 
parameter TXAREFBIASSEL_B = "TRUE";
4926 
parameter TXASYNCDIVIDE_A = 2'b11;
4927 
parameter TXASYNCDIVIDE_B = 2'b11;
4928 
parameter TXCLK0_FORCE_PMACLK_A = "FALSE";
4929 
parameter TXCLK0_FORCE_PMACLK_B = "FALSE";
4930 
parameter TXCLKMODE_A = 4'b1001;
4931 
parameter TXCLKMODE_B = 4'b1001;
4932 
parameter TXCLMODE_A = 2'b00;
4933 
parameter TXCLMODE_B = 2'b00;
4934 
parameter TXCPSEL_A = "TRUE";
4935 
parameter TXCPSEL_B = "TRUE";
4936 
parameter TXCRCCLOCKDOUBLE_A = "FALSE";
4937 
parameter TXCRCCLOCKDOUBLE_B = "FALSE";
4938 
parameter TXCRCENABLE_A = "FALSE";
4939 
parameter TXCRCENABLE_B = "FALSE";
4940 
parameter TXCRCINITVAL_A = 32'h00000000;
4941 
parameter TXCRCINITVAL_B = 32'h00000000;
4942 
parameter TXCRCINVERTGEN_A = "FALSE";
4943 
parameter TXCRCINVERTGEN_B = "FALSE";
4944 
parameter TXCRCSAMECLOCK_A = "FALSE";
4945 
parameter TXCRCSAMECLOCK_B = "FALSE";
4946 
parameter TXCTRL1_A = 10'h200;
4947 
parameter TXCTRL1_B = 10'h200;
4948 
parameter TXDATA_SEL_A = 2'b00;
4949 
parameter TXDATA_SEL_B = 2'b00;
4950 
parameter TXDAT_PRDRV_DAC_A = 3'b111;
4951 
parameter TXDAT_PRDRV_DAC_B = 3'b111;
4952 
parameter TXDAT_TAP_DAC_A = 5'b10110;
4953 
parameter TXDAT_TAP_DAC_B = 5'b10110;
4954 
parameter TXDIGPD_A = "FALSE";
4955 
parameter TXDIGPD_B = "FALSE";
4956 
parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE";
4957 
parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE";
4958 
parameter TXHIGHSIGNALEN_A = "TRUE";
4959 
parameter TXHIGHSIGNALEN_B = "TRUE";
4960 
parameter TXLOOPFILT_A = 4'b0111;
4961 
parameter TXLOOPFILT_B = 4'b0111;
4962 
parameter TXLVLSHFTPD_A = "FALSE";
4963 
parameter TXLVLSHFTPD_B = "FALSE";
4964 
parameter TXOUTCLK1_USE_SYNC_A = "FALSE";
4965 
parameter TXOUTCLK1_USE_SYNC_B = "FALSE";
4966 
parameter TXPD_A = "FALSE";
4967 
parameter TXPD_B = "FALSE";
4968 
parameter TXPHASESEL_A = "FALSE";
4969 
parameter TXPHASESEL_B = "FALSE";
4970 
parameter TXPOST_PRDRV_DAC_A = 3'b111;
4971 
parameter TXPOST_PRDRV_DAC_B = 3'b111;
4972 
parameter TXPOST_TAP_DAC_A = 5'b01110;
4973 
parameter TXPOST_TAP_DAC_B = 5'b01110;
4974 
parameter TXPOST_TAP_PD_A = "TRUE";
4975 
parameter TXPOST_TAP_PD_B = "TRUE";
4976 
parameter TXPRE_PRDRV_DAC_A = 3'b111;
4977 
parameter TXPRE_PRDRV_DAC_B = 3'b111;
4978 
parameter TXPRE_TAP_DAC_A = 5'b00000;
4979 
parameter TXPRE_TAP_DAC_B = 5'b00000;
4980 
parameter TXPRE_TAP_PD_A = "TRUE";
4981 
parameter TXPRE_TAP_PD_B = "TRUE";
4982 
parameter TXSLEWRATE_A = "FALSE";
4983 
parameter TXSLEWRATE_B = "FALSE";
4984 
parameter TXTERMTRIM_A = 4'b1100;
4985 
parameter TXTERMTRIM_B = 4'b1100;
4986 
parameter TXTUNE_A = 13'h0000;
4987 
parameter TXTUNE_B = 13'h0000;
4988 
parameter TX_BUFFER_USE_A = "TRUE";
4989 
parameter TX_BUFFER_USE_B = "TRUE";
4990 
parameter TX_CLOCK_DIVIDER_A = 2'b00;
4991 
parameter TX_CLOCK_DIVIDER_B = 2'b00;
4992 
parameter VCODAC_INIT_A = 10'b1010000000;
4993 
parameter VCODAC_INIT_B = 10'b1010000000;
4994 
parameter VCO_CTRL_ENABLE_A = "FALSE";
4995 
parameter VCO_CTRL_ENABLE_B = "FALSE";
4996 
parameter VREFBIASMODE_A = 2'b11;
4997 
parameter VREFBIASMODE_B = 2'b11;
4998 
parameter integer ALIGN_COMMA_WORD_A = 4;
4999 
parameter integer ALIGN_COMMA_WORD_B = 4;
5000 
parameter integer CHAN_BOND_LIMIT_A = 16;
5001 
parameter integer CHAN_BOND_LIMIT_B = 16;
5002 
parameter integer CHAN_BOND_SEQ_LEN_A = 1;
5003 
parameter integer CHAN_BOND_SEQ_LEN_B = 1;
5004 
parameter integer CLK_COR_MAX_LAT_A = 48;
5005 
parameter integer CLK_COR_MAX_LAT_B = 48;
5006 
parameter integer CLK_COR_MIN_LAT_A = 36;
5007 
parameter integer CLK_COR_MIN_LAT_B = 36;
5008 
parameter integer CLK_COR_SEQ_LEN_A = 1;
5009 
parameter integer CLK_COR_SEQ_LEN_B = 1;
5010 
parameter integer RXOUTDIV2SEL_A = 1;
5011 
parameter integer RXOUTDIV2SEL_B = 1;
5012 
parameter integer RXPLLNDIVSEL_A = 8;
5013 
parameter integer RXPLLNDIVSEL_B = 8;
5014 
parameter integer RXUSRDIVISOR_A = 1;
5015 
parameter integer RXUSRDIVISOR_B = 1;
5016 
parameter integer SH_CNT_MAX_A = 64;
5017 
parameter integer SH_CNT_MAX_B = 64;
5018 
parameter integer SH_INVALID_CNT_MAX_A = 16;
5019 
parameter integer SH_INVALID_CNT_MAX_B = 16;
5020 
parameter integer TXOUTDIV2SEL_A = 1;
5021 
parameter integer TXOUTDIV2SEL_B = 1;
5022 
parameter integer TXPLLNDIVSEL_A = 8;
5023 
parameter integer TXPLLNDIVSEL_B = 8;
5024 
output [4:0] CHBONDOA;
5025 
output [4:0] CHBONDOB;
5026 
output [15:0] DOA;
5027 
output [15:0] DOB;
5028 
output DRDYA;
5029 
output DRDYB;
5030 
output RXBUFERRA;
5031 
output RXBUFERRB;
5032 
output RXCALFAILA;
5033 
output RXCALFAILB;
5034 
output [7:0] RXCHARISCOMMAA;
5035 
output [7:0] RXCHARISCOMMAB;
5036 
output [7:0] RXCHARISKA;
5037 
output [7:0] RXCHARISKB;
5038 
output RXCOMMADETA;
5039 
output RXCOMMADETB;
5040 
output [31:0] RXCRCOUTA;
5041 
output [31:0] RXCRCOUTB;
5042 
output RXCYCLELIMITA;
5043 
output RXCYCLELIMITB;
5044 
output [63:0] RXDATAA;
5045 
output [63:0] RXDATAB;
5046 
output [7:0] RXDISPERRA;
5047 
output [7:0] RXDISPERRB;
5048 
output RXLOCKA;
5049 
output RXLOCKB;
5050 
output [1:0] RXLOSSOFSYNCA;
5051 
output [1:0] RXLOSSOFSYNCB;
5052 
output RXMCLKA;
5053 
output RXMCLKB;
5054 
output [7:0] RXNOTINTABLEA;
5055 
output [7:0] RXNOTINTABLEB;
5056 
output RXPCSHCLKOUTA;
5057 
output RXPCSHCLKOUTB;
5058 
output RXREALIGNA;
5059 
output RXREALIGNB;
5060 
output RXRECCLK1A;
5061 
output RXRECCLK1B;
5062 
output RXRECCLK2A;
5063 
output RXRECCLK2B;
5064 
output [7:0] RXRUNDISPA;
5065 
output [7:0] RXRUNDISPB;
5066 
output RXSIGDETA;
5067 
output RXSIGDETB;
5068 
output [5:0] RXSTATUSA;
5069 
output [5:0] RXSTATUSB;
5070 
output TX1NA;
5071 
output TX1NB;
5072 
output TX1PA;
5073 
output TX1PB;
5074 
output TXBUFERRA;
5075 
output TXBUFERRB;
5076 
output TXCALFAILA;
5077 
output TXCALFAILB;
5078 
output [31:0] TXCRCOUTA;
5079 
output [31:0] TXCRCOUTB;
5080 
output TXCYCLELIMITA;
5081 
output TXCYCLELIMITB;
5082 
output [7:0] TXKERRA;
5083 
output [7:0] TXKERRB;
5084 
output TXLOCKA;
5085 
output TXLOCKB;
5086 
output TXOUTCLK1A;
5087 
output TXOUTCLK1B;
5088 
output TXOUTCLK2A;
5089 
output TXOUTCLK2B;
5090 
output TXPCSHCLKOUTA;
5091 
output TXPCSHCLKOUTB;
5092 
output [7:0] TXRUNDISPA;
5093 
output [7:0] TXRUNDISPB;
5094 
input [4:0] CHBONDIA;
5095 
input [4:0] CHBONDIB;
5096 
input [7:0] DADDRA;
5097 
input [7:0] DADDRB;
5098 
input DCLKA;
5099 
input DCLKB;
5100 
input DENA;
5101 
input DENB;
5102 
input [15:0] DIA;
5103 
input [15:0] DIB;
5104 
input DWEA;
5105 
input DWEB;
5106 
input ENCHANSYNCA;
5107 
input ENCHANSYNCB;
5108 
input ENMCOMMAALIGNA;
5109 
input ENMCOMMAALIGNB;
5110 
input ENPCOMMAALIGNA;
5111 
input ENPCOMMAALIGNB;
5112 
input GREFCLKA;
5113 
input GREFCLKB;
5114 
input [1:0] LOOPBACKA;
5115 
input [1:0] LOOPBACKB;
5116 
input POWERDOWNA;
5117 
input POWERDOWNB;
5118 
input REFCLK1A;
5119 
input REFCLK1B;
5120 
input REFCLK2A;
5121 
input REFCLK2B;
5122 
input RX1NA;
5123 
input RX1NB;
5124 
input RX1PA;
5125 
input RX1PB;
5126 
input RXBLOCKSYNC64B66BUSEA;
5127 
input RXBLOCKSYNC64B66BUSEB;
5128 
input RXCLKSTABLEA;
5129 
input RXCLKSTABLEB;
5130 
input RXCOMMADETUSEA;
5131 
input RXCOMMADETUSEB;
5132 
input RXCRCCLKA;
5133 
input RXCRCCLKB;
5134 
input RXCRCDATAVALIDA;
5135 
input RXCRCDATAVALIDB;
5136 
input [2:0] RXCRCDATAWIDTHA;
5137 
input [2:0] RXCRCDATAWIDTHB;
5138 
input [63:0] RXCRCINA;
5139 
input [63:0] RXCRCINB;
5140 
input RXCRCINITA;
5141 
input RXCRCINITB;
5142 
input RXCRCINTCLKA;
5143 
input RXCRCINTCLKB;
5144 
input RXCRCPDA;
5145 
input RXCRCPDB;
5146 
input RXCRCRESETA;
5147 
input RXCRCRESETB;
5148 
input [1:0] RXDATAWIDTHA;
5149 
input [1:0] RXDATAWIDTHB;
5150 
input RXDEC64B66BUSEA;
5151 
input RXDEC64B66BUSEB;
5152 
input RXDEC8B10BUSEA;
5153 
input RXDEC8B10BUSEB;
5154 
input RXDESCRAM64B66BUSEA;
5155 
input RXDESCRAM64B66BUSEB;
5156 
input RXIGNOREBTFA;
5157 
input RXIGNOREBTFB;
5158 
input [1:0] RXINTDATAWIDTHA;
5159 
input [1:0] RXINTDATAWIDTHB;
5160 
input RXPMARESETA;
5161 
input RXPMARESETB;
5162 
input RXPOLARITYA;
5163 
input RXPOLARITYB;
5164 
input RXRESETA;
5165 
input RXRESETB;
5166 
input RXSLIDEA;
5167 
input RXSLIDEB;
5168 
input RXSYNCA;
5169 
input RXSYNCB;
5170 
input RXUSRCLK2A;
5171 
input RXUSRCLK2B;
5172 
input RXUSRCLKA;
5173 
input RXUSRCLKB;
5174 
input [7:0] TXBYPASS8B10BA;
5175 
input [7:0] TXBYPASS8B10BB;
5176 
input [7:0] TXCHARDISPMODEA;
5177 
input [7:0] TXCHARDISPMODEB;
5178 
input [7:0] TXCHARDISPVALA;
5179 
input [7:0] TXCHARDISPVALB;
5180 
input [7:0] TXCHARISKA;
5181 
input [7:0] TXCHARISKB;
5182 
input TXCLKSTABLEA;
5183 
input TXCLKSTABLEB;
5184 
input TXCRCCLKA;
5185 
input TXCRCCLKB;
5186 
input TXCRCDATAVALIDA;
5187 
input TXCRCDATAVALIDB;
5188 
input [2:0] TXCRCDATAWIDTHA;
5189 
input [2:0] TXCRCDATAWIDTHB;
5190 
input [63:0] TXCRCINA;
5191 
input [63:0] TXCRCINB;
5192 
input TXCRCINITA;
5193 
input TXCRCINITB;
5194 
input TXCRCINTCLKA;
5195 
input TXCRCINTCLKB;
5196 
input TXCRCPDA;
5197 
input TXCRCPDB;
5198 
input TXCRCRESETA;
5199 
input TXCRCRESETB;
5200 
input [63:0] TXDATAA;
5201 
input [63:0] TXDATAB;
5202 
input [1:0] TXDATAWIDTHA;
5203 
input [1:0] TXDATAWIDTHB;
5204 
input TXENC64B66BUSEA;
5205 
input TXENC64B66BUSEB;
5206 
input TXENC8B10BUSEA;
5207 
input TXENC8B10BUSEB;
5208 
input TXENOOBA;
5209 
input TXENOOBB;
5210 
input TXGEARBOX64B66BUSEA;
5211 
input TXGEARBOX64B66BUSEB;
5212 
input TXINHIBITA;
5213 
input TXINHIBITB;
5214 
input [1:0] TXINTDATAWIDTHA;
5215 
input [1:0] TXINTDATAWIDTHB;
5216 
input TXPMARESETA;
5217 
input TXPMARESETB;
5218 
input TXPOLARITYA;
5219 
input TXPOLARITYB;
5220 
input TXRESETA;
5221 
input TXRESETB;
5222 
input TXSCRAM64B66BUSEA;
5223 
input TXSCRAM64B66BUSEB;
5224 
input TXSYNCA;
5225 
input TXSYNCB;
5226 
input TXUSRCLK2A;
5227 
input TXUSRCLK2B;
5228 
input TXUSRCLKA;
5229 
input TXUSRCLKB;
5230 
endmodule
5231 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5232 
module GT11 (CHBONDO, COMBUSOUT, DO, DRDY, RXBUFERR, RXCALFAIL, RXCHARISCOMMA, RXCHARISK, RXCOMMADET, RXCRCOUT, RXCYCLELIMIT, RXDATA, RXDISPERR, RXLOCK, RXLOSSOFSYNC, RXMCLK, RXNOTINTABLE, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXRUNDISP, RXSIGDET, RXSTATUS, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCRCOUT, TXCYCLELIMIT, TXKERR, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT, TXRUNDISP, CHBONDI, COMBUSIN, DADDR, DCLK, DEN, DI, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK, LOOPBACK, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCDATAWIDTH, RXCRCIN, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXPMARESET, RXPOLARITY, RXRESET, RXSLIDE, RXSYNC, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCDATAWIDTH, TXCRCIN, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC, TXUSRCLK, TXUSRCLK2);
5233 
parameter BANDGAPSEL = "FALSE";
5234 
parameter BIASRESSEL = "FALSE";
5235 
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
5236 
parameter CHAN_BOND_MODE = "NONE";
5237 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
5238 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
5239 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
5240 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
5241 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
5242 
parameter CHAN_BOND_SEQ_1_MASK = 4'b1110;
5243 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
5244 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
5245 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
5246 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
5247 
parameter CHAN_BOND_SEQ_2_MASK = 4'b1110;
5248 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
5249 
parameter CLK_CORRECT_USE = "FALSE";
5250 
parameter CLK_COR_8B10B_DE = "FALSE";
5251 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
5252 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
5253 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
5254 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
5255 
parameter CLK_COR_SEQ_1_MASK = 4'b1110;
5256 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
5257 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
5258 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
5259 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
5260 
parameter CLK_COR_SEQ_2_MASK = 4'b1110;
5261 
parameter CLK_COR_SEQ_2_USE = "FALSE";
5262 
parameter CLK_COR_SEQ_DROP = "FALSE";
5263 
parameter COMMA32 = "FALSE";
5264 
parameter COMMA_10B_MASK = 10'h3FF;
5265 
parameter CYCLE_LIMIT_SEL = 2'b00;
5266 
parameter DCDR_FILTER = 3'b010;
5267 
parameter DEC_MCOMMA_DETECT = "TRUE";
5268 
parameter DEC_PCOMMA_DETECT = "TRUE";
5269 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
5270 
parameter DIGRX_FWDCLK = 2'b00;
5271 
parameter DIGRX_SYNC_MODE = "FALSE";
5272 
parameter ENABLE_DCDR = "FALSE";
5273 
parameter FDET_HYS_CAL = 3'b010;
5274 
parameter FDET_HYS_SEL = 3'b100;
5275 
parameter FDET_LCK_CAL = 3'b100;
5276 
parameter FDET_LCK_SEL = 3'b001;
5277 
parameter GT11_MODE = "DONT_CARE";
5278 
parameter IREFBIASMODE = 2'b11;
5279 
parameter LOOPCAL_WAIT = 2'b00;
5280 
parameter MCOMMA_32B_VALUE = 32'h00000000;
5281 
parameter MCOMMA_DETECT = "TRUE";
5282 
parameter OPPOSITE_SELECT = "FALSE";
5283 
parameter PCOMMA_32B_VALUE = 32'h00000000;
5284 
parameter PCOMMA_DETECT = "TRUE";
5285 
parameter PCS_BIT_SLIP = "FALSE";
5286 
parameter PMACLKENABLE = "TRUE";
5287 
parameter PMACOREPWRENABLE = "TRUE";
5288 
parameter PMAIREFTRIM = 4'b0111;
5289 
parameter PMAVBGCTRL = 5'b00000;
5290 
parameter PMAVREFTRIM = 4'b0111;
5291 
parameter PMA_BIT_SLIP = "FALSE";
5292 
parameter POWER_ENABLE = "TRUE";
5293 
parameter REPEATER = "FALSE";
5294 
parameter RXACTST = "FALSE";
5295 
parameter RXAFEEQ = 9'b000000000;
5296 
parameter RXAFEPD = "FALSE";
5297 
parameter RXAFETST = "FALSE";
5298 
parameter RXAPD = "FALSE";
5299 
parameter RXAREGCTRL = 5'b00000;
5300 
parameter RXASYNCDIVIDE = 2'b11;
5301 
parameter RXBY_32 = "FALSE";
5302 
parameter RXCDRLOS = 6'b000000;
5303 
parameter RXCLK0_FORCE_PMACLK = "FALSE";
5304 
parameter RXCLKMODE = 6'b110001;
5305 
parameter RXCLMODE = 2'b00;
5306 
parameter RXCMADJ = 2'b01;
5307 
parameter RXCPSEL = "TRUE";
5308 
parameter RXCPTST = "FALSE";
5309 
parameter RXCRCCLOCKDOUBLE = "FALSE";
5310 
parameter RXCRCENABLE = "FALSE";
5311 
parameter RXCRCINITVAL = 32'h00000000;
5312 
parameter RXCRCINVERTGEN = "FALSE";
5313 
parameter RXCRCSAMECLOCK = "FALSE";
5314 
parameter RXCTRL1 = 10'h200;
5315 
parameter RXCYCLE_LIMIT_SEL = 2'b00;
5316 
parameter RXDATA_SEL = 2'b00;
5317 
parameter RXDCCOUPLE = "FALSE";
5318 
parameter RXDIGRESET = "FALSE";
5319 
parameter RXDIGRX = "FALSE";
5320 
parameter RXEQ = 64'h4000000000000000;
5321 
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
5322 
parameter RXFDET_HYS_CAL = 3'b010;
5323 
parameter RXFDET_HYS_SEL = 3'b100;
5324 
parameter RXFDET_LCK_CAL = 3'b100;
5325 
parameter RXFDET_LCK_SEL = 3'b001;
5326 
parameter RXFECONTROL1 = 2'b00;
5327 
parameter RXFECONTROL2 = 3'b000;
5328 
parameter RXFETUNE = 2'b01;
5329 
parameter RXLB = "FALSE";
5330 
parameter RXLKADJ = 5'b00000;
5331 
parameter RXLKAPD = "FALSE";
5332 
parameter RXLOOPCAL_WAIT = 2'b00;
5333 
parameter RXLOOPFILT = 4'b0111;
5334 
parameter RXMODE = 6'b000000;
5335 
parameter RXPD = "FALSE";
5336 
parameter RXPDDTST = "TRUE";
5337 
parameter RXPMACLKSEL = "REFCLK1";
5338 
parameter RXRCPADJ = 3'b011;
5339 
parameter RXRCPPD = "FALSE";
5340 
parameter RXRECCLK1_USE_SYNC = "FALSE";
5341 
parameter RXRIBADJ = 2'b11;
5342 
parameter RXRPDPD = "FALSE";
5343 
parameter RXRSDPD = "FALSE";
5344 
parameter RXSLOWDOWN_CAL = 2'b00;
5345 
parameter RXTUNE = 13'h0000;
5346 
parameter RXVCODAC_INIT = 10'b1010000000;
5347 
parameter RXVCO_CTRL_ENABLE = "FALSE";
5348 
parameter RX_BUFFER_USE = "TRUE";
5349 
parameter RX_CLOCK_DIVIDER = 2'b00;
5350 
parameter SAMPLE_8X = "FALSE";
5351 
parameter SLOWDOWN_CAL = 2'b00;
5352 
parameter TXABPMACLKSEL = "REFCLK1";
5353 
parameter TXAPD = "FALSE";
5354 
parameter TXAREFBIASSEL = "TRUE";
5355 
parameter TXASYNCDIVIDE = 2'b11;
5356 
parameter TXCLK0_FORCE_PMACLK = "FALSE";
5357 
parameter TXCLKMODE = 4'b1001;
5358 
parameter TXCLMODE = 2'b00;
5359 
parameter TXCPSEL = "TRUE";
5360 
parameter TXCRCCLOCKDOUBLE = "FALSE";
5361 
parameter TXCRCENABLE = "FALSE";
5362 
parameter TXCRCINITVAL = 32'h00000000;
5363 
parameter TXCRCINVERTGEN = "FALSE";
5364 
parameter TXCRCSAMECLOCK = "FALSE";
5365 
parameter TXCTRL1 = 10'h200;
5366 
parameter TXDATA_SEL = 2'b00;
5367 
parameter TXDAT_PRDRV_DAC = 3'b111;
5368 
parameter TXDAT_TAP_DAC = 5'b10110;
5369 
parameter TXDIGPD = "FALSE";
5370 
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
5371 
parameter TXHIGHSIGNALEN = "TRUE";
5372 
parameter TXLOOPFILT = 4'b0111;
5373 
parameter TXLVLSHFTPD = "FALSE";
5374 
parameter TXOUTCLK1_USE_SYNC = "FALSE";
5375 
parameter TXPD = "FALSE";
5376 
parameter TXPHASESEL = "FALSE";
5377 
parameter TXPOST_PRDRV_DAC = 3'b111;
5378 
parameter TXPOST_TAP_DAC = 5'b01110;
5379 
parameter TXPOST_TAP_PD = "TRUE";
5380 
parameter TXPRE_PRDRV_DAC = 3'b111;
5381 
parameter TXPRE_TAP_DAC = 5'b00000;
5382 
parameter TXPRE_TAP_PD = "TRUE";
5383 
parameter TXSLEWRATE = "FALSE";
5384 
parameter TXTERMTRIM = 4'b1100;
5385 
parameter TXTUNE = 13'h0000;
5386 
parameter TX_BUFFER_USE = "TRUE";
5387 
parameter TX_CLOCK_DIVIDER = 2'b00;
5388 
parameter VCODAC_INIT = 10'b1010000000;
5389 
parameter VCO_CTRL_ENABLE = "FALSE";
5390 
parameter VREFBIASMODE = 2'b11;
5391 
parameter integer ALIGN_COMMA_WORD = 4;
5392 
parameter integer CHAN_BOND_LIMIT = 16;
5393 
parameter integer CHAN_BOND_SEQ_LEN = 1;
5394 
parameter integer CLK_COR_MAX_LAT = 48;
5395 
parameter integer CLK_COR_MIN_LAT = 36;
5396 
parameter integer CLK_COR_SEQ_LEN = 1;
5397 
parameter integer RXOUTDIV2SEL = 1;
5398 
parameter integer RXPLLNDIVSEL = 8;
5399 
parameter integer RXUSRDIVISOR = 1;
5400 
parameter integer SH_CNT_MAX = 64;
5401 
parameter integer SH_INVALID_CNT_MAX = 16;
5402 
parameter integer TXOUTDIV2SEL = 1;
5403 
parameter integer TXPLLNDIVSEL = 8;
5404 
output [4:0] CHBONDO;
5405 
output [15:0] COMBUSOUT;
5406 
output [15:0] DO;
5407 
output DRDY;
5408 
output RXBUFERR;
5409 
output RXCALFAIL;
5410 
output [7:0] RXCHARISCOMMA;
5411 
output [7:0] RXCHARISK;
5412 
output RXCOMMADET;
5413 
output [31:0] RXCRCOUT;
5414 
output RXCYCLELIMIT;
5415 
output [63:0] RXDATA;
5416 
output [7:0] RXDISPERR;
5417 
output RXLOCK;
5418 
output [1:0] RXLOSSOFSYNC;
5419 
output RXMCLK;
5420 
output [7:0] RXNOTINTABLE;
5421 
output RXPCSHCLKOUT;
5422 
output RXREALIGN;
5423 
output RXRECCLK1;
5424 
output RXRECCLK2;
5425 
output [7:0] RXRUNDISP;
5426 
output RXSIGDET;
5427 
output [5:0] RXSTATUS;
5428 
output TX1N;
5429 
output TX1P;
5430 
output TXBUFERR;
5431 
output TXCALFAIL;
5432 
output [31:0] TXCRCOUT;
5433 
output TXCYCLELIMIT;
5434 
output [7:0] TXKERR;
5435 
output TXLOCK;
5436 
output TXOUTCLK1;
5437 
output TXOUTCLK2;
5438 
output TXPCSHCLKOUT;
5439 
output [7:0] TXRUNDISP;
5440 
input [4:0] CHBONDI;
5441 
input [15:0] COMBUSIN;
5442 
input [7:0] DADDR;
5443 
input DCLK;
5444 
input DEN;
5445 
input [15:0] DI;
5446 
input DWE;
5447 
input ENCHANSYNC;
5448 
input ENMCOMMAALIGN;
5449 
input ENPCOMMAALIGN;
5450 
input GREFCLK;
5451 
input [1:0] LOOPBACK;
5452 
input POWERDOWN;
5453 
input REFCLK1;
5454 
input REFCLK2;
5455 
input RX1N;
5456 
input RX1P;
5457 
input RXBLOCKSYNC64B66BUSE;
5458 
input RXCLKSTABLE;
5459 
input RXCOMMADETUSE;
5460 
input RXCRCCLK;
5461 
input RXCRCDATAVALID;
5462 
input [2:0] RXCRCDATAWIDTH;
5463 
input [63:0] RXCRCIN;
5464 
input RXCRCINIT;
5465 
input RXCRCINTCLK;
5466 
input RXCRCPD;
5467 
input RXCRCRESET;
5468 
input [1:0] RXDATAWIDTH;
5469 
input RXDEC64B66BUSE;
5470 
input RXDEC8B10BUSE;
5471 
input RXDESCRAM64B66BUSE;
5472 
input RXIGNOREBTF;
5473 
input [1:0] RXINTDATAWIDTH;
5474 
input RXPMARESET;
5475 
input RXPOLARITY;
5476 
input RXRESET;
5477 
input RXSLIDE;
5478 
input RXSYNC;
5479 
input RXUSRCLK;
5480 
input RXUSRCLK2;
5481 
input [7:0] TXBYPASS8B10B;
5482 
input [7:0] TXCHARDISPMODE;
5483 
input [7:0] TXCHARDISPVAL;
5484 
input [7:0] TXCHARISK;
5485 
input TXCLKSTABLE;
5486 
input TXCRCCLK;
5487 
input TXCRCDATAVALID;
5488 
input [2:0] TXCRCDATAWIDTH;
5489 
input [63:0] TXCRCIN;
5490 
input TXCRCINIT;
5491 
input TXCRCINTCLK;
5492 
input TXCRCPD;
5493 
input TXCRCRESET;
5494 
input [63:0] TXDATA;
5495 
input [1:0] TXDATAWIDTH;
5496 
input TXENC64B66BUSE;
5497 
input TXENC8B10BUSE;
5498 
input TXENOOB;
5499 
input TXGEARBOX64B66BUSE;
5500 
input TXINHIBIT;
5501 
input [1:0] TXINTDATAWIDTH;
5502 
input TXPMARESET;
5503 
input TXPOLARITY;
5504 
input TXRESET;
5505 
input TXSCRAM64B66BUSE;
5506 
input TXSYNC;
5507 
input TXUSRCLK;
5508 
input TXUSRCLK2;
5509 
endmodule
5510 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5511 
module GT_AURORA_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5512 
parameter CHAN_BOND_MODE = "OFF";
5513 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
5514 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5515 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5516 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5517 
parameter integer REF_CLK_V_SEL = 0;
5518 
parameter RX_CRC_USE = "FALSE";
5519 
parameter integer RX_LOS_INVALID_INCR = 1;
5520 
parameter integer RX_LOS_THRESHOLD = 4;
5521 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5522 
parameter SERDES_10B = "FALSE";
5523 
parameter integer TERMINATION_IMP = 50;
5524 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5525 
parameter TX_CRC_USE = "FALSE";
5526 
parameter integer TX_DIFF_CTRL = 500;
5527 
parameter integer TX_PREEMPHASIS = 0;
5528 
output CHBONDDONE;
5529 
output [3:0] CHBONDO;
5530 
output CONFIGOUT;
5531 
output [1:0] RXBUFSTATUS;
5532 
output [0:0] RXCHARISCOMMA;
5533 
output [0:0] RXCHARISK;
5534 
output RXCHECKINGCRC;
5535 
output [2:0] RXCLKCORCNT;
5536 
output RXCOMMADET;
5537 
output RXCRCERR;
5538 
output [7:0] RXDATA;
5539 
output [0:0] RXDISPERR;
5540 
output [1:0] RXLOSSOFSYNC;
5541 
output [0:0] RXNOTINTABLE;
5542 
output RXREALIGN;
5543 
output RXRECCLK;
5544 
output [0:0] RXRUNDISP;
5545 
output TXBUFERR;
5546 
output [0:0] TXKERR;
5547 
output TXN;
5548 
output TXP;
5549 
output [0:0] TXRUNDISP;
5550 
input BREFCLK;
5551 
input BREFCLK2;
5552 
input [3:0] CHBONDI;
5553 
input CONFIGENABLE;
5554 
input CONFIGIN;
5555 
input ENCHANSYNC;
5556 
input ENMCOMMAALIGN;
5557 
input ENPCOMMAALIGN;
5558 
input [1:0] LOOPBACK;
5559 
input POWERDOWN;
5560 
input REFCLK;
5561 
input REFCLK2;
5562 
input REFCLKSEL;
5563 
input RXN;
5564 
input RXP;
5565 
input RXPOLARITY;
5566 
input RXRESET;
5567 
input RXUSRCLK;
5568 
input RXUSRCLK2;
5569 
input [0:0] TXBYPASS8B10B;
5570 
input [0:0] TXCHARDISPMODE;
5571 
input [0:0] TXCHARDISPVAL;
5572 
input [0:0] TXCHARISK;
5573 
input [7:0] TXDATA;
5574 
input TXFORCECRCERR;
5575 
input TXINHIBIT;
5576 
input TXPOLARITY;
5577 
input TXRESET;
5578 
input TXUSRCLK;
5579 
input TXUSRCLK2;
5580 
endmodule
5581 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5582 
module GT_AURORA_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5583 
parameter CHAN_BOND_MODE = "OFF";
5584 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
5585 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5586 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5587 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5588 
parameter integer REF_CLK_V_SEL = 0;
5589 
parameter RX_CRC_USE = "FALSE";
5590 
parameter integer RX_LOS_INVALID_INCR = 1;
5591 
parameter integer RX_LOS_THRESHOLD = 4;
5592 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5593 
parameter SERDES_10B = "FALSE";
5594 
parameter integer TERMINATION_IMP = 50;
5595 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5596 
parameter TX_CRC_USE = "FALSE";
5597 
parameter integer TX_DIFF_CTRL = 500;
5598 
parameter integer TX_PREEMPHASIS = 0;
5599 
output CHBONDDONE;
5600 
output [3:0] CHBONDO;
5601 
output CONFIGOUT;
5602 
output [1:0] RXBUFSTATUS;
5603 
output [1:0] RXCHARISCOMMA;
5604 
output [1:0] RXCHARISK;
5605 
output RXCHECKINGCRC;
5606 
output [2:0] RXCLKCORCNT;
5607 
output RXCOMMADET;
5608 
output RXCRCERR;
5609 
output [15:0] RXDATA;
5610 
output [1:0] RXDISPERR;
5611 
output [1:0] RXLOSSOFSYNC;
5612 
output [1:0] RXNOTINTABLE;
5613 
output RXREALIGN;
5614 
output RXRECCLK;
5615 
output [1:0] RXRUNDISP;
5616 
output TXBUFERR;
5617 
output [1:0] TXKERR;
5618 
output TXN;
5619 
output TXP;
5620 
output [1:0] TXRUNDISP;
5621 
input BREFCLK;
5622 
input BREFCLK2;
5623 
input [3:0] CHBONDI;
5624 
input CONFIGENABLE;
5625 
input CONFIGIN;
5626 
input ENCHANSYNC;
5627 
input ENMCOMMAALIGN;
5628 
input ENPCOMMAALIGN;
5629 
input [1:0] LOOPBACK;
5630 
input POWERDOWN;
5631 
input REFCLK;
5632 
input REFCLK2;
5633 
input REFCLKSEL;
5634 
input RXN;
5635 
input RXP;
5636 
input RXPOLARITY;
5637 
input RXRESET;
5638 
input RXUSRCLK;
5639 
input RXUSRCLK2;
5640 
input [1:0] TXBYPASS8B10B;
5641 
input [1:0] TXCHARDISPMODE;
5642 
input [1:0] TXCHARDISPVAL;
5643 
input [1:0] TXCHARISK;
5644 
input [15:0] TXDATA;
5645 
input TXFORCECRCERR;
5646 
input TXINHIBIT;
5647 
input TXPOLARITY;
5648 
input TXRESET;
5649 
input TXUSRCLK;
5650 
input TXUSRCLK2;
5651 
endmodule
5652 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5653 
module GT_AURORA_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5654 
parameter CHAN_BOND_MODE = "OFF";
5655 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
5656 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5657 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5658 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5659 
parameter integer REF_CLK_V_SEL = 0;
5660 
parameter RX_CRC_USE = "FALSE";
5661 
parameter integer RX_LOS_INVALID_INCR = 1;
5662 
parameter integer RX_LOS_THRESHOLD = 4;
5663 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5664 
parameter SERDES_10B = "FALSE";
5665 
parameter integer TERMINATION_IMP = 50;
5666 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5667 
parameter TX_CRC_USE = "FALSE";
5668 
parameter integer TX_DIFF_CTRL = 500;
5669 
parameter integer TX_PREEMPHASIS = 0;
5670 
output CHBONDDONE;
5671 
output [3:0] CHBONDO;
5672 
output CONFIGOUT;
5673 
output [1:0] RXBUFSTATUS;
5674 
output [3:0] RXCHARISCOMMA;
5675 
output [3:0] RXCHARISK;
5676 
output RXCHECKINGCRC;
5677 
output [2:0] RXCLKCORCNT;
5678 
output RXCOMMADET;
5679 
output RXCRCERR;
5680 
output [31:0] RXDATA;
5681 
output [3:0] RXDISPERR;
5682 
output [1:0] RXLOSSOFSYNC;
5683 
output [3:0] RXNOTINTABLE;
5684 
output RXREALIGN;
5685 
output RXRECCLK;
5686 
output [3:0] RXRUNDISP;
5687 
output TXBUFERR;
5688 
output [3:0] TXKERR;
5689 
output TXN;
5690 
output TXP;
5691 
output [3:0] TXRUNDISP;
5692 
input BREFCLK;
5693 
input BREFCLK2;
5694 
input [3:0] CHBONDI;
5695 
input CONFIGENABLE;
5696 
input CONFIGIN;
5697 
input ENCHANSYNC;
5698 
input ENMCOMMAALIGN;
5699 
input ENPCOMMAALIGN;
5700 
input [1:0] LOOPBACK;
5701 
input POWERDOWN;
5702 
input REFCLK;
5703 
input REFCLK2;
5704 
input REFCLKSEL;
5705 
input RXN;
5706 
input RXP;
5707 
input RXPOLARITY;
5708 
input RXRESET;
5709 
input RXUSRCLK;
5710 
input RXUSRCLK2;
5711 
input [3:0] TXBYPASS8B10B;
5712 
input [3:0] TXCHARDISPMODE;
5713 
input [3:0] TXCHARDISPVAL;
5714 
input [3:0] TXCHARISK;
5715 
input [31:0] TXDATA;
5716 
input TXFORCECRCERR;
5717 
input TXINHIBIT;
5718 
input TXPOLARITY;
5719 
input TXRESET;
5720 
input TXUSRCLK;
5721 
input TXUSRCLK2;
5722 
endmodule
5723 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5724 
module GT_CUSTOM (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5725 
parameter ALIGN_COMMA_MSB = "FALSE";
5726 
parameter integer CHAN_BOND_LIMIT = 16;
5727 
parameter CHAN_BOND_MODE = "OFF";
5728 
parameter integer CHAN_BOND_OFFSET = 8;
5729 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
5730 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
5731 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
5732 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
5733 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
5734 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
5735 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
5736 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
5737 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
5738 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
5739 
parameter integer CHAN_BOND_SEQ_LEN = 1;
5740 
parameter integer CHAN_BOND_WAIT = 8;
5741 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5742 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5743 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5744 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
5745 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
5746 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
5747 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
5748 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
5749 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
5750 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
5751 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
5752 
parameter CLK_COR_SEQ_2_USE = "FALSE";
5753 
parameter integer CLK_COR_SEQ_LEN = 1;
5754 
parameter CLK_CORRECT_USE = "TRUE";
5755 
parameter COMMA_10B_MASK = 10'b1111111000;
5756 
parameter CRC_END_OF_PKT = "K29_7";
5757 
parameter CRC_FORMAT = "USER_MODE";
5758 
parameter CRC_START_OF_PKT = "K27_7";
5759 
parameter DEC_MCOMMA_DETECT = "TRUE";
5760 
parameter DEC_PCOMMA_DETECT = "TRUE";
5761 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
5762 
parameter MCOMMA_10B_VALUE = 10'b1100000000;
5763 
parameter MCOMMA_DETECT = "TRUE";
5764 
parameter PCOMMA_10B_VALUE = 10'b0011111000;
5765 
parameter PCOMMA_DETECT = "TRUE";
5766 
parameter integer REF_CLK_V_SEL = 0;
5767 
parameter RX_BUFFER_USE = "TRUE";
5768 
parameter RX_CRC_USE = "FALSE";
5769 
parameter integer RX_DATA_WIDTH = 2;
5770 
parameter RX_DECODE_USE = "TRUE";
5771 
parameter integer RX_LOS_INVALID_INCR = 1;
5772 
parameter integer RX_LOS_THRESHOLD = 4;
5773 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5774 
parameter SERDES_10B = "FALSE";
5775 
parameter integer TERMINATION_IMP = 50;
5776 
parameter TX_BUFFER_USE = "TRUE";
5777 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5778 
parameter TX_CRC_USE = "FALSE";
5779 
parameter integer TX_DATA_WIDTH = 2;
5780 
parameter integer TX_DIFF_CTRL = 500;
5781 
parameter integer TX_PREEMPHASIS = 0;
5782 
output CHBONDDONE;
5783 
output [3:0] CHBONDO;
5784 
output CONFIGOUT;
5785 
output [1:0] RXBUFSTATUS;
5786 
output [3:0] RXCHARISCOMMA;
5787 
output [3:0] RXCHARISK;
5788 
output RXCHECKINGCRC;
5789 
output [2:0] RXCLKCORCNT;
5790 
output RXCOMMADET;
5791 
output RXCRCERR;
5792 
output [31:0] RXDATA;
5793 
output [3:0] RXDISPERR;
5794 
output [1:0] RXLOSSOFSYNC;
5795 
output [3:0] RXNOTINTABLE;
5796 
output RXREALIGN;
5797 
output RXRECCLK;
5798 
output [3:0] RXRUNDISP;
5799 
output TXBUFERR;
5800 
output [3:0] TXKERR;
5801 
output TXN;
5802 
output TXP;
5803 
output [3:0] TXRUNDISP;
5804 
input BREFCLK;
5805 
input BREFCLK2;
5806 
input [3:0] CHBONDI;
5807 
input CONFIGENABLE;
5808 
input CONFIGIN;
5809 
input ENCHANSYNC;
5810 
input ENMCOMMAALIGN;
5811 
input ENPCOMMAALIGN;
5812 
input [1:0] LOOPBACK;
5813 
input POWERDOWN;
5814 
input REFCLK;
5815 
input REFCLK2;
5816 
input REFCLKSEL;
5817 
input RXN;
5818 
input RXP;
5819 
input RXPOLARITY;
5820 
input RXRESET;
5821 
input RXUSRCLK;
5822 
input RXUSRCLK2;
5823 
input [3:0] TXBYPASS8B10B;
5824 
input [3:0] TXCHARDISPMODE;
5825 
input [3:0] TXCHARDISPVAL;
5826 
input [3:0] TXCHARISK;
5827 
input [31:0] TXDATA;
5828 
input TXFORCECRCERR;
5829 
input TXINHIBIT;
5830 
input TXPOLARITY;
5831 
input TXRESET;
5832 
input TXUSRCLK;
5833 
input TXUSRCLK2;
5834 
endmodule
5835 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5836 
module GT_ETHERNET_1 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5837 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5838 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5839 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5840 
parameter integer REF_CLK_V_SEL = 0;
5841 
parameter RX_CRC_USE = "FALSE";
5842 
parameter integer RX_LOS_INVALID_INCR = 1;
5843 
parameter integer RX_LOS_THRESHOLD = 4;
5844 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5845 
parameter SERDES_10B = "FALSE";
5846 
parameter integer TERMINATION_IMP = 50;
5847 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5848 
parameter TX_CRC_USE = "FALSE";
5849 
parameter integer TX_DIFF_CTRL = 500;
5850 
parameter integer TX_PREEMPHASIS = 0;
5851 
output CONFIGOUT;
5852 
output [1:0] RXBUFSTATUS;
5853 
output [0:0] RXCHARISCOMMA;
5854 
output [0:0] RXCHARISK;
5855 
output RXCHECKINGCRC;
5856 
output [2:0] RXCLKCORCNT;
5857 
output RXCOMMADET;
5858 
output RXCRCERR;
5859 
output [7:0] RXDATA;
5860 
output [0:0] RXDISPERR;
5861 
output [1:0] RXLOSSOFSYNC;
5862 
output [0:0] RXNOTINTABLE;
5863 
output RXREALIGN;
5864 
output RXRECCLK;
5865 
output [0:0] RXRUNDISP;
5866 
output TXBUFERR;
5867 
output [0:0] TXKERR;
5868 
output TXN;
5869 
output TXP;
5870 
output [0:0] TXRUNDISP;
5871 
input BREFCLK;
5872 
input BREFCLK2;
5873 
input CONFIGENABLE;
5874 
input CONFIGIN;
5875 
input ENMCOMMAALIGN;
5876 
input ENPCOMMAALIGN;
5877 
input [1:0] LOOPBACK;
5878 
input POWERDOWN;
5879 
input REFCLK;
5880 
input REFCLK2;
5881 
input REFCLKSEL;
5882 
input RXN;
5883 
input RXP;
5884 
input RXPOLARITY;
5885 
input RXRESET;
5886 
input RXUSRCLK;
5887 
input RXUSRCLK2;
5888 
input [0:0] TXBYPASS8B10B;
5889 
input [0:0] TXCHARDISPMODE;
5890 
input [0:0] TXCHARDISPVAL;
5891 
input [0:0] TXCHARISK;
5892 
input [7:0] TXDATA;
5893 
input TXFORCECRCERR;
5894 
input TXINHIBIT;
5895 
input TXPOLARITY;
5896 
input TXRESET;
5897 
input TXUSRCLK;
5898 
input TXUSRCLK2;
5899 
endmodule
5900 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5901 
module GT_ETHERNET_2 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5902 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5903 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5904 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5905 
parameter integer REF_CLK_V_SEL = 0;
5906 
parameter RX_CRC_USE = "FALSE";
5907 
parameter integer RX_LOS_INVALID_INCR = 1;
5908 
parameter integer RX_LOS_THRESHOLD = 4;
5909 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5910 
parameter SERDES_10B = "FALSE";
5911 
parameter integer TERMINATION_IMP = 50;
5912 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5913 
parameter TX_CRC_USE = "FALSE";
5914 
parameter integer TX_DIFF_CTRL = 500;
5915 
parameter integer TX_PREEMPHASIS = 0;
5916 
output CONFIGOUT;
5917 
output [1:0] RXBUFSTATUS;
5918 
output [1:0] RXCHARISCOMMA;
5919 
output [1:0] RXCHARISK;
5920 
output RXCHECKINGCRC;
5921 
output [2:0] RXCLKCORCNT;
5922 
output RXCOMMADET;
5923 
output RXCRCERR;
5924 
output [15:0] RXDATA;
5925 
output [1:0] RXDISPERR;
5926 
output [1:0] RXLOSSOFSYNC;
5927 
output [1:0] RXNOTINTABLE;
5928 
output RXREALIGN;
5929 
output RXRECCLK;
5930 
output [1:0] RXRUNDISP;
5931 
output TXBUFERR;
5932 
output [1:0] TXKERR;
5933 
output TXN;
5934 
output TXP;
5935 
output [1:0] TXRUNDISP;
5936 
input BREFCLK;
5937 
input BREFCLK2;
5938 
input CONFIGENABLE;
5939 
input CONFIGIN;
5940 
input ENMCOMMAALIGN;
5941 
input ENPCOMMAALIGN;
5942 
input [1:0] LOOPBACK;
5943 
input POWERDOWN;
5944 
input REFCLK;
5945 
input REFCLK2;
5946 
input REFCLKSEL;
5947 
input RXN;
5948 
input RXP;
5949 
input RXPOLARITY;
5950 
input RXRESET;
5951 
input RXUSRCLK;
5952 
input RXUSRCLK2;
5953 
input [1:0] TXBYPASS8B10B;
5954 
input [1:0] TXCHARDISPMODE;
5955 
input [1:0] TXCHARDISPVAL;
5956 
input [1:0] TXCHARISK;
5957 
input [15:0] TXDATA;
5958 
input TXFORCECRCERR;
5959 
input TXINHIBIT;
5960 
input TXPOLARITY;
5961 
input TXRESET;
5962 
input TXUSRCLK;
5963 
input TXUSRCLK2;
5964 
endmodule
5965 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
5966 
module GT_ETHERNET_4 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
5967 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
5968 
parameter CLK_COR_KEEP_IDLE = "FALSE";
5969 
parameter integer CLK_COR_REPEAT_WAIT = 1;
5970 
parameter integer REF_CLK_V_SEL = 0;
5971 
parameter RX_CRC_USE = "FALSE";
5972 
parameter integer RX_LOS_INVALID_INCR = 1;
5973 
parameter integer RX_LOS_THRESHOLD = 4;
5974 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
5975 
parameter SERDES_10B = "FALSE";
5976 
parameter integer TERMINATION_IMP = 50;
5977 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
5978 
parameter TX_CRC_USE = "FALSE";
5979 
parameter integer TX_DIFF_CTRL = 500;
5980 
parameter integer TX_PREEMPHASIS = 0;
5981 
output CONFIGOUT;
5982 
output [1:0] RXBUFSTATUS;
5983 
output [3:0] RXCHARISCOMMA;
5984 
output [3:0] RXCHARISK;
5985 
output RXCHECKINGCRC;
5986 
output [2:0] RXCLKCORCNT;
5987 
output RXCOMMADET;
5988 
output RXCRCERR;
5989 
output [31:0] RXDATA;
5990 
output [3:0] RXDISPERR;
5991 
output [1:0] RXLOSSOFSYNC;
5992 
output [3:0] RXNOTINTABLE;
5993 
output RXREALIGN;
5994 
output RXRECCLK;
5995 
output [3:0] RXRUNDISP;
5996 
output TXBUFERR;
5997 
output [3:0] TXKERR;
5998 
output TXN;
5999 
output TXP;
6000 
output [3:0] TXRUNDISP;
6001 
input BREFCLK;
6002 
input BREFCLK2;
6003 
input CONFIGENABLE;
6004 
input CONFIGIN;
6005 
input ENMCOMMAALIGN;
6006 
input ENPCOMMAALIGN;
6007 
input [1:0] LOOPBACK;
6008 
input POWERDOWN;
6009 
input REFCLK;
6010 
input REFCLK2;
6011 
input REFCLKSEL;
6012 
input RXN;
6013 
input RXP;
6014 
input RXPOLARITY;
6015 
input RXRESET;
6016 
input RXUSRCLK;
6017 
input RXUSRCLK2;
6018 
input [3:0] TXBYPASS8B10B;
6019 
input [3:0] TXCHARDISPMODE;
6020 
input [3:0] TXCHARDISPVAL;
6021 
input [3:0] TXCHARISK;
6022 
input [31:0] TXDATA;
6023 
input TXFORCECRCERR;
6024 
input TXINHIBIT;
6025 
input TXPOLARITY;
6026 
input TXRESET;
6027 
input TXUSRCLK;
6028 
input TXUSRCLK2;
6029 
endmodule
6030 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6031 
module GT_FIBRE_CHAN_1 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6032 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6033 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6034 
parameter integer CLK_COR_REPEAT_WAIT = 2;
6035 
parameter integer REF_CLK_V_SEL = 0;
6036 
parameter RX_CRC_USE = "FALSE";
6037 
parameter integer RX_LOS_INVALID_INCR = 1;
6038 
parameter integer RX_LOS_THRESHOLD = 4;
6039 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6040 
parameter SERDES_10B = "FALSE";
6041 
parameter integer TERMINATION_IMP = 50;
6042 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6043 
parameter TX_CRC_USE = "FALSE";
6044 
parameter integer TX_DIFF_CTRL = 500;
6045 
parameter integer TX_PREEMPHASIS = 0;
6046 
output CONFIGOUT;
6047 
output [1:0] RXBUFSTATUS;
6048 
output [0:0] RXCHARISCOMMA;
6049 
output [0:0] RXCHARISK;
6050 
output RXCHECKINGCRC;
6051 
output [2:0] RXCLKCORCNT;
6052 
output RXCOMMADET;
6053 
output RXCRCERR;
6054 
output [7:0] RXDATA;
6055 
output [0:0] RXDISPERR;
6056 
output [1:0] RXLOSSOFSYNC;
6057 
output [0:0] RXNOTINTABLE;
6058 
output RXREALIGN;
6059 
output RXRECCLK;
6060 
output [0:0] RXRUNDISP;
6061 
output TXBUFERR;
6062 
output [0:0] TXKERR;
6063 
output TXN;
6064 
output TXP;
6065 
output [0:0] TXRUNDISP;
6066 
input BREFCLK;
6067 
input BREFCLK2;
6068 
input CONFIGENABLE;
6069 
input CONFIGIN;
6070 
input ENMCOMMAALIGN;
6071 
input ENPCOMMAALIGN;
6072 
input [1:0] LOOPBACK;
6073 
input POWERDOWN;
6074 
input REFCLK;
6075 
input REFCLK2;
6076 
input REFCLKSEL;
6077 
input RXN;
6078 
input RXP;
6079 
input RXPOLARITY;
6080 
input RXRESET;
6081 
input RXUSRCLK;
6082 
input RXUSRCLK2;
6083 
input [0:0] TXBYPASS8B10B;
6084 
input [0:0] TXCHARDISPMODE;
6085 
input [0:0] TXCHARDISPVAL;
6086 
input [0:0] TXCHARISK;
6087 
input [7:0] TXDATA;
6088 
input TXFORCECRCERR;
6089 
input TXINHIBIT;
6090 
input TXPOLARITY;
6091 
input TXRESET;
6092 
input TXUSRCLK;
6093 
input TXUSRCLK2;
6094 
endmodule
6095 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6096 
module GT_FIBRE_CHAN_2 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6097 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6098 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6099 
parameter integer CLK_COR_REPEAT_WAIT = 2;
6100 
parameter integer REF_CLK_V_SEL = 0;
6101 
parameter RX_CRC_USE = "FALSE";
6102 
parameter integer RX_LOS_INVALID_INCR = 1;
6103 
parameter integer RX_LOS_THRESHOLD = 4;
6104 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6105 
parameter SERDES_10B = "FALSE";
6106 
parameter integer TERMINATION_IMP = 50;
6107 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6108 
parameter TX_CRC_USE = "FALSE";
6109 
parameter integer TX_DIFF_CTRL = 500;
6110 
parameter integer TX_PREEMPHASIS = 0;
6111 
output CONFIGOUT;
6112 
output [1:0] RXBUFSTATUS;
6113 
output [1:0] RXCHARISCOMMA;
6114 
output [1:0] RXCHARISK;
6115 
output RXCHECKINGCRC;
6116 
output [2:0] RXCLKCORCNT;
6117 
output RXCOMMADET;
6118 
output RXCRCERR;
6119 
output [15:0] RXDATA;
6120 
output [1:0] RXDISPERR;
6121 
output [1:0] RXLOSSOFSYNC;
6122 
output [1:0] RXNOTINTABLE;
6123 
output RXREALIGN;
6124 
output RXRECCLK;
6125 
output [1:0] RXRUNDISP;
6126 
output TXBUFERR;
6127 
output [1:0] TXKERR;
6128 
output TXN;
6129 
output TXP;
6130 
output [1:0] TXRUNDISP;
6131 
input BREFCLK;
6132 
input BREFCLK2;
6133 
input CONFIGENABLE;
6134 
input CONFIGIN;
6135 
input ENMCOMMAALIGN;
6136 
input ENPCOMMAALIGN;
6137 
input [1:0] LOOPBACK;
6138 
input POWERDOWN;
6139 
input REFCLK;
6140 
input REFCLK2;
6141 
input REFCLKSEL;
6142 
input RXN;
6143 
input RXP;
6144 
input RXPOLARITY;
6145 
input RXRESET;
6146 
input RXUSRCLK;
6147 
input RXUSRCLK2;
6148 
input [1:0] TXBYPASS8B10B;
6149 
input [1:0] TXCHARDISPMODE;
6150 
input [1:0] TXCHARDISPVAL;
6151 
input [1:0] TXCHARISK;
6152 
input [15:0] TXDATA;
6153 
input TXFORCECRCERR;
6154 
input TXINHIBIT;
6155 
input TXPOLARITY;
6156 
input TXRESET;
6157 
input TXUSRCLK;
6158 
input TXUSRCLK2;
6159 
endmodule
6160 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6161 
module GT_FIBRE_CHAN_4 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6162 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6163 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6164 
parameter integer CLK_COR_REPEAT_WAIT = 2;
6165 
parameter integer REF_CLK_V_SEL = 0;
6166 
parameter RX_CRC_USE = "FALSE";
6167 
parameter integer RX_LOS_INVALID_INCR = 1;
6168 
parameter integer RX_LOS_THRESHOLD = 4;
6169 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6170 
parameter SERDES_10B = "FALSE";
6171 
parameter integer TERMINATION_IMP = 50;
6172 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6173 
parameter TX_CRC_USE = "FALSE";
6174 
parameter integer TX_DIFF_CTRL = 500;
6175 
parameter integer TX_PREEMPHASIS = 0;
6176 
output CONFIGOUT;
6177 
output [1:0] RXBUFSTATUS;
6178 
output [3:0] RXCHARISCOMMA;
6179 
output [3:0] RXCHARISK;
6180 
output RXCHECKINGCRC;
6181 
output [2:0] RXCLKCORCNT;
6182 
output RXCOMMADET;
6183 
output RXCRCERR;
6184 
output [31:0] RXDATA;
6185 
output [3:0] RXDISPERR;
6186 
output [1:0] RXLOSSOFSYNC;
6187 
output [3:0] RXNOTINTABLE;
6188 
output RXREALIGN;
6189 
output RXRECCLK;
6190 
output [3:0] RXRUNDISP;
6191 
output TXBUFERR;
6192 
output [3:0] TXKERR;
6193 
output TXN;
6194 
output TXP;
6195 
output [3:0] TXRUNDISP;
6196 
input BREFCLK;
6197 
input BREFCLK2;
6198 
input CONFIGENABLE;
6199 
input CONFIGIN;
6200 
input ENMCOMMAALIGN;
6201 
input ENPCOMMAALIGN;
6202 
input [1:0] LOOPBACK;
6203 
input POWERDOWN;
6204 
input REFCLK;
6205 
input REFCLK2;
6206 
input REFCLKSEL;
6207 
input RXN;
6208 
input RXP;
6209 
input RXPOLARITY;
6210 
input RXRESET;
6211 
input RXUSRCLK;
6212 
input RXUSRCLK2;
6213 
input [3:0] TXBYPASS8B10B;
6214 
input [3:0] TXCHARDISPMODE;
6215 
input [3:0] TXCHARDISPVAL;
6216 
input [3:0] TXCHARISK;
6217 
input [31:0] TXDATA;
6218 
input TXFORCECRCERR;
6219 
input TXINHIBIT;
6220 
input TXPOLARITY;
6221 
input TXRESET;
6222 
input TXUSRCLK;
6223 
input TXUSRCLK2;
6224 
endmodule
6225 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6226 
module GT_INFINIBAND_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6227 
parameter CHAN_BOND_MODE = "OFF";
6228 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6229 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6230 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6231 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6232 
parameter LANE_ID = 11'b00000000000;
6233 
parameter integer REF_CLK_V_SEL = 0;
6234 
parameter RX_CRC_USE = "FALSE";
6235 
parameter integer RX_LOS_INVALID_INCR = 1;
6236 
parameter integer RX_LOS_THRESHOLD = 4;
6237 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6238 
parameter SERDES_10B = "FALSE";
6239 
parameter integer TERMINATION_IMP = 50;
6240 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6241 
parameter TX_CRC_USE = "FALSE";
6242 
parameter integer TX_DIFF_CTRL = 500;
6243 
parameter integer TX_PREEMPHASIS = 0;
6244 
output CHBONDDONE;
6245 
output [3:0] CHBONDO;
6246 
output CONFIGOUT;
6247 
output [1:0] RXBUFSTATUS;
6248 
output [0:0] RXCHARISCOMMA;
6249 
output [0:0] RXCHARISK;
6250 
output RXCHECKINGCRC;
6251 
output [2:0] RXCLKCORCNT;
6252 
output RXCOMMADET;
6253 
output RXCRCERR;
6254 
output [7:0] RXDATA;
6255 
output [0:0] RXDISPERR;
6256 
output [1:0] RXLOSSOFSYNC;
6257 
output [0:0] RXNOTINTABLE;
6258 
output RXREALIGN;
6259 
output RXRECCLK;
6260 
output [0:0] RXRUNDISP;
6261 
output TXBUFERR;
6262 
output [0:0] TXKERR;
6263 
output TXN;
6264 
output TXP;
6265 
output [0:0] TXRUNDISP;
6266 
input BREFCLK;
6267 
input BREFCLK2;
6268 
input [3:0] CHBONDI;
6269 
input CONFIGENABLE;
6270 
input CONFIGIN;
6271 
input ENCHANSYNC;
6272 
input ENMCOMMAALIGN;
6273 
input ENPCOMMAALIGN;
6274 
input [1:0] LOOPBACK;
6275 
input POWERDOWN;
6276 
input REFCLK;
6277 
input REFCLK2;
6278 
input REFCLKSEL;
6279 
input RXN;
6280 
input RXP;
6281 
input RXPOLARITY;
6282 
input RXRESET;
6283 
input RXUSRCLK;
6284 
input RXUSRCLK2;
6285 
input [0:0] TXBYPASS8B10B;
6286 
input [0:0] TXCHARDISPMODE;
6287 
input [0:0] TXCHARDISPVAL;
6288 
input [0:0] TXCHARISK;
6289 
input [7:0] TXDATA;
6290 
input TXFORCECRCERR;
6291 
input TXINHIBIT;
6292 
input TXPOLARITY;
6293 
input TXRESET;
6294 
input TXUSRCLK;
6295 
input TXUSRCLK2;
6296 
endmodule
6297 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6298 
module GT_INFINIBAND_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6299 
parameter CHAN_BOND_MODE = "OFF";
6300 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6301 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6302 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6303 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6304 
parameter LANE_ID = 11'b00000000000;
6305 
parameter integer REF_CLK_V_SEL = 0;
6306 
parameter RX_CRC_USE = "FALSE";
6307 
parameter integer RX_LOS_INVALID_INCR = 1;
6308 
parameter integer RX_LOS_THRESHOLD = 4;
6309 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6310 
parameter SERDES_10B = "FALSE";
6311 
parameter integer TERMINATION_IMP = 50;
6312 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6313 
parameter TX_CRC_USE = "FALSE";
6314 
parameter integer TX_DIFF_CTRL = 500;
6315 
parameter integer TX_PREEMPHASIS = 0;
6316 
output CHBONDDONE;
6317 
output [3:0] CHBONDO;
6318 
output CONFIGOUT;
6319 
output [1:0] RXBUFSTATUS;
6320 
output [1:0] RXCHARISCOMMA;
6321 
output [1:0] RXCHARISK;
6322 
output RXCHECKINGCRC;
6323 
output [2:0] RXCLKCORCNT;
6324 
output RXCOMMADET;
6325 
output RXCRCERR;
6326 
output [15:0] RXDATA;
6327 
output [1:0] RXDISPERR;
6328 
output [1:0] RXLOSSOFSYNC;
6329 
output [1:0] RXNOTINTABLE;
6330 
output RXREALIGN;
6331 
output RXRECCLK;
6332 
output [1:0] RXRUNDISP;
6333 
output TXBUFERR;
6334 
output [1:0] TXKERR;
6335 
output TXN;
6336 
output TXP;
6337 
output [1:0] TXRUNDISP;
6338 
input BREFCLK;
6339 
input BREFCLK2;
6340 
input [3:0] CHBONDI;
6341 
input CONFIGENABLE;
6342 
input CONFIGIN;
6343 
input ENCHANSYNC;
6344 
input ENMCOMMAALIGN;
6345 
input ENPCOMMAALIGN;
6346 
input [1:0] LOOPBACK;
6347 
input POWERDOWN;
6348 
input REFCLK;
6349 
input REFCLK2;
6350 
input REFCLKSEL;
6351 
input RXN;
6352 
input RXP;
6353 
input RXPOLARITY;
6354 
input RXRESET;
6355 
input RXUSRCLK;
6356 
input RXUSRCLK2;
6357 
input [1:0] TXBYPASS8B10B;
6358 
input [1:0] TXCHARDISPMODE;
6359 
input [1:0] TXCHARDISPVAL;
6360 
input [1:0] TXCHARISK;
6361 
input [15:0] TXDATA;
6362 
input TXFORCECRCERR;
6363 
input TXINHIBIT;
6364 
input TXPOLARITY;
6365 
input TXRESET;
6366 
input TXUSRCLK;
6367 
input TXUSRCLK2;
6368 
endmodule
6369 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6370 
module GT_INFINIBAND_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6371 
parameter CHAN_BOND_MODE = "OFF";
6372 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6373 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6374 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6375 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6376 
parameter LANE_ID = 11'b00000000000;
6377 
parameter integer REF_CLK_V_SEL = 0;
6378 
parameter RX_CRC_USE = "FALSE";
6379 
parameter integer RX_LOS_INVALID_INCR = 1;
6380 
parameter integer RX_LOS_THRESHOLD = 4;
6381 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6382 
parameter SERDES_10B = "FALSE";
6383 
parameter integer TERMINATION_IMP = 50;
6384 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6385 
parameter TX_CRC_USE = "FALSE";
6386 
parameter integer TX_DIFF_CTRL = 500;
6387 
parameter integer TX_PREEMPHASIS = 0;
6388 
output CHBONDDONE;
6389 
output [3:0] CHBONDO;
6390 
output CONFIGOUT;
6391 
output [1:0] RXBUFSTATUS;
6392 
output [3:0] RXCHARISCOMMA;
6393 
output [3:0] RXCHARISK;
6394 
output RXCHECKINGCRC;
6395 
output [2:0] RXCLKCORCNT;
6396 
output RXCOMMADET;
6397 
output RXCRCERR;
6398 
output [31:0] RXDATA;
6399 
output [3:0] RXDISPERR;
6400 
output [1:0] RXLOSSOFSYNC;
6401 
output [3:0] RXNOTINTABLE;
6402 
output RXREALIGN;
6403 
output RXRECCLK;
6404 
output [3:0] RXRUNDISP;
6405 
output TXBUFERR;
6406 
output [3:0] TXKERR;
6407 
output TXN;
6408 
output TXP;
6409 
output [3:0] TXRUNDISP;
6410 
input BREFCLK;
6411 
input BREFCLK2;
6412 
input [3:0] CHBONDI;
6413 
input CONFIGENABLE;
6414 
input CONFIGIN;
6415 
input ENCHANSYNC;
6416 
input ENMCOMMAALIGN;
6417 
input ENPCOMMAALIGN;
6418 
input [1:0] LOOPBACK;
6419 
input POWERDOWN;
6420 
input REFCLK;
6421 
input REFCLK2;
6422 
input REFCLKSEL;
6423 
input RXN;
6424 
input RXP;
6425 
input RXPOLARITY;
6426 
input RXRESET;
6427 
input RXUSRCLK;
6428 
input RXUSRCLK2;
6429 
input [3:0] TXBYPASS8B10B;
6430 
input [3:0] TXCHARDISPMODE;
6431 
input [3:0] TXCHARDISPVAL;
6432 
input [3:0] TXCHARISK;
6433 
input [31:0] TXDATA;
6434 
input TXFORCECRCERR;
6435 
input TXINHIBIT;
6436 
input TXPOLARITY;
6437 
input TXRESET;
6438 
input TXUSRCLK;
6439 
input TXUSRCLK2;
6440 
endmodule
6441 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6442 
module GTP_DUAL (DO, DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBUFSTATUS0, RXBUFSTATUS1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXCOMMADET0, RXCOMMADET1, RXDATA0, RXDATA1, RXDISPERR0, RXDISPERR1, RXELECIDLE0, RXELECIDLE1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXRUNDISP0, RXRUNDISP1, RXSTATUS0, RXSTATUS1, RXVALID0, RXVALID1, TXBUFSTATUS0, TXBUFSTATUS1, TXKERR0, TXKERR1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, TXRUNDISP0, TXRUNDISP1, CLKIN, DADDR, DCLK, DEN, DI, DWE, GTPRESET, GTPTEST, INTDATAWIDTH, LOOPBACK0, LOOPBACK1, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDI0, RXCHBONDI1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXELECIDLERESET0, RXELECIDLERESET1, RXENCHANSYNC0, RXENCHANSYNC1, RXENELECIDLERESETB, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPRBSTST0, RXENPRBSTST1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXEQMIX0, RXEQMIX1, RXEQPOLE0, RXEQPOLE1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXPOWERDOWN0, RXPOWERDOWN1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATA0, TXDATA1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXDIFFCTRL0, TXDIFFCTRL1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN, TXENPRBSTST0, TXENPRBSTST1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE, TXPOLARITY0, TXPOLARITY1, TXPOWERDOWN0, TXPOWERDOWN1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21);
6443 
parameter AC_CAP_DIS_0 = "TRUE";
6444 
parameter AC_CAP_DIS_1 = "TRUE";
6445 
parameter CHAN_BOND_MODE_0 = "OFF";
6446 
parameter CHAN_BOND_MODE_1 = "OFF";
6447 
parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE";
6448 
parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE";
6449 
parameter CLKINDC_B = "TRUE";
6450 
parameter CLK_CORRECT_USE_0 = "TRUE";
6451 
parameter CLK_CORRECT_USE_1 = "TRUE";
6452 
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
6453 
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
6454 
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
6455 
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
6456 
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
6457 
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
6458 
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
6459 
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
6460 
parameter COMMA_DOUBLE_0 = "FALSE";
6461 
parameter COMMA_DOUBLE_1 = "FALSE";
6462 
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
6463 
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
6464 
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
6465 
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
6466 
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
6467 
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
6468 
parameter MCOMMA_DETECT_0 = "TRUE";
6469 
parameter MCOMMA_DETECT_1 = "TRUE";
6470 
parameter OVERSAMPLE_MODE = "FALSE";
6471 
parameter PCI_EXPRESS_MODE_0 = "TRUE";
6472 
parameter PCI_EXPRESS_MODE_1 = "TRUE";
6473 
parameter PCOMMA_DETECT_0 = "TRUE";
6474 
parameter PCOMMA_DETECT_1 = "TRUE";
6475 
parameter PLL_SATA_0 = "FALSE";
6476 
parameter PLL_SATA_1 = "FALSE";
6477 
parameter RCV_TERM_GND_0 = "TRUE";
6478 
parameter RCV_TERM_GND_1 = "TRUE";
6479 
parameter RCV_TERM_MID_0 = "FALSE";
6480 
parameter RCV_TERM_MID_1 = "FALSE";
6481 
parameter RCV_TERM_VTTRX_0 = "FALSE";
6482 
parameter RCV_TERM_VTTRX_1 = "FALSE";
6483 
parameter RX_BUFFER_USE_0 = "TRUE";
6484 
parameter RX_BUFFER_USE_1 = "TRUE";
6485 
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
6486 
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
6487 
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
6488 
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
6489 
parameter RX_SLIDE_MODE_0 = "PCS";
6490 
parameter RX_SLIDE_MODE_1 = "PCS";
6491 
parameter RX_STATUS_FMT_0 = "PCIE";
6492 
parameter RX_STATUS_FMT_1 = "PCIE";
6493 
parameter RX_XCLK_SEL_0 = "RXREC";
6494 
parameter RX_XCLK_SEL_1 = "RXREC";
6495 
parameter SIM_MODE = "FAST";
6496 
parameter SIM_PLL_PERDIV2 = 9'h190;
6497 
parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE";
6498 
parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE";
6499 
parameter TERMINATION_OVRD = "FALSE";
6500 
parameter TX_BUFFER_USE_0 = "TRUE";
6501 
parameter TX_BUFFER_USE_1 = "TRUE";
6502 
parameter TX_DIFF_BOOST_0 = "TRUE";
6503 
parameter TX_DIFF_BOOST_1 = "TRUE";
6504 
parameter TX_XCLK_SEL_0 = "TXUSR";
6505 
parameter TX_XCLK_SEL_1 = "TXUSR";
6506 
parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c;
6507 
parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c;
6508 
parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019;
6509 
parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019;
6510 
parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064;
6511 
parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064;
6512 
parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089;
6513 
parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089;
6514 
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640;
6515 
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640;
6516 
parameter [27:0] PCS_COM_CFG = 28'h1680a0e;
6517 
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001;
6518 
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001;
6519 
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
6520 
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
6521 
parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
6522 
parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
6523 
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1;
6524 
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1;
6525 
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
6526 
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
6527 
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
6528 
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
6529 
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
6530 
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
6531 
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
6532 
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
6533 
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
6534 
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
6535 
parameter [4:0] TERMINATION_CTRL = 5'b10100;
6536 
parameter [4:0] TXRX_INVERT_0 = 5'b00000;
6537 
parameter [4:0] TXRX_INVERT_1 = 5'b00000;
6538 
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010;
6539 
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010;
6540 
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
6541 
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
6542 
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
6543 
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
6544 
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
6545 
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
6546 
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
6547 
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
6548 
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
6549 
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
6550 
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
6551 
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
6552 
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
6553 
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
6554 
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
6555 
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
6556 
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0;
6557 
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0;
6558 
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0;
6559 
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0;
6560 
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0;
6561 
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0;
6562 
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0;
6563 
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0;
6564 
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0;
6565 
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0;
6566 
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0;
6567 
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0;
6568 
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0;
6569 
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0;
6570 
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
6571 
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
6572 
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
6573 
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
6574 
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
6575 
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
6576 
parameter integer ALIGN_COMMA_WORD_0 = 1;
6577 
parameter integer ALIGN_COMMA_WORD_1 = 1;
6578 
parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
6579 
parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
6580 
parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1;
6581 
parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1;
6582 
parameter integer CHAN_BOND_LEVEL_0 = 0;
6583 
parameter integer CHAN_BOND_LEVEL_1 = 0;
6584 
parameter integer CHAN_BOND_SEQ_LEN_0 = 4;
6585 
parameter integer CHAN_BOND_SEQ_LEN_1 = 4;
6586 
parameter integer CLK25_DIVIDER = 4;
6587 
parameter integer CLK_COR_ADJ_LEN_0 = 1;
6588 
parameter integer CLK_COR_ADJ_LEN_1 = 1;
6589 
parameter integer CLK_COR_DET_LEN_0 = 1;
6590 
parameter integer CLK_COR_DET_LEN_1 = 1;
6591 
parameter integer CLK_COR_MAX_LAT_0 = 18;
6592 
parameter integer CLK_COR_MAX_LAT_1 = 18;
6593 
parameter integer CLK_COR_MIN_LAT_0 = 16;
6594 
parameter integer CLK_COR_MIN_LAT_1 = 16;
6595 
parameter integer CLK_COR_REPEAT_WAIT_0 = 5;
6596 
parameter integer CLK_COR_REPEAT_WAIT_1 = 5;
6597 
parameter integer OOB_CLK_DIVIDER = 4;
6598 
parameter integer PLL_DIVSEL_FB = 5;
6599 
parameter integer PLL_DIVSEL_REF = 2;
6600 
parameter integer PLL_RXDIVSEL_OUT_0 = 1;
6601 
parameter integer PLL_RXDIVSEL_OUT_1 = 1;
6602 
parameter integer PLL_TXDIVSEL_COMM_OUT = 1;
6603 
parameter integer PLL_TXDIVSEL_OUT_0 = 1;
6604 
parameter integer PLL_TXDIVSEL_OUT_1 = 1;
6605 
parameter integer RX_LOS_INVALID_INCR_0 = 8;
6606 
parameter integer RX_LOS_INVALID_INCR_1 = 8;
6607 
parameter integer RX_LOS_THRESHOLD_0 = 128;
6608 
parameter integer RX_LOS_THRESHOLD_1 = 128;
6609 
parameter integer SATA_MAX_BURST_0 = 7;
6610 
parameter integer SATA_MAX_BURST_1 = 7;
6611 
parameter integer SATA_MAX_INIT_0 = 22;
6612 
parameter integer SATA_MAX_INIT_1 = 22;
6613 
parameter integer SATA_MAX_WAKE_0 = 7;
6614 
parameter integer SATA_MAX_WAKE_1 = 7;
6615 
parameter integer SATA_MIN_BURST_0 = 4;
6616 
parameter integer SATA_MIN_BURST_1 = 4;
6617 
parameter integer SATA_MIN_INIT_0 = 12;
6618 
parameter integer SATA_MIN_INIT_1 = 12;
6619 
parameter integer SATA_MIN_WAKE_0 = 4;
6620 
parameter integer SATA_MIN_WAKE_1 = 4;
6621 
parameter integer SIM_GTPRESET_SPEEDUP = 0;
6622 
parameter integer TERMINATION_IMP_0 = 50;
6623 
parameter integer TERMINATION_IMP_1 = 50;
6624 
parameter integer TX_SYNC_FILTERB = 1;
6625 
output [15:0] DO;
6626 
output DRDY;
6627 
output PHYSTATUS0;
6628 
output PHYSTATUS1;
6629 
output PLLLKDET;
6630 
output REFCLKOUT;
6631 
output RESETDONE0;
6632 
output RESETDONE1;
6633 
output [2:0] RXBUFSTATUS0;
6634 
output [2:0] RXBUFSTATUS1;
6635 
output RXBYTEISALIGNED0;
6636 
output RXBYTEISALIGNED1;
6637 
output RXBYTEREALIGN0;
6638 
output RXBYTEREALIGN1;
6639 
output RXCHANBONDSEQ0;
6640 
output RXCHANBONDSEQ1;
6641 
output RXCHANISALIGNED0;
6642 
output RXCHANISALIGNED1;
6643 
output RXCHANREALIGN0;
6644 
output RXCHANREALIGN1;
6645 
output [1:0] RXCHARISCOMMA0;
6646 
output [1:0] RXCHARISCOMMA1;
6647 
output [1:0] RXCHARISK0;
6648 
output [1:0] RXCHARISK1;
6649 
output [2:0] RXCHBONDO0;
6650 
output [2:0] RXCHBONDO1;
6651 
output [2:0] RXCLKCORCNT0;
6652 
output [2:0] RXCLKCORCNT1;
6653 
output RXCOMMADET0;
6654 
output RXCOMMADET1;
6655 
output [15:0] RXDATA0;
6656 
output [15:0] RXDATA1;
6657 
output [1:0] RXDISPERR0;
6658 
output [1:0] RXDISPERR1;
6659 
output RXELECIDLE0;
6660 
output RXELECIDLE1;
6661 
output [1:0] RXLOSSOFSYNC0;
6662 
output [1:0] RXLOSSOFSYNC1;
6663 
output [1:0] RXNOTINTABLE0;
6664 
output [1:0] RXNOTINTABLE1;
6665 
output RXOVERSAMPLEERR0;
6666 
output RXOVERSAMPLEERR1;
6667 
output RXPRBSERR0;
6668 
output RXPRBSERR1;
6669 
output RXRECCLK0;
6670 
output RXRECCLK1;
6671 
output [1:0] RXRUNDISP0;
6672 
output [1:0] RXRUNDISP1;
6673 
output [2:0] RXSTATUS0;
6674 
output [2:0] RXSTATUS1;
6675 
output RXVALID0;
6676 
output RXVALID1;
6677 
output [1:0] TXBUFSTATUS0;
6678 
output [1:0] TXBUFSTATUS1;
6679 
output [1:0] TXKERR0;
6680 
output [1:0] TXKERR1;
6681 
output TXN0;
6682 
output TXN1;
6683 
output TXOUTCLK0;
6684 
output TXOUTCLK1;
6685 
output TXP0;
6686 
output TXP1;
6687 
output [1:0] TXRUNDISP0;
6688 
output [1:0] TXRUNDISP1;
6689 
input CLKIN;
6690 
input [6:0] DADDR;
6691 
input DCLK;
6692 
input DEN;
6693 
input [15:0] DI;
6694 
input DWE;
6695 
input GTPRESET;
6696 
input [3:0] GTPTEST;
6697 
input INTDATAWIDTH;
6698 
input [2:0] LOOPBACK0;
6699 
input [2:0] LOOPBACK1;
6700 
input PLLLKDETEN;
6701 
input PLLPOWERDOWN;
6702 
input PRBSCNTRESET0;
6703 
input PRBSCNTRESET1;
6704 
input REFCLKPWRDNB;
6705 
input RXBUFRESET0;
6706 
input RXBUFRESET1;
6707 
input RXCDRRESET0;
6708 
input RXCDRRESET1;
6709 
input [2:0] RXCHBONDI0;
6710 
input [2:0] RXCHBONDI1;
6711 
input RXCOMMADETUSE0;
6712 
input RXCOMMADETUSE1;
6713 
input RXDATAWIDTH0;
6714 
input RXDATAWIDTH1;
6715 
input RXDEC8B10BUSE0;
6716 
input RXDEC8B10BUSE1;
6717 
input RXELECIDLERESET0;
6718 
input RXELECIDLERESET1;
6719 
input RXENCHANSYNC0;
6720 
input RXENCHANSYNC1;
6721 
input RXENELECIDLERESETB;
6722 
input RXENEQB0;
6723 
input RXENEQB1;
6724 
input RXENMCOMMAALIGN0;
6725 
input RXENMCOMMAALIGN1;
6726 
input RXENPCOMMAALIGN0;
6727 
input RXENPCOMMAALIGN1;
6728 
input [1:0] RXENPRBSTST0;
6729 
input [1:0] RXENPRBSTST1;
6730 
input RXENSAMPLEALIGN0;
6731 
input RXENSAMPLEALIGN1;
6732 
input [1:0] RXEQMIX0;
6733 
input [1:0] RXEQMIX1;
6734 
input [3:0] RXEQPOLE0;
6735 
input [3:0] RXEQPOLE1;
6736 
input RXN0;
6737 
input RXN1;
6738 
input RXP0;
6739 
input RXP1;
6740 
input RXPMASETPHASE0;
6741 
input RXPMASETPHASE1;
6742 
input RXPOLARITY0;
6743 
input RXPOLARITY1;
6744 
input [1:0] RXPOWERDOWN0;
6745 
input [1:0] RXPOWERDOWN1;
6746 
input RXRESET0;
6747 
input RXRESET1;
6748 
input RXSLIDE0;
6749 
input RXSLIDE1;
6750 
input RXUSRCLK0;
6751 
input RXUSRCLK1;
6752 
input RXUSRCLK20;
6753 
input RXUSRCLK21;
6754 
input [2:0] TXBUFDIFFCTRL0;
6755 
input [2:0] TXBUFDIFFCTRL1;
6756 
input [1:0] TXBYPASS8B10B0;
6757 
input [1:0] TXBYPASS8B10B1;
6758 
input [1:0] TXCHARDISPMODE0;
6759 
input [1:0] TXCHARDISPMODE1;
6760 
input [1:0] TXCHARDISPVAL0;
6761 
input [1:0] TXCHARDISPVAL1;
6762 
input [1:0] TXCHARISK0;
6763 
input [1:0] TXCHARISK1;
6764 
input TXCOMSTART0;
6765 
input TXCOMSTART1;
6766 
input TXCOMTYPE0;
6767 
input TXCOMTYPE1;
6768 
input [15:0] TXDATA0;
6769 
input [15:0] TXDATA1;
6770 
input TXDATAWIDTH0;
6771 
input TXDATAWIDTH1;
6772 
input TXDETECTRX0;
6773 
input TXDETECTRX1;
6774 
input [2:0] TXDIFFCTRL0;
6775 
input [2:0] TXDIFFCTRL1;
6776 
input TXELECIDLE0;
6777 
input TXELECIDLE1;
6778 
input TXENC8B10BUSE0;
6779 
input TXENC8B10BUSE1;
6780 
input TXENPMAPHASEALIGN;
6781 
input [1:0] TXENPRBSTST0;
6782 
input [1:0] TXENPRBSTST1;
6783 
input TXINHIBIT0;
6784 
input TXINHIBIT1;
6785 
input TXPMASETPHASE;
6786 
input TXPOLARITY0;
6787 
input TXPOLARITY1;
6788 
input [1:0] TXPOWERDOWN0;
6789 
input [1:0] TXPOWERDOWN1;
6790 
input [2:0] TXPREEMPHASIS0;
6791 
input [2:0] TXPREEMPHASIS1;
6792 
input TXRESET0;
6793 
input TXRESET1;
6794 
input TXUSRCLK0;
6795 
input TXUSRCLK1;
6796 
input TXUSRCLK20;
6797 
input TXUSRCLK21;
6798 
endmodule
6799 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6800 
module GT (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6801 
parameter ALIGN_COMMA_MSB = "FALSE";
6802 
parameter integer CHAN_BOND_LIMIT = 16;
6803 
parameter CHAN_BOND_MODE = "OFF";
6804 
parameter integer CHAN_BOND_OFFSET = 8;
6805 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6806 
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
6807 
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
6808 
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
6809 
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
6810 
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
6811 
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
6812 
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
6813 
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
6814 
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
6815 
parameter integer CHAN_BOND_SEQ_LEN = 1;
6816 
parameter integer CHAN_BOND_WAIT = 8;
6817 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6818 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6819 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6820 
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
6821 
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
6822 
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
6823 
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
6824 
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
6825 
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
6826 
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
6827 
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
6828 
parameter CLK_COR_SEQ_2_USE = "FALSE";
6829 
parameter integer CLK_COR_SEQ_LEN = 1;
6830 
parameter CLK_CORRECT_USE = "TRUE";
6831 
parameter COMMA_10B_MASK = 10'b1111111000;
6832 
parameter CRC_END_OF_PKT = "K29_7";
6833 
parameter CRC_FORMAT = "USER_MODE";
6834 
parameter CRC_START_OF_PKT = "K27_7";
6835 
parameter DEC_MCOMMA_DETECT = "TRUE";
6836 
parameter DEC_PCOMMA_DETECT = "TRUE";
6837 
parameter DEC_VALID_COMMA_ONLY = "TRUE";
6838 
parameter MCOMMA_10B_VALUE = 10'b1100000000;
6839 
parameter MCOMMA_DETECT = "TRUE";
6840 
parameter PCOMMA_10B_VALUE = 10'b0011111000;
6841 
parameter PCOMMA_DETECT = "TRUE";
6842 
parameter integer REF_CLK_V_SEL = 0;
6843 
parameter RX_BUFFER_USE = "TRUE";
6844 
parameter RX_CRC_USE = "FALSE";
6845 
parameter integer RX_DATA_WIDTH = 2;
6846 
parameter RX_DECODE_USE = "TRUE";
6847 
parameter integer RX_LOS_INVALID_INCR = 1;
6848 
parameter integer RX_LOS_THRESHOLD = 4;
6849 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6850 
parameter SERDES_10B = "FALSE";
6851 
parameter integer TERMINATION_IMP = 50;
6852 
parameter TX_BUFFER_USE = "TRUE";
6853 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6854 
parameter TX_CRC_USE = "FALSE";
6855 
parameter integer TX_DATA_WIDTH = 2;
6856 
parameter integer TX_DIFF_CTRL = 500;
6857 
parameter integer TX_PREEMPHASIS = 0;
6858 
output CHBONDDONE;
6859 
output [3:0] CHBONDO;
6860 
output CONFIGOUT;
6861 
output [1:0] RXBUFSTATUS;
6862 
output [3:0] RXCHARISCOMMA;
6863 
output [3:0] RXCHARISK;
6864 
output RXCHECKINGCRC;
6865 
output [2:0] RXCLKCORCNT;
6866 
output RXCOMMADET;
6867 
output RXCRCERR;
6868 
output [31:0] RXDATA;
6869 
output [3:0] RXDISPERR;
6870 
output [1:0] RXLOSSOFSYNC;
6871 
output [3:0] RXNOTINTABLE;
6872 
output RXREALIGN;
6873 
output RXRECCLK;
6874 
output [3:0] RXRUNDISP;
6875 
output TXBUFERR;
6876 
output [3:0] TXKERR;
6877 
output TXN;
6878 
output TXP;
6879 
output [3:0] TXRUNDISP;
6880 
input BREFCLK;
6881 
input BREFCLK2;
6882 
input [3:0] CHBONDI;
6883 
input CONFIGENABLE;
6884 
input CONFIGIN;
6885 
input ENCHANSYNC;
6886 
input ENMCOMMAALIGN;
6887 
input ENPCOMMAALIGN;
6888 
input [1:0] LOOPBACK;
6889 
input POWERDOWN;
6890 
input REFCLK;
6891 
input REFCLK2;
6892 
input REFCLKSEL;
6893 
input RXN;
6894 
input RXP;
6895 
input RXPOLARITY;
6896 
input RXRESET;
6897 
input RXUSRCLK;
6898 
input RXUSRCLK2;
6899 
input [3:0] TXBYPASS8B10B;
6900 
input [3:0] TXCHARDISPMODE;
6901 
input [3:0] TXCHARDISPVAL;
6902 
input [3:0] TXCHARISK;
6903 
input [31:0] TXDATA;
6904 
input TXFORCECRCERR;
6905 
input TXINHIBIT;
6906 
input TXPOLARITY;
6907 
input TXRESET;
6908 
input TXUSRCLK;
6909 
input TXUSRCLK2;
6910 
endmodule
6911 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6912 
module GT_XAUI_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6913 
parameter CHAN_BOND_MODE = "OFF";
6914 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6915 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6916 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6917 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6918 
parameter CRC_END_OF_PKT = "K29_7";
6919 
parameter CRC_FORMAT = "USER_MODE";
6920 
parameter CRC_START_OF_PKT = "K27_7";
6921 
parameter integer REF_CLK_V_SEL = 0;
6922 
parameter RX_CRC_USE = "FALSE";
6923 
parameter integer RX_LOS_INVALID_INCR = 1;
6924 
parameter integer RX_LOS_THRESHOLD = 4;
6925 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
6926 
parameter SERDES_10B = "FALSE";
6927 
parameter integer TERMINATION_IMP = 50;
6928 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
6929 
parameter TX_CRC_USE = "FALSE";
6930 
parameter integer TX_DIFF_CTRL = 500;
6931 
parameter integer TX_PREEMPHASIS = 0;
6932 
output CHBONDDONE;
6933 
output [3:0] CHBONDO;
6934 
output CONFIGOUT;
6935 
output [1:0] RXBUFSTATUS;
6936 
output [0:0] RXCHARISCOMMA;
6937 
output [0:0] RXCHARISK;
6938 
output RXCHECKINGCRC;
6939 
output [2:0] RXCLKCORCNT;
6940 
output RXCOMMADET;
6941 
output RXCRCERR;
6942 
output [7:0] RXDATA;
6943 
output [0:0] RXDISPERR;
6944 
output [1:0] RXLOSSOFSYNC;
6945 
output [0:0] RXNOTINTABLE;
6946 
output RXREALIGN;
6947 
output RXRECCLK;
6948 
output [0:0] RXRUNDISP;
6949 
output TXBUFERR;
6950 
output [0:0] TXKERR;
6951 
output TXN;
6952 
output TXP;
6953 
output [0:0] TXRUNDISP;
6954 
input BREFCLK;
6955 
input BREFCLK2;
6956 
input [3:0] CHBONDI;
6957 
input CONFIGENABLE;
6958 
input CONFIGIN;
6959 
input ENCHANSYNC;
6960 
input ENMCOMMAALIGN;
6961 
input ENPCOMMAALIGN;
6962 
input [1:0] LOOPBACK;
6963 
input POWERDOWN;
6964 
input REFCLK;
6965 
input REFCLK2;
6966 
input REFCLKSEL;
6967 
input RXN;
6968 
input RXP;
6969 
input RXPOLARITY;
6970 
input RXRESET;
6971 
input RXUSRCLK;
6972 
input RXUSRCLK2;
6973 
input [0:0] TXBYPASS8B10B;
6974 
input [0:0] TXCHARDISPMODE;
6975 
input [0:0] TXCHARDISPVAL;
6976 
input [0:0] TXCHARISK;
6977 
input [7:0] TXDATA;
6978 
input TXFORCECRCERR;
6979 
input TXINHIBIT;
6980 
input TXPOLARITY;
6981 
input TXRESET;
6982 
input TXUSRCLK;
6983 
input TXUSRCLK2;
6984 
endmodule
6985 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
6986 
module GT_XAUI_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
6987 
parameter CHAN_BOND_MODE = "OFF";
6988 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
6989 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
6990 
parameter CLK_COR_KEEP_IDLE = "FALSE";
6991 
parameter integer CLK_COR_REPEAT_WAIT = 1;
6992 
parameter CRC_END_OF_PKT = "K29_7";
6993 
parameter CRC_FORMAT = "USER_MODE";
6994 
parameter CRC_START_OF_PKT = "K27_7";
6995 
parameter integer REF_CLK_V_SEL = 0;
6996 
parameter RX_CRC_USE = "FALSE";
6997 
parameter integer RX_LOS_INVALID_INCR = 1;
6998 
parameter integer RX_LOS_THRESHOLD = 4;
6999 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
7000 
parameter SERDES_10B = "FALSE";
7001 
parameter integer TERMINATION_IMP = 50;
7002 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
7003 
parameter TX_CRC_USE = "FALSE";
7004 
parameter integer TX_DIFF_CTRL = 500;
7005 
parameter integer TX_PREEMPHASIS = 0;
7006 
output CHBONDDONE;
7007 
output [3:0] CHBONDO;
7008 
output CONFIGOUT;
7009 
output [1:0] RXBUFSTATUS;
7010 
output [1:0] RXCHARISCOMMA;
7011 
output [1:0] RXCHARISK;
7012 
output RXCHECKINGCRC;
7013 
output [2:0] RXCLKCORCNT;
7014 
output RXCOMMADET;
7015 
output RXCRCERR;
7016 
output [15:0] RXDATA;
7017 
output [1:0] RXDISPERR;
7018 
output [1:0] RXLOSSOFSYNC;
7019 
output [1:0] RXNOTINTABLE;
7020 
output RXREALIGN;
7021 
output RXRECCLK;
7022 
output [1:0] RXRUNDISP;
7023 
output TXBUFERR;
7024 
output [1:0] TXKERR;
7025 
output TXN;
7026 
output TXP;
7027 
output [1:0] TXRUNDISP;
7028 
input BREFCLK;
7029 
input BREFCLK2;
7030 
input [3:0] CHBONDI;
7031 
input CONFIGENABLE;
7032 
input CONFIGIN;
7033 
input ENCHANSYNC;
7034 
input ENMCOMMAALIGN;
7035 
input ENPCOMMAALIGN;
7036 
input [1:0] LOOPBACK;
7037 
input POWERDOWN;
7038 
input REFCLK;
7039 
input REFCLK2;
7040 
input REFCLKSEL;
7041 
input RXN;
7042 
input RXP;
7043 
input RXPOLARITY;
7044 
input RXRESET;
7045 
input RXUSRCLK;
7046 
input RXUSRCLK2;
7047 
input [1:0] TXBYPASS8B10B;
7048 
input [1:0] TXCHARDISPMODE;
7049 
input [1:0] TXCHARDISPVAL;
7050 
input [1:0] TXCHARISK;
7051 
input [15:0] TXDATA;
7052 
input TXFORCECRCERR;
7053 
input TXINHIBIT;
7054 
input TXPOLARITY;
7055 
input TXRESET;
7056 
input TXUSRCLK;
7057 
input TXUSRCLK2;
7058 
endmodule
7059 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7060 
module GT_XAUI_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
7061 
parameter CHAN_BOND_MODE = "OFF";
7062 
parameter CHAN_BOND_ONE_SHOT = "FALSE";
7063 
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
7064 
parameter CLK_COR_KEEP_IDLE = "FALSE";
7065 
parameter integer CLK_COR_REPEAT_WAIT = 1;
7066 
parameter CRC_END_OF_PKT = "K29_7";
7067 
parameter CRC_FORMAT = "USER_MODE";
7068 
parameter CRC_START_OF_PKT = "K27_7";
7069 
parameter integer REF_CLK_V_SEL = 0;
7070 
parameter RX_CRC_USE = "FALSE";
7071 
parameter integer RX_LOS_INVALID_INCR = 1;
7072 
parameter integer RX_LOS_THRESHOLD = 4;
7073 
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
7074 
parameter SERDES_10B = "FALSE";
7075 
parameter integer TERMINATION_IMP = 50;
7076 
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
7077 
parameter TX_CRC_USE = "FALSE";
7078 
parameter integer TX_DIFF_CTRL = 500;
7079 
parameter integer TX_PREEMPHASIS = 0;
7080 
output CHBONDDONE;
7081 
output [3:0] CHBONDO;
7082 
output CONFIGOUT;
7083 
output [1:0] RXBUFSTATUS;
7084 
output [3:0] RXCHARISCOMMA;
7085 
output [3:0] RXCHARISK;
7086 
output RXCHECKINGCRC;
7087 
output [2:0] RXCLKCORCNT;
7088 
output RXCOMMADET;
7089 
output RXCRCERR;
7090 
output [31:0] RXDATA;
7091 
output [3:0] RXDISPERR;
7092 
output [1:0] RXLOSSOFSYNC;
7093 
output [3:0] RXNOTINTABLE;
7094 
output RXREALIGN;
7095 
output RXRECCLK;
7096 
output [3:0] RXRUNDISP;
7097 
output TXBUFERR;
7098 
output [3:0] TXKERR;
7099 
output TXN;
7100 
output TXP;
7101 
output [3:0] TXRUNDISP;
7102 
input BREFCLK;
7103 
input BREFCLK2;
7104 
input [3:0] CHBONDI;
7105 
input CONFIGENABLE;
7106 
input CONFIGIN;
7107 
input ENCHANSYNC;
7108 
input ENMCOMMAALIGN;
7109 
input ENPCOMMAALIGN;
7110 
input [1:0] LOOPBACK;
7111 
input POWERDOWN;
7112 
input REFCLK;
7113 
input REFCLK2;
7114 
input REFCLKSEL;
7115 
input RXN;
7116 
input RXP;
7117 
input RXPOLARITY;
7118 
input RXRESET;
7119 
input RXUSRCLK;
7120 
input RXUSRCLK2;
7121 
input [3:0] TXBYPASS8B10B;
7122 
input [3:0] TXCHARDISPMODE;
7123 
input [3:0] TXCHARDISPVAL;
7124 
input [3:0] TXCHARISK;
7125 
input [31:0] TXDATA;
7126 
input TXFORCECRCERR;
7127 
input TXINHIBIT;
7128 
input TXPOLARITY;
7129 
input TXRESET;
7130 
input TXUSRCLK;
7131 
input TXUSRCLK2;
7132 
endmodule
7133 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7134 
module GTX_DUAL (DFECLKDLYADJMONITOR0, DFECLKDLYADJMONITOR1, DFEEYEDACMONITOR0, DFEEYEDACMONITOR1, DFESENSCAL0, DFESENSCAL1, DFETAP1MONITOR0, DFETAP1MONITOR1, DFETAP2MONITOR0, DFETAP2MONITOR1, DFETAP3MONITOR0, DFETAP3MONITOR1, DFETAP4MONITOR0, DFETAP4MONITOR1, DO, DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBUFSTATUS0, RXBUFSTATUS1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXCOMMADET0, RXCOMMADET1, RXDATA0, RXDATA1, RXDATAVALID0, RXDATAVALID1, RXDISPERR0, RXDISPERR1, RXELECIDLE0, RXELECIDLE1, RXHEADER0, RXHEADER1, RXHEADERVALID0, RXHEADERVALID1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXRUNDISP0, RXRUNDISP1, RXSTARTOFSEQ0, RXSTARTOFSEQ1, RXSTATUS0, RXSTATUS1, RXVALID0, RXVALID1, TXBUFSTATUS0, TXBUFSTATUS1, TXGEARBOXREADY0, TXGEARBOXREADY1, TXKERR0, TXKERR1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, TXRUNDISP0, TXRUNDISP1, CLKIN, DADDR, DCLK, DEN, DFECLKDLYADJ0, DFECLKDLYADJ1, DFETAP10, DFETAP11, DFETAP20, DFETAP21, DFETAP30, DFETAP31, DFETAP40, DFETAP41, DI, DWE, GTXRESET, GTXTEST, INTDATAWIDTH, LOOPBACK0, LOOPBACK1, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDI0, RXCHBONDI1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXENPRBSTST0, RXENPRBSTST1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXEQMIX0, RXEQMIX1, RXEQPOLE0, RXEQPOLE1, RXGEARBOXSLIP0, RXGEARBOXSLIP1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXPOWERDOWN0, RXPOWERDOWN1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATA0, TXDATA1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXDIFFCTRL0, TXDIFFCTRL1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXENPRBSTST0, TXENPRBSTST1, TXHEADER0, TXHEADER1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXPOWERDOWN0, TXPOWERDOWN1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXRESET0, TXRESET1, TXSEQUENCE0, TXSEQUENCE1, TXSTARTSEQ0, TXSTARTSEQ1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21);
7135 
parameter AC_CAP_DIS_0 = "TRUE";
7136 
parameter AC_CAP_DIS_1 = "TRUE";
7137 
parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
7138 
parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
7139 
parameter CHAN_BOND_MODE_0 = "OFF";
7140 
parameter CHAN_BOND_MODE_1 = "OFF";
7141 
parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE";
7142 
parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE";
7143 
parameter CLKINDC_B = "TRUE";
7144 
parameter CLKRCV_TRST = "TRUE";
7145 
parameter CLK_CORRECT_USE_0 = "TRUE";
7146 
parameter CLK_CORRECT_USE_1 = "TRUE";
7147 
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
7148 
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
7149 
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
7150 
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
7151 
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
7152 
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
7153 
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
7154 
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
7155 
parameter COMMA_DOUBLE_0 = "FALSE";
7156 
parameter COMMA_DOUBLE_1 = "FALSE";
7157 
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
7158 
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
7159 
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
7160 
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
7161 
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
7162 
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
7163 
parameter MCOMMA_DETECT_0 = "TRUE";
7164 
parameter MCOMMA_DETECT_1 = "TRUE";
7165 
parameter OVERSAMPLE_MODE = "FALSE";
7166 
parameter PCI_EXPRESS_MODE_0 = "FALSE";
7167 
parameter PCI_EXPRESS_MODE_1 = "FALSE";
7168 
parameter PCOMMA_DETECT_0 = "TRUE";
7169 
parameter PCOMMA_DETECT_1 = "TRUE";
7170 
parameter PLL_FB_DCCEN = "FALSE";
7171 
parameter PLL_SATA_0 = "FALSE";
7172 
parameter PLL_SATA_1 = "FALSE";
7173 
parameter RCV_TERM_GND_0 = "FALSE";
7174 
parameter RCV_TERM_GND_1 = "FALSE";
7175 
parameter RCV_TERM_VTTRX_0 = "FALSE";
7176 
parameter RCV_TERM_VTTRX_1 = "FALSE";
7177 
parameter RXGEARBOX_USE_0 = "FALSE";
7178 
parameter RXGEARBOX_USE_1 = "FALSE";
7179 
parameter RX_BUFFER_USE_0 = "TRUE";
7180 
parameter RX_BUFFER_USE_1 = "TRUE";
7181 
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
7182 
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
7183 
parameter RX_EN_IDLE_HOLD_CDR = "FALSE";
7184 
parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE";
7185 
parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE";
7186 
parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE";
7187 
parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE";
7188 
parameter RX_EN_IDLE_RESET_FR = "TRUE";
7189 
parameter RX_EN_IDLE_RESET_PH = "TRUE";
7190 
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
7191 
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
7192 
parameter RX_SLIDE_MODE_0 = "PCS";
7193 
parameter RX_SLIDE_MODE_1 = "PCS";
7194 
parameter RX_STATUS_FMT_0 = "PCIE";
7195 
parameter RX_STATUS_FMT_1 = "PCIE";
7196 
parameter RX_XCLK_SEL_0 = "RXREC";
7197 
parameter RX_XCLK_SEL_1 = "RXREC";
7198 
parameter SIM_MODE = "FAST";
7199 
parameter SIM_PLL_PERDIV2 = 9'h140;
7200 
parameter SIM_RECEIVER_DETECT_PASS_0 = "TRUE";
7201 
parameter SIM_RECEIVER_DETECT_PASS_1 = "TRUE";
7202 
parameter TERMINATION_OVRD = "FALSE";
7203 
parameter TXGEARBOX_USE_0 = "FALSE";
7204 
parameter TXGEARBOX_USE_1 = "FALSE";
7205 
parameter TX_BUFFER_USE_0 = "TRUE";
7206 
parameter TX_BUFFER_USE_1 = "TRUE";
7207 
parameter TX_XCLK_SEL_0 = "TXOUT";
7208 
parameter TX_XCLK_SEL_1 = "TXOUT";
7209 
parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c;
7210 
parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c;
7211 
parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832;
7212 
parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832;
7213 
parameter [19:0] PMA_TX_CFG_0 = 20'h80082;
7214 
parameter [19:0] PMA_TX_CFG_1 = 20'h80082;
7215 
parameter [1:0] CM_TRIM_0 = 2'b10;
7216 
parameter [1:0] CM_TRIM_1 = 2'b10;
7217 
parameter [23:0] PLL_COM_CFG = 24'h21680a;
7218 
parameter [24:0] PMA_RX_CFG_0 = 25'h0f44089;
7219 
parameter [24:0] PMA_RX_CFG_1 = 25'h0f44089;
7220 
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404035;
7221 
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404035;
7222 
parameter [2:0] GEARBOX_ENDEC_0 = 3'b000;
7223 
parameter [2:0] GEARBOX_ENDEC_1 = 3'b000;
7224 
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110;
7225 
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110;
7226 
parameter [2:0] PLL_LKDET_CFG = 3'b101;
7227 
parameter [2:0] PLL_TDCC_CFG = 3'b000;
7228 
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
7229 
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
7230 
parameter [2:0] SATA_IDLE_VAL_0 = 3'b100;
7231 
parameter [2:0] SATA_IDLE_VAL_1 = 3'b100;
7232 
parameter [2:0] TXRX_INVERT_0 = 3'b011;
7233 
parameter [2:0] TXRX_INVERT_1 = 3'b011;
7234 
parameter [2:0] TX_IDLE_DELAY_0 = 3'b010;
7235 
parameter [2:0] TX_IDLE_DELAY_1 = 3'b010;
7236 
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h00000001;
7237 
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h00000001;
7238 
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b0001;
7239 
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b0001;
7240 
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b0000;
7241 
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b0000;
7242 
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b0001;
7243 
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b0001;
7244 
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b0000;
7245 
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b0000;
7246 
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
7247 
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
7248 
parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000;
7249 
parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000;
7250 
parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000;
7251 
parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000;
7252 
parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010;
7253 
parameter [4:0] DFE_CAL_TIME = 5'b00110;
7254 
parameter [4:0] TERMINATION_CTRL = 5'b10100;
7255 
parameter [68:0] PMA_COM_CFG = 69'h0;
7256 
parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0;
7257 
parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0;
7258 
parameter [7:0] PLL_CP_CFG = 8'h00;
7259 
parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19;
7260 
parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19;
7261 
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100;
7262 
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100;
7263 
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0000000000;
7264 
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0000000000;
7265 
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0000000000;
7266 
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0000000000;
7267 
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0000000000;
7268 
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0000000000;
7269 
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0000000000;
7270 
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0000000000;
7271 
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0000000000;
7272 
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0000000000;
7273 
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0000000000;
7274 
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0000000000;
7275 
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0000000000;
7276 
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0000000000;
7277 
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
7278 
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
7279 
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000;
7280 
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000;
7281 
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000;
7282 
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000;
7283 
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000;
7284 
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000;
7285 
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000;
7286 
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000;
7287 
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000;
7288 
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000;
7289 
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000;
7290 
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000;
7291 
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000;
7292 
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000;
7293 
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b0001111111;
7294 
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b0001111111;
7295 
parameter [9:0] DFE_CFG_0 = 10'b1101111011;
7296 
parameter [9:0] DFE_CFG_1 = 10'b1101111011;
7297 
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
7298 
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
7299 
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
7300 
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
7301 
parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064;
7302 
parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064;
7303 
parameter integer ALIGN_COMMA_WORD_0 = 1;
7304 
parameter integer ALIGN_COMMA_WORD_1 = 1;
7305 
parameter integer CB2_INH_CC_PERIOD_0 = 8;
7306 
parameter integer CB2_INH_CC_PERIOD_1 = 8;
7307 
parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
7308 
parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
7309 
parameter integer CHAN_BOND_2_MAX_SKEW_0 = 7;
7310 
parameter integer CHAN_BOND_2_MAX_SKEW_1 = 7;
7311 
parameter integer CHAN_BOND_LEVEL_0 = 0;
7312 
parameter integer CHAN_BOND_LEVEL_1 = 0;
7313 
parameter integer CHAN_BOND_SEQ_LEN_0 = 1;
7314 
parameter integer CHAN_BOND_SEQ_LEN_1 = 1;
7315 
parameter integer CLK25_DIVIDER = 10;
7316 
parameter integer CLK_COR_ADJ_LEN_0 = 1;
7317 
parameter integer CLK_COR_ADJ_LEN_1 = 1;
7318 
parameter integer CLK_COR_DET_LEN_0 = 1;
7319 
parameter integer CLK_COR_DET_LEN_1 = 1;
7320 
parameter integer CLK_COR_MAX_LAT_0 = 20;
7321 
parameter integer CLK_COR_MAX_LAT_1 = 20;
7322 
parameter integer CLK_COR_MIN_LAT_0 = 18;
7323 
parameter integer CLK_COR_MIN_LAT_1 = 18;
7324 
parameter integer CLK_COR_REPEAT_WAIT_0 = 0;
7325 
parameter integer CLK_COR_REPEAT_WAIT_1 = 0;
7326 
parameter integer OOB_CLK_DIVIDER = 6;
7327 
parameter integer PLL_DIVSEL_FB = 2;
7328 
parameter integer PLL_DIVSEL_REF = 1;
7329 
parameter integer PLL_RXDIVSEL_OUT_0 = 1;
7330 
parameter integer PLL_RXDIVSEL_OUT_1 = 1;
7331 
parameter integer PLL_TXDIVSEL_OUT_0 = 1;
7332 
parameter integer PLL_TXDIVSEL_OUT_1 = 1;
7333 
parameter integer RX_LOS_INVALID_INCR_0 = 1;
7334 
parameter integer RX_LOS_INVALID_INCR_1 = 1;
7335 
parameter integer RX_LOS_THRESHOLD_0 = 4;
7336 
parameter integer RX_LOS_THRESHOLD_1 = 4;
7337 
parameter integer SATA_MAX_BURST_0 = 7;
7338 
parameter integer SATA_MAX_BURST_1 = 7;
7339 
parameter integer SATA_MAX_INIT_0 = 22;
7340 
parameter integer SATA_MAX_INIT_1 = 22;
7341 
parameter integer SATA_MAX_WAKE_0 = 7;
7342 
parameter integer SATA_MAX_WAKE_1 = 7;
7343 
parameter integer SATA_MIN_BURST_0 = 4;
7344 
parameter integer SATA_MIN_BURST_1 = 4;
7345 
parameter integer SATA_MIN_INIT_0 = 12;
7346 
parameter integer SATA_MIN_INIT_1 = 12;
7347 
parameter integer SATA_MIN_WAKE_0 = 4;
7348 
parameter integer SATA_MIN_WAKE_1 = 4;
7349 
parameter integer SIM_GTXRESET_SPEEDUP = 1;
7350 
parameter integer TERMINATION_IMP_0 = 50;
7351 
parameter integer TERMINATION_IMP_1 = 50;
7352 
output [5:0] DFECLKDLYADJMONITOR0;
7353 
output [5:0] DFECLKDLYADJMONITOR1;
7354 
output [4:0] DFEEYEDACMONITOR0;
7355 
output [4:0] DFEEYEDACMONITOR1;
7356 
output [2:0] DFESENSCAL0;
7357 
output [2:0] DFESENSCAL1;
7358 
output [4:0] DFETAP1MONITOR0;
7359 
output [4:0] DFETAP1MONITOR1;
7360 
output [4:0] DFETAP2MONITOR0;
7361 
output [4:0] DFETAP2MONITOR1;
7362 
output [3:0] DFETAP3MONITOR0;
7363 
output [3:0] DFETAP3MONITOR1;
7364 
output [3:0] DFETAP4MONITOR0;
7365 
output [3:0] DFETAP4MONITOR1;
7366 
output [15:0] DO;
7367 
output DRDY;
7368 
output PHYSTATUS0;
7369 
output PHYSTATUS1;
7370 
output PLLLKDET;
7371 
output REFCLKOUT;
7372 
output RESETDONE0;
7373 
output RESETDONE1;
7374 
output [2:0] RXBUFSTATUS0;
7375 
output [2:0] RXBUFSTATUS1;
7376 
output RXBYTEISALIGNED0;
7377 
output RXBYTEISALIGNED1;
7378 
output RXBYTEREALIGN0;
7379 
output RXBYTEREALIGN1;
7380 
output RXCHANBONDSEQ0;
7381 
output RXCHANBONDSEQ1;
7382 
output RXCHANISALIGNED0;
7383 
output RXCHANISALIGNED1;
7384 
output RXCHANREALIGN0;
7385 
output RXCHANREALIGN1;
7386 
output [3:0] RXCHARISCOMMA0;
7387 
output [3:0] RXCHARISCOMMA1;
7388 
output [3:0] RXCHARISK0;
7389 
output [3:0] RXCHARISK1;
7390 
output [3:0] RXCHBONDO0;
7391 
output [3:0] RXCHBONDO1;
7392 
output [2:0] RXCLKCORCNT0;
7393 
output [2:0] RXCLKCORCNT1;
7394 
output RXCOMMADET0;
7395 
output RXCOMMADET1;
7396 
output [31:0] RXDATA0;
7397 
output [31:0] RXDATA1;
7398 
output RXDATAVALID0;
7399 
output RXDATAVALID1;
7400 
output [3:0] RXDISPERR0;
7401 
output [3:0] RXDISPERR1;
7402 
output RXELECIDLE0;
7403 
output RXELECIDLE1;
7404 
output [2:0] RXHEADER0;
7405 
output [2:0] RXHEADER1;
7406 
output RXHEADERVALID0;
7407 
output RXHEADERVALID1;
7408 
output [1:0] RXLOSSOFSYNC0;
7409 
output [1:0] RXLOSSOFSYNC1;
7410 
output [3:0] RXNOTINTABLE0;
7411 
output [3:0] RXNOTINTABLE1;
7412 
output RXOVERSAMPLEERR0;
7413 
output RXOVERSAMPLEERR1;
7414 
output RXPRBSERR0;
7415 
output RXPRBSERR1;
7416 
output RXRECCLK0;
7417 
output RXRECCLK1;
7418 
output [3:0] RXRUNDISP0;
7419 
output [3:0] RXRUNDISP1;
7420 
output RXSTARTOFSEQ0;
7421 
output RXSTARTOFSEQ1;
7422 
output [2:0] RXSTATUS0;
7423 
output [2:0] RXSTATUS1;
7424 
output RXVALID0;
7425 
output RXVALID1;
7426 
output [1:0] TXBUFSTATUS0;
7427 
output [1:0] TXBUFSTATUS1;
7428 
output TXGEARBOXREADY0;
7429 
output TXGEARBOXREADY1;
7430 
output [3:0] TXKERR0;
7431 
output [3:0] TXKERR1;
7432 
output TXN0;
7433 
output TXN1;
7434 
output TXOUTCLK0;
7435 
output TXOUTCLK1;
7436 
output TXP0;
7437 
output TXP1;
7438 
output [3:0] TXRUNDISP0;
7439 
output [3:0] TXRUNDISP1;
7440 
input CLKIN;
7441 
input [6:0] DADDR;
7442 
input DCLK;
7443 
input DEN;
7444 
input [5:0] DFECLKDLYADJ0;
7445 
input [5:0] DFECLKDLYADJ1;
7446 
input [4:0] DFETAP10;
7447 
input [4:0] DFETAP11;
7448 
input [4:0] DFETAP20;
7449 
input [4:0] DFETAP21;
7450 
input [3:0] DFETAP30;
7451 
input [3:0] DFETAP31;
7452 
input [3:0] DFETAP40;
7453 
input [3:0] DFETAP41;
7454 
input [15:0] DI;
7455 
input DWE;
7456 
input GTXRESET;
7457 
input [13:0] GTXTEST;
7458 
input INTDATAWIDTH;
7459 
input [2:0] LOOPBACK0;
7460 
input [2:0] LOOPBACK1;
7461 
input PLLLKDETEN;
7462 
input PLLPOWERDOWN;
7463 
input PRBSCNTRESET0;
7464 
input PRBSCNTRESET1;
7465 
input REFCLKPWRDNB;
7466 
input RXBUFRESET0;
7467 
input RXBUFRESET1;
7468 
input RXCDRRESET0;
7469 
input RXCDRRESET1;
7470 
input [3:0] RXCHBONDI0;
7471 
input [3:0] RXCHBONDI1;
7472 
input RXCOMMADETUSE0;
7473 
input RXCOMMADETUSE1;
7474 
input [1:0] RXDATAWIDTH0;
7475 
input [1:0] RXDATAWIDTH1;
7476 
input RXDEC8B10BUSE0;
7477 
input RXDEC8B10BUSE1;
7478 
input RXENCHANSYNC0;
7479 
input RXENCHANSYNC1;
7480 
input RXENEQB0;
7481 
input RXENEQB1;
7482 
input RXENMCOMMAALIGN0;
7483 
input RXENMCOMMAALIGN1;
7484 
input RXENPCOMMAALIGN0;
7485 
input RXENPCOMMAALIGN1;
7486 
input RXENPMAPHASEALIGN0;
7487 
input RXENPMAPHASEALIGN1;
7488 
input [1:0] RXENPRBSTST0;
7489 
input [1:0] RXENPRBSTST1;
7490 
input RXENSAMPLEALIGN0;
7491 
input RXENSAMPLEALIGN1;
7492 
input [1:0] RXEQMIX0;
7493 
input [1:0] RXEQMIX1;
7494 
input [3:0] RXEQPOLE0;
7495 
input [3:0] RXEQPOLE1;
7496 
input RXGEARBOXSLIP0;
7497 
input RXGEARBOXSLIP1;
7498 
input RXN0;
7499 
input RXN1;
7500 
input RXP0;
7501 
input RXP1;
7502 
input RXPMASETPHASE0;
7503 
input RXPMASETPHASE1;
7504 
input RXPOLARITY0;
7505 
input RXPOLARITY1;
7506 
input [1:0] RXPOWERDOWN0;
7507 
input [1:0] RXPOWERDOWN1;
7508 
input RXRESET0;
7509 
input RXRESET1;
7510 
input RXSLIDE0;
7511 
input RXSLIDE1;
7512 
input RXUSRCLK0;
7513 
input RXUSRCLK1;
7514 
input RXUSRCLK20;
7515 
input RXUSRCLK21;
7516 
input [2:0] TXBUFDIFFCTRL0;
7517 
input [2:0] TXBUFDIFFCTRL1;
7518 
input [3:0] TXBYPASS8B10B0;
7519 
input [3:0] TXBYPASS8B10B1;
7520 
input [3:0] TXCHARDISPMODE0;
7521 
input [3:0] TXCHARDISPMODE1;
7522 
input [3:0] TXCHARDISPVAL0;
7523 
input [3:0] TXCHARDISPVAL1;
7524 
input [3:0] TXCHARISK0;
7525 
input [3:0] TXCHARISK1;
7526 
input TXCOMSTART0;
7527 
input TXCOMSTART1;
7528 
input TXCOMTYPE0;
7529 
input TXCOMTYPE1;
7530 
input [31:0] TXDATA0;
7531 
input [31:0] TXDATA1;
7532 
input [1:0] TXDATAWIDTH0;
7533 
input [1:0] TXDATAWIDTH1;
7534 
input TXDETECTRX0;
7535 
input TXDETECTRX1;
7536 
input [2:0] TXDIFFCTRL0;
7537 
input [2:0] TXDIFFCTRL1;
7538 
input TXELECIDLE0;
7539 
input TXELECIDLE1;
7540 
input TXENC8B10BUSE0;
7541 
input TXENC8B10BUSE1;
7542 
input TXENPMAPHASEALIGN0;
7543 
input TXENPMAPHASEALIGN1;
7544 
input [1:0] TXENPRBSTST0;
7545 
input [1:0] TXENPRBSTST1;
7546 
input [2:0] TXHEADER0;
7547 
input [2:0] TXHEADER1;
7548 
input TXINHIBIT0;
7549 
input TXINHIBIT1;
7550 
input TXPMASETPHASE0;
7551 
input TXPMASETPHASE1;
7552 
input TXPOLARITY0;
7553 
input TXPOLARITY1;
7554 
input [1:0] TXPOWERDOWN0;
7555 
input [1:0] TXPOWERDOWN1;
7556 
input [3:0] TXPREEMPHASIS0;
7557 
input [3:0] TXPREEMPHASIS1;
7558 
input TXRESET0;
7559 
input TXRESET1;
7560 
input [6:0] TXSEQUENCE0;
7561 
input [6:0] TXSEQUENCE1;
7562 
input TXSTARTSEQ0;
7563 
input TXSTARTSEQ1;
7564 
input TXUSRCLK0;
7565 
input TXUSRCLK1;
7566 
input TXUSRCLK20;
7567 
input TXUSRCLK21;
7568 
endmodule
7569 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7570 
module IBUF_AGP (O, I);
7571 
output O;
7572 
input I;
7573 
endmodule
7574 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7575 
module IBUF_CTT (O, I);
7576 
output O;
7577 
input I;
7578 
endmodule
7579 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7580 
module IBUF_DLY_ADJ (O, I, S);
7581 
parameter DELAY_OFFSET = "OFF";
7582 
parameter IOSTANDARD = "DEFAULT";
7583 
output O;
7584 
input I;
7585 
input [2:0] S;
7586 
endmodule
7587 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7588 
module IBUFDS_BLVDS_25 (O, I, IB);
7589 
output O;
7590 
input I;
7591 
input IB;
7592 
endmodule
7593 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7594 
module IBUFDS_DIFF_OUT (O, OB, I, IB);
7595 
parameter IOSTANDARD = "LVDS_25";
7596 
output O;
7597 
output OB;
7598 
input I;
7599 
input IB;
7600 
endmodule
7601 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7602 
module IBUFDS_DLY_ADJ (O, I, IB, S);
7603 
parameter DELAY_OFFSET = "OFF";
7604 
parameter DIFF_TERM = "FALSE";
7605 
parameter IOSTANDARD = "DEFAULT";
7606 
output O;
7607 
input I;
7608 
input IB;
7609 
input [2:0] S;
7610 
endmodule
7611 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7612 
module IBUFDS_LDT_25 (O, I, IB);
7613 
output O;
7614 
input I;
7615 
input IB;
7616 
endmodule
7617 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7618 
module IBUFDS_LVDS_25_DCI (O, I, IB);
7619 
output O;
7620 
input I;
7621 
input IB;
7622 
endmodule
7623 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7624 
module IBUFDS_LVDS_25 (O, I, IB);
7625 
output O;
7626 
input I;
7627 
input IB;
7628 
endmodule
7629 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7630 
module IBUFDS_LVDS_33_DCI (O, I, IB);
7631 
output O;
7632 
input I;
7633 
input IB;
7634 
endmodule
7635 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7636 
module IBUFDS_LVDS_33 (O, I, IB);
7637 
output O;
7638 
input I;
7639 
input IB;
7640 
endmodule
7641 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7642 
module IBUFDS_LVDSEXT_25_DCI (O, I, IB);
7643 
output O;
7644 
input I;
7645 
input IB;
7646 
endmodule
7647 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7648 
module IBUFDS_LVDSEXT_25 (O, I, IB);
7649 
output O;
7650 
input I;
7651 
input IB;
7652 
endmodule
7653 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7654 
module IBUFDS_LVDSEXT_33_DCI (O, I, IB);
7655 
output O;
7656 
input I;
7657 
input IB;
7658 
endmodule
7659 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7660 
module IBUFDS_LVDSEXT_33 (O, I, IB);
7661 
output O;
7662 
input I;
7663 
input IB;
7664 
endmodule
7665 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7666 
module IBUFDS_LVPECL_25 (O, I, IB);
7667 
output O;
7668 
input I;
7669 
input IB;
7670 
endmodule
7671 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7672 
module IBUFDS_LVPECL_33 (O, I, IB);
7673 
output O;
7674 
input I;
7675 
input IB;
7676 
endmodule
7677 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7678 
module IBUFDS_ULVDS_25 (O, I, IB);
7679 
output O;
7680 
input I;
7681 
input IB;
7682 
endmodule
7683 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7684 
module IBUFDS (O, I, IB);
7685 
parameter CAPACITANCE = "DONT_CARE";
7686 
parameter DIFF_TERM = "FALSE";
7687 
parameter IBUF_DELAY_VALUE = "0";
7688 
parameter IFD_DELAY_VALUE = "AUTO";
7689 
parameter IOSTANDARD = "DEFAULT";
7690 
output O;
7691 
input I;
7692 
input IB;
7693 
endmodule
7694 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7695 
module IBUFG_AGP (O, I);
7696 
output O;
7697 
input I;
7698 
endmodule
7699 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7700 
module IBUFG_CTT (O, I);
7701 
output O;
7702 
input I;
7703 
endmodule
7704 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7705 
module IBUFGDS_BLVDS_25 (O, I, IB);
7706 
output O;
7707 
input I;
7708 
input IB;
7709 
endmodule
7710 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7711 
module IBUFGDS_DIFF_OUT (O, OB, I, IB);
7712 
parameter IOSTANDARD = "LVDS_25";
7713 
output O;
7714 
output OB;
7715 
input I;
7716 
input IB;
7717 
endmodule
7718 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7719 
module IBUFGDS_LDT_25 (O, I, IB);
7720 
output O;
7721 
input I;
7722 
input IB;
7723 
endmodule
7724 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7725 
module IBUFGDS_LVDS_25_DCI (O, I, IB);
7726 
output O;
7727 
input I;
7728 
input IB;
7729 
endmodule
7730 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7731 
module IBUFGDS_LVDS_25 (O, I, IB);
7732 
output O;
7733 
input I;
7734 
input IB;
7735 
endmodule
7736 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7737 
module IBUFGDS_LVDS_33_DCI (O, I, IB);
7738 
output O;
7739 
input I;
7740 
input IB;
7741 
endmodule
7742 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7743 
module IBUFGDS_LVDS_33 (O, I, IB);
7744 
output O;
7745 
input I;
7746 
input IB;
7747 
endmodule
7748 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7749 
module IBUFGDS_LVDSEXT_25_DCI (O, I, IB);
7750 
output O;
7751 
input I;
7752 
input IB;
7753 
endmodule
7754 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7755 
module IBUFGDS_LVDSEXT_25 (O, I, IB);
7756 
output O;
7757 
input I;
7758 
input IB;
7759 
endmodule
7760 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7761 
module IBUFGDS_LVDSEXT_33_DCI (O, I, IB);
7762 
output O;
7763 
input I;
7764 
input IB;
7765 
endmodule
7766 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7767 
module IBUFGDS_LVDSEXT_33 (O, I, IB);
7768 
output O;
7769 
input I;
7770 
input IB;
7771 
endmodule
7772 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7773 
module IBUFGDS_LVPECL_25 (O, I, IB);
7774 
output O;
7775 
input I;
7776 
input IB;
7777 
endmodule
7778 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7779 
module IBUFGDS_LVPECL_33 (O, I, IB);
7780 
output O;
7781 
input I;
7782 
input IB;
7783 
endmodule
7784 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7785 
module IBUFGDS_ULVDS_25 (O, I, IB);
7786 
output O;
7787 
input I;
7788 
input IB;
7789 
endmodule
7790 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7791 
module IBUFGDS (O, I, IB);
7792 
parameter CAPACITANCE = "DONT_CARE";
7793 
parameter DIFF_TERM = "FALSE";
7794 
parameter IBUF_DELAY_VALUE = "0";
7795 
parameter IOSTANDARD = "DEFAULT";
7796 
output O;
7797 
input I;
7798 
input IB;
7799 
endmodule
7800 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7801 
module IBUFG_GTL_DCI (O, I);
7802 
output O;
7803 
input I;
7804 
endmodule
7805 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7806 
module IBUFG_GTLP_DCI (O, I);
7807 
output O;
7808 
input I;
7809 
endmodule
7810 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7811 
module IBUFG_GTLP (O, I);
7812 
output O;
7813 
input I;
7814 
endmodule
7815 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7816 
module IBUFG_GTL (O, I);
7817 
output O;
7818 
input I;
7819 
endmodule
7820 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7821 
module IBUFG_HSTL_I_18 (O, I);
7822 
output O;
7823 
input I;
7824 
endmodule
7825 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7826 
module IBUFG_HSTL_I_DCI_18 (O, I);
7827 
output O;
7828 
input I;
7829 
endmodule
7830 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7831 
module IBUFG_HSTL_I_DCI (O, I);
7832 
output O;
7833 
input I;
7834 
endmodule
7835 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7836 
module IBUFG_HSTL_II_18 (O, I);
7837 
output O;
7838 
input I;
7839 
endmodule
7840 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7841 
module IBUFG_HSTL_II_DCI_18 (O, I);
7842 
output O;
7843 
input I;
7844 
endmodule
7845 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7846 
module IBUFG_HSTL_II_DCI (O, I);
7847 
output O;
7848 
input I;
7849 
endmodule
7850 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7851 
module IBUFG_HSTL_III_18 (O, I);
7852 
output O;
7853 
input I;
7854 
endmodule
7855 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7856 
module IBUFG_HSTL_III_DCI_18 (O, I);
7857 
output O;
7858 
input I;
7859 
endmodule
7860 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7861 
module IBUFG_HSTL_III_DCI (O, I);
7862 
output O;
7863 
input I;
7864 
endmodule
7865 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7866 
module IBUFG_HSTL_III (O, I);
7867 
output O;
7868 
input I;
7869 
endmodule
7870 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7871 
module IBUFG_HSTL_II (O, I);
7872 
output O;
7873 
input I;
7874 
endmodule
7875 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7876 
module IBUFG_HSTL_I (O, I);
7877 
output O;
7878 
input I;
7879 
endmodule
7880 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7881 
module IBUFG_HSTL_IV_18 (O, I);
7882 
output O;
7883 
input I;
7884 
endmodule
7885 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7886 
module IBUFG_HSTL_IV_DCI_18 (O, I);
7887 
output O;
7888 
input I;
7889 
endmodule
7890 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7891 
module IBUFG_HSTL_IV_DCI (O, I);
7892 
output O;
7893 
input I;
7894 
endmodule
7895 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7896 
module IBUFG_HSTL_IV (O, I);
7897 
output O;
7898 
input I;
7899 
endmodule
7900 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7901 
module IBUFG_LVCMOS12 (O, I);
7902 
output O;
7903 
input I;
7904 
endmodule
7905 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7906 
module IBUFG_LVCMOS15 (O, I);
7907 
output O;
7908 
input I;
7909 
endmodule
7910 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7911 
module IBUFG_LVCMOS18 (O, I);
7912 
output O;
7913 
input I;
7914 
endmodule
7915 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7916 
module IBUFG_LVCMOS25 (O, I);
7917 
output O;
7918 
input I;
7919 
endmodule
7920 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7921 
module IBUFG_LVCMOS2 (O, I);
7922 
output O;
7923 
input I;
7924 
endmodule
7925 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7926 
module IBUFG_LVCMOS33 (O, I);
7927 
output O;
7928 
input I;
7929 
endmodule
7930 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7931 
module IBUFG_LVDCI_15 (O, I);
7932 
output O;
7933 
input I;
7934 
endmodule
7935 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7936 
module IBUFG_LVDCI_18 (O, I);
7937 
output O;
7938 
input I;
7939 
endmodule
7940 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7941 
module IBUFG_LVDCI_25 (O, I);
7942 
output O;
7943 
input I;
7944 
endmodule
7945 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7946 
module IBUFG_LVDCI_33 (O, I);
7947 
output O;
7948 
input I;
7949 
endmodule
7950 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7951 
module IBUFG_LVDCI_DV2_15 (O, I);
7952 
output O;
7953 
input I;
7954 
endmodule
7955 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7956 
module IBUFG_LVDCI_DV2_18 (O, I);
7957 
output O;
7958 
input I;
7959 
endmodule
7960 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7961 
module IBUFG_LVDCI_DV2_25 (O, I);
7962 
output O;
7963 
input I;
7964 
endmodule
7965 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7966 
module IBUFG_LVDCI_DV2_33 (O, I);
7967 
output O;
7968 
input I;
7969 
endmodule
7970 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7971 
module IBUFG_LVDS (O, I);
7972 
output O;
7973 
input I;
7974 
endmodule
7975 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7976 
module IBUFG_LVPECL (O, I);
7977 
output O;
7978 
input I;
7979 
endmodule
7980 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7981 
module IBUFG_LVTTL (O, I);
7982 
output O;
7983 
input I;
7984 
endmodule
7985 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7986 
module IBUFG_PCI33_3 (O, I);
7987 
output O;
7988 
input I;
7989 
endmodule
7990 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7991 
module IBUFG_PCI33_5 (O, I);
7992 
output O;
7993 
input I;
7994 
endmodule
7995 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
7996 
module IBUFG_PCI66_3 (O, I);
7997 
output O;
7998 
input I;
7999 
endmodule
8000 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8001 
module IBUFG_PCIX66_3 (O, I);
8002 
output O;
8003 
input I;
8004 
endmodule
8005 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8006 
module IBUFG_PCIX (O, I);
8007 
output O;
8008 
input I;
8009 
endmodule
8010 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8011 
module IBUFG_SSTL18_I_DCI (O, I);
8012 
output O;
8013 
input I;
8014 
endmodule
8015 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8016 
module IBUFG_SSTL18_II_DCI (O, I);
8017 
output O;
8018 
input I;
8019 
endmodule
8020 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8021 
module IBUFG_SSTL18_II (O, I);
8022 
output O;
8023 
input I;
8024 
endmodule
8025 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8026 
module IBUFG_SSTL18_I (O, I);
8027 
output O;
8028 
input I;
8029 
endmodule
8030 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8031 
module IBUFG_SSTL2_I_DCI (O, I);
8032 
output O;
8033 
input I;
8034 
endmodule
8035 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8036 
module IBUFG_SSTL2_II_DCI (O, I);
8037 
output O;
8038 
input I;
8039 
endmodule
8040 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8041 
module IBUFG_SSTL2_II (O, I);
8042 
output O;
8043 
input I;
8044 
endmodule
8045 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8046 
module IBUFG_SSTL2_I (O, I);
8047 
output O;
8048 
input I;
8049 
endmodule
8050 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8051 
module IBUFG_SSTL3_I_DCI (O, I);
8052 
output O;
8053 
input I;
8054 
endmodule
8055 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8056 
module IBUFG_SSTL3_II_DCI (O, I);
8057 
output O;
8058 
input I;
8059 
endmodule
8060 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8061 
module IBUFG_SSTL3_II (O, I);
8062 
output O;
8063 
input I;
8064 
endmodule
8065 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8066 
module IBUFG_SSTL3_I (O, I);
8067 
output O;
8068 
input I;
8069 
endmodule
8070 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8071 
module IBUF_GTL_DCI (O, I);
8072 
output O;
8073 
input I;
8074 
endmodule
8075 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8076 
module IBUF_GTLP_DCI (O, I);
8077 
output O;
8078 
input I;
8079 
endmodule
8080 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8081 
module IBUF_GTLP (O, I);
8082 
output O;
8083 
input I;
8084 
endmodule
8085 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8086 
module IBUF_GTL (O, I);
8087 
output O;
8088 
input I;
8089 
endmodule
8090 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8091 
module IBUFG (O, I);
8092 
parameter CAPACITANCE = "DONT_CARE";
8093 
parameter IBUF_DELAY_VALUE = "0";
8094 
parameter IOSTANDARD = "DEFAULT";
8095 
output O;
8096 
input I;
8097 
endmodule
8098 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8099 
module IBUF_HSTL_I_18 (O, I);
8100 
output O;
8101 
input I;
8102 
endmodule
8103 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8104 
module IBUF_HSTL_I_DCI_18 (O, I);
8105 
output O;
8106 
input I;
8107 
endmodule
8108 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8109 
module IBUF_HSTL_I_DCI (O, I);
8110 
output O;
8111 
input I;
8112 
endmodule
8113 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8114 
module IBUF_HSTL_II_18 (O, I);
8115 
output O;
8116 
input I;
8117 
endmodule
8118 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8119 
module IBUF_HSTL_II_DCI_18 (O, I);
8120 
output O;
8121 
input I;
8122 
endmodule
8123 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8124 
module IBUF_HSTL_II_DCI (O, I);
8125 
output O;
8126 
input I;
8127 
endmodule
8128 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8129 
module IBUF_HSTL_III_18 (O, I);
8130 
output O;
8131 
input I;
8132 
endmodule
8133 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8134 
module IBUF_HSTL_III_DCI_18 (O, I);
8135 
output O;
8136 
input I;
8137 
endmodule
8138 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8139 
module IBUF_HSTL_III_DCI (O, I);
8140 
output O;
8141 
input I;
8142 
endmodule
8143 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8144 
module IBUF_HSTL_III (O, I);
8145 
output O;
8146 
input I;
8147 
endmodule
8148 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8149 
module IBUF_HSTL_II (O, I);
8150 
output O;
8151 
input I;
8152 
endmodule
8153 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8154 
module IBUF_HSTL_I (O, I);
8155 
output O;
8156 
input I;
8157 
endmodule
8158 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8159 
module IBUF_HSTL_IV_18 (O, I);
8160 
output O;
8161 
input I;
8162 
endmodule
8163 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8164 
module IBUF_HSTL_IV_DCI_18 (O, I);
8165 
output O;
8166 
input I;
8167 
endmodule
8168 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8169 
module IBUF_HSTL_IV_DCI (O, I);
8170 
output O;
8171 
input I;
8172 
endmodule
8173 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8174 
module IBUF_HSTL_IV (O, I);
8175 
output O;
8176 
input I;
8177 
endmodule
8178 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8179 
module IBUF_LVCMOS12 (O, I);
8180 
output O;
8181 
input I;
8182 
endmodule
8183 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8184 
module IBUF_LVCMOS15 (O, I);
8185 
output O;
8186 
input I;
8187 
endmodule
8188 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8189 
module IBUF_LVCMOS18 (O, I);
8190 
output O;
8191 
input I;
8192 
endmodule
8193 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8194 
module IBUF_LVCMOS25 (O, I);
8195 
output O;
8196 
input I;
8197 
endmodule
8198 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8199 
module IBUF_LVCMOS2 (O, I);
8200 
output O;
8201 
input I;
8202 
endmodule
8203 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8204 
module IBUF_LVCMOS33 (O, I);
8205 
output O;
8206 
input I;
8207 
endmodule
8208 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8209 
module IBUF_LVDCI_15 (O, I);
8210 
output O;
8211 
input I;
8212 
endmodule
8213 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8214 
module IBUF_LVDCI_18 (O, I);
8215 
output O;
8216 
input I;
8217 
endmodule
8218 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8219 
module IBUF_LVDCI_25 (O, I);
8220 
output O;
8221 
input I;
8222 
endmodule
8223 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8224 
module IBUF_LVDCI_33 (O, I);
8225 
output O;
8226 
input I;
8227 
endmodule
8228 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8229 
module IBUF_LVDCI_DV2_15 (O, I);
8230 
output O;
8231 
input I;
8232 
endmodule
8233 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8234 
module IBUF_LVDCI_DV2_18 (O, I);
8235 
output O;
8236 
input I;
8237 
endmodule
8238 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8239 
module IBUF_LVDCI_DV2_25 (O, I);
8240 
output O;
8241 
input I;
8242 
endmodule
8243 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8244 
module IBUF_LVDCI_DV2_33 (O, I);
8245 
output O;
8246 
input I;
8247 
endmodule
8248 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8249 
module IBUF_LVDS (O, I);
8250 
output O;
8251 
input I;
8252 
endmodule
8253 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8254 
module IBUF_LVPECL (O, I);
8255 
output O;
8256 
input I;
8257 
endmodule
8258 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8259 
module IBUF_LVTTL (O, I);
8260 
output O;
8261 
input I;
8262 
endmodule
8263 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8264 
module IBUF_PCI33_3 (O, I);
8265 
output O;
8266 
input I;
8267 
endmodule
8268 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8269 
module IBUF_PCI33_5 (O, I);
8270 
output O;
8271 
input I;
8272 
endmodule
8273 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8274 
module IBUF_PCI66_3 (O, I);
8275 
output O;
8276 
input I;
8277 
endmodule
8278 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8279 
module IBUF_PCIX66_3 (O, I);
8280 
output O;
8281 
input I;
8282 
endmodule
8283 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8284 
module IBUF_PCIX (O, I);
8285 
output O;
8286 
input I;
8287 
endmodule
8288 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8289 
module IBUF_SSTL18_I_DCI (O, I);
8290 
output O;
8291 
input I;
8292 
endmodule
8293 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8294 
module IBUF_SSTL18_II_DCI (O, I);
8295 
output O;
8296 
input I;
8297 
endmodule
8298 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8299 
module IBUF_SSTL18_II (O, I);
8300 
output O;
8301 
input I;
8302 
endmodule
8303 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8304 
module IBUF_SSTL18_I (O, I);
8305 
output O;
8306 
input I;
8307 
endmodule
8308 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8309 
module IBUF_SSTL2_I_DCI (O, I);
8310 
output O;
8311 
input I;
8312 
endmodule
8313 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8314 
module IBUF_SSTL2_II_DCI (O, I);
8315 
output O;
8316 
input I;
8317 
endmodule
8318 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8319 
module IBUF_SSTL2_II (O, I);
8320 
output O;
8321 
input I;
8322 
endmodule
8323 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8324 
module IBUF_SSTL2_I (O, I);
8325 
output O;
8326 
input I;
8327 
endmodule
8328 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8329 
module IBUF_SSTL3_I_DCI (O, I);
8330 
output O;
8331 
input I;
8332 
endmodule
8333 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8334 
module IBUF_SSTL3_II_DCI (O, I);
8335 
output O;
8336 
input I;
8337 
endmodule
8338 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8339 
module IBUF_SSTL3_II (O, I);
8340 
output O;
8341 
input I;
8342 
endmodule
8343 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8344 
module IBUF_SSTL3_I (O, I);
8345 
output O;
8346 
input I;
8347 
endmodule
8348 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8349 
module IBUF (O, I);
8350 
parameter CAPACITANCE = "DONT_CARE";
8351 
parameter IBUF_DELAY_VALUE = "0";
8352 
parameter IFD_DELAY_VALUE = "AUTO";
8353 
parameter IOSTANDARD = "DEFAULT";
8354 
output O;
8355 
input I;
8356 
endmodule
8357 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8358 
module ICAP_SPARTAN3A (BUSY, O, CE, CLK, I, WRITE);
8359 
output BUSY;
8360 
output [7:0] O;
8361 
input CE;
8362 
input CLK;
8363 
input [7:0] I;
8364 
input WRITE;
8365 
endmodule
8366 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8367 
module ICAP_VIRTEX2 (BUSY, O, CE, CLK, I, WRITE);
8368 
output BUSY;
8369 
output [7:0] O;
8370 
input CE;
8371 
input CLK;
8372 
input [7:0] I;
8373 
input WRITE;
8374 
endmodule
8375 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8376 
module ICAP_VIRTEX4 (BUSY, O, CE, CLK, I, WRITE);
8377 
parameter ICAP_WIDTH = "X8";
8378 
output BUSY;
8379 
output [31:0] O;
8380 
input CE;
8381 
input CLK;
8382 
input [31:0] I;
8383 
input WRITE;
8384 
endmodule
8385 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8386 
module ICAP_VIRTEX5 (BUSY, O, CE, CLK, I, WRITE);
8387 
parameter ICAP_WIDTH = "X8";
8388 
output BUSY;
8389 
output [31:0] O;
8390 
input CE;
8391 
input CLK;
8392 
input [31:0] I;
8393 
input WRITE;
8394 
endmodule
8395 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8396 
module IDDR_2CLK (Q1, Q2, C, CB, CE, D, R, S);
8397 
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
8398 
parameter INIT_Q1 = 1'b0;
8399 
parameter INIT_Q2 = 1'b0;
8400 
parameter SRTYPE = "SYNC";
8401 
output Q1;
8402 
output Q2;
8403 
input C;
8404 
input CB;
8405 
input CE;
8406 
input D;
8407 
input R;
8408 
input S;
8409 
endmodule
8410 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8411 
module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
8412 
parameter DDR_ALIGNMENT = "NONE";
8413 
parameter INIT_Q0 = 1'b0;
8414 
parameter INIT_Q1 = 1'b0;
8415 
parameter SRTYPE = "SYNC";
8416 
output Q0;
8417 
output Q1;
8418 
input C0;
8419 
input C1;
8420 
input CE;
8421 
input D;
8422 
input R;
8423 
input S;
8424 
endmodule
8425 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8426 
module IDDR (Q1, Q2, C, CE, D, R, S);
8427 
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
8428 
parameter INIT_Q1 = 1'b0;
8429 
parameter INIT_Q2 = 1'b0;
8430 
parameter SRTYPE = "SYNC";
8431 
output Q1;
8432 
output Q2;
8433 
input C;
8434 
input CE;
8435 
input D;
8436 
input R;
8437 
input S;
8438 
endmodule
8439 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8440 
module IDELAYCTRL (RDY, REFCLK, RST);
8441 
output RDY;
8442 
input REFCLK;
8443 
input RST;
8444 
endmodule
8445 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8446 
module IDELAY (O, C, CE, I, INC, RST);
8447 
parameter IOBDELAY_TYPE = "DEFAULT";
8448 
parameter integer IOBDELAY_VALUE = 0;
8449 
output O;
8450 
input C;
8451 
input CE;
8452 
input I;
8453 
input INC;
8454 
input RST;
8455 
endmodule
8456 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8457 
module IFDDRCPE (Q0, Q1, C0, C1, CE, CLR, D, PRE);
8458 
output Q0;
8459 
output Q1;
8460 
input C0;
8461 
input C1;
8462 
input CE;
8463 
input CLR;
8464 
input D;
8465 
input PRE;
8466 
endmodule
8467 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8468 
module IFDDRRSE (Q0, Q1, C0, C1, CE, D, R, S);
8469 
output Q0;
8470 
output Q1;
8471 
input C0;
8472 
input C1;
8473 
input CE;
8474 
input D;
8475 
input R;
8476 
input S;
8477 
endmodule
8478 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8479 
module ILD (Q, D, G);
8480 
output Q;
8481 
input D;
8482 
input G;
8483 
endmodule
8484 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8485 
module INV (O, I);
8486 
output O;
8487 
input I;
8488 
endmodule
8489 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8490 
module IOBUF_AGP (O, IO, I, T);
8491 
output O;
8492 
inout IO;
8493 
input I;
8494 
input T;
8495 
endmodule
8496 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8497 
module IOBUF_CTT (O, IO, I, T);
8498 
output O;
8499 
inout IO;
8500 
input I;
8501 
input T;
8502 
endmodule
8503 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8504 
module IOBUFDS_BLVDS_25 (O, IO, IOB, I, T);
8505 
output O;
8506 
inout IO;
8507 
inout IOB;
8508 
input I;
8509 
input T;
8510 
endmodule
8511 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8512 
module IOBUFDS (O, IO, IOB, I, T);
8513 
parameter CAPACITANCE = "DONT_CARE";
8514 
parameter IBUF_DELAY_VALUE = "0";
8515 
parameter IFD_DELAY_VALUE = "AUTO";
8516 
parameter IOSTANDARD = "DEFAULT";
8517 
output O;
8518 
inout IO;
8519 
inout IOB;
8520 
input I;
8521 
input T;
8522 
endmodule
8523 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8524 
module IOBUFE_F (O, IO, I, E);
8525 
output O;
8526 
inout IO;
8527 
input I;
8528 
input E;
8529 
endmodule
8530 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8531 
module IOBUFE_S (O, IO, I, E);
8532 
output O;
8533 
inout IO;
8534 
input I;
8535 
input E;
8536 
endmodule
8537 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8538 
module IOBUFE (O, IO, I, E);
8539 
output O;
8540 
inout IO;
8541 
input I;
8542 
input E;
8543 
endmodule
8544 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8545 
module IOBUF_F_12 (O, IO, I, T);
8546 
output O;
8547 
inout IO;
8548 
input I;
8549 
input T;
8550 
endmodule
8551 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8552 
module IOBUF_F_16 (O, IO, I, T);
8553 
output O;
8554 
inout IO;
8555 
input I;
8556 
input T;
8557 
endmodule
8558 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8559 
module IOBUF_F_24 (O, IO, I, T);
8560 
output O;
8561 
inout IO;
8562 
input I;
8563 
input T;
8564 
endmodule
8565 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8566 
module IOBUF_F_2 (O, IO, I, T);
8567 
output O;
8568 
inout IO;
8569 
input I;
8570 
input T;
8571 
endmodule
8572 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8573 
module IOBUF_F_4 (O, IO, I, T);
8574 
output O;
8575 
inout IO;
8576 
input I;
8577 
input T;
8578 
endmodule
8579 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8580 
module IOBUF_F_6 (O, IO, I, T);
8581 
output O;
8582 
inout IO;
8583 
input I;
8584 
input T;
8585 
endmodule
8586 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8587 
module IOBUF_F_8 (O, IO, I, T);
8588 
output O;
8589 
inout IO;
8590 
input I;
8591 
input T;
8592 
endmodule
8593 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8594 
module IOBUF_GTL_DCI (O, IO, I, T);
8595 
output O;
8596 
inout IO;
8597 
input I;
8598 
input T;
8599 
endmodule
8600 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8601 
module IOBUF_GTLP_DCI (O, IO, I, T);
8602 
output O;
8603 
inout IO;
8604 
input I;
8605 
input T;
8606 
endmodule
8607 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8608 
module IOBUF_GTLP (O, IO, I, T);
8609 
output O;
8610 
inout IO;
8611 
input I;
8612 
input T;
8613 
endmodule
8614 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8615 
module IOBUF_GTL (O, IO, I, T);
8616 
output O;
8617 
inout IO;
8618 
input I;
8619 
input T;
8620 
endmodule
8621 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8622 
module IOBUF_HSTL_I_18 (O, IO, I, T);
8623 
output O;
8624 
inout IO;
8625 
input I;
8626 
input T;
8627 
endmodule
8628 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8629 
module IOBUF_HSTL_II_18 (O, IO, I, T);
8630 
output O;
8631 
inout IO;
8632 
input I;
8633 
input T;
8634 
endmodule
8635 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8636 
module IOBUF_HSTL_II_DCI_18 (O, IO, I, T);
8637 
output O;
8638 
inout IO;
8639 
input I;
8640 
input T;
8641 
endmodule
8642 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8643 
module IOBUF_HSTL_II_DCI (O, IO, I, T);
8644 
output O;
8645 
inout IO;
8646 
input I;
8647 
input T;
8648 
endmodule
8649 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8650 
module IOBUF_HSTL_III_18 (O, IO, I, T);
8651 
output O;
8652 
inout IO;
8653 
input I;
8654 
input T;
8655 
endmodule
8656 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8657 
module IOBUF_HSTL_III (O, IO, I, T);
8658 
output O;
8659 
inout IO;
8660 
input I;
8661 
input T;
8662 
endmodule
8663 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8664 
module IOBUF_HSTL_II (O, IO, I, T);
8665 
output O;
8666 
inout IO;
8667 
input I;
8668 
input T;
8669 
endmodule
8670 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8671 
module IOBUF_HSTL_I (O, IO, I, T);
8672 
output O;
8673 
inout IO;
8674 
input I;
8675 
input T;
8676 
endmodule
8677 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8678 
module IOBUF_HSTL_IV_18 (O, IO, I, T);
8679 
output O;
8680 
inout IO;
8681 
input I;
8682 
input T;
8683 
endmodule
8684 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8685 
module IOBUF_HSTL_IV_DCI_18 (O, IO, I, T);
8686 
output O;
8687 
inout IO;
8688 
input I;
8689 
input T;
8690 
endmodule
8691 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8692 
module IOBUF_HSTL_IV_DCI (O, IO, I, T);
8693 
output O;
8694 
inout IO;
8695 
input I;
8696 
input T;
8697 
endmodule
8698 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8699 
module IOBUF_HSTL_IV (O, IO, I, T);
8700 
output O;
8701 
inout IO;
8702 
input I;
8703 
input T;
8704 
endmodule
8705 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8706 
module IOBUF_LVCMOS12_F_2 (O, IO, I, T);
8707 
output O;
8708 
inout IO;
8709 
input I;
8710 
input T;
8711 
endmodule
8712 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8713 
module IOBUF_LVCMOS12_F_4 (O, IO, I, T);
8714 
output O;
8715 
inout IO;
8716 
input I;
8717 
input T;
8718 
endmodule
8719 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8720 
module IOBUF_LVCMOS12_F_6 (O, IO, I, T);
8721 
output O;
8722 
inout IO;
8723 
input I;
8724 
input T;
8725 
endmodule
8726 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8727 
module IOBUF_LVCMOS12_F_8 (O, IO, I, T);
8728 
output O;
8729 
inout IO;
8730 
input I;
8731 
input T;
8732 
endmodule
8733 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8734 
module IOBUF_LVCMOS12_S_2 (O, IO, I, T);
8735 
output O;
8736 
inout IO;
8737 
input I;
8738 
input T;
8739 
endmodule
8740 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8741 
module IOBUF_LVCMOS12_S_4 (O, IO, I, T);
8742 
output O;
8743 
inout IO;
8744 
input I;
8745 
input T;
8746 
endmodule
8747 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8748 
module IOBUF_LVCMOS12_S_6 (O, IO, I, T);
8749 
output O;
8750 
inout IO;
8751 
input I;
8752 
input T;
8753 
endmodule
8754 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8755 
module IOBUF_LVCMOS12_S_8 (O, IO, I, T);
8756 
output O;
8757 
inout IO;
8758 
input I;
8759 
input T;
8760 
endmodule
8761 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8762 
module IOBUF_LVCMOS12 (O, IO, I, T);
8763 
output O;
8764 
inout IO;
8765 
input I;
8766 
input T;
8767 
endmodule
8768 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8769 
module IOBUF_LVCMOS15_F_12 (O, IO, I, T);
8770 
output O;
8771 
inout IO;
8772 
input I;
8773 
input T;
8774 
endmodule
8775 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8776 
module IOBUF_LVCMOS15_F_16 (O, IO, I, T);
8777 
output O;
8778 
inout IO;
8779 
input I;
8780 
input T;
8781 
endmodule
8782 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8783 
module IOBUF_LVCMOS15_F_2 (O, IO, I, T);
8784 
output O;
8785 
inout IO;
8786 
input I;
8787 
input T;
8788 
endmodule
8789 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8790 
module IOBUF_LVCMOS15_F_4 (O, IO, I, T);
8791 
output O;
8792 
inout IO;
8793 
input I;
8794 
input T;
8795 
endmodule
8796 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8797 
module IOBUF_LVCMOS15_F_6 (O, IO, I, T);
8798 
output O;
8799 
inout IO;
8800 
input I;
8801 
input T;
8802 
endmodule
8803 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8804 
module IOBUF_LVCMOS15_F_8 (O, IO, I, T);
8805 
output O;
8806 
inout IO;
8807 
input I;
8808 
input T;
8809 
endmodule
8810 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8811 
module IOBUF_LVCMOS15_S_12 (O, IO, I, T);
8812 
output O;
8813 
inout IO;
8814 
input I;
8815 
input T;
8816 
endmodule
8817 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8818 
module IOBUF_LVCMOS15_S_16 (O, IO, I, T);
8819 
output O;
8820 
inout IO;
8821 
input I;
8822 
input T;
8823 
endmodule
8824 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8825 
module IOBUF_LVCMOS15_S_2 (O, IO, I, T);
8826 
output O;
8827 
inout IO;
8828 
input I;
8829 
input T;
8830 
endmodule
8831 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8832 
module IOBUF_LVCMOS15_S_4 (O, IO, I, T);
8833 
output O;
8834 
inout IO;
8835 
input I;
8836 
input T;
8837 
endmodule
8838 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8839 
module IOBUF_LVCMOS15_S_6 (O, IO, I, T);
8840 
output O;
8841 
inout IO;
8842 
input I;
8843 
input T;
8844 
endmodule
8845 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8846 
module IOBUF_LVCMOS15_S_8 (O, IO, I, T);
8847 
output O;
8848 
inout IO;
8849 
input I;
8850 
input T;
8851 
endmodule
8852 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8853 
module IOBUF_LVCMOS15 (O, IO, I, T);
8854 
output O;
8855 
inout IO;
8856 
input I;
8857 
input T;
8858 
endmodule
8859 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8860 
module IOBUF_LVCMOS18_F_12 (O, IO, I, T);
8861 
output O;
8862 
inout IO;
8863 
input I;
8864 
input T;
8865 
endmodule
8866 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8867 
module IOBUF_LVCMOS18_F_16 (O, IO, I, T);
8868 
output O;
8869 
inout IO;
8870 
input I;
8871 
input T;
8872 
endmodule
8873 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8874 
module IOBUF_LVCMOS18_F_2 (O, IO, I, T);
8875 
output O;
8876 
inout IO;
8877 
input I;
8878 
input T;
8879 
endmodule
8880 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8881 
module IOBUF_LVCMOS18_F_4 (O, IO, I, T);
8882 
output O;
8883 
inout IO;
8884 
input I;
8885 
input T;
8886 
endmodule
8887 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8888 
module IOBUF_LVCMOS18_F_6 (O, IO, I, T);
8889 
output O;
8890 
inout IO;
8891 
input I;
8892 
input T;
8893 
endmodule
8894 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8895 
module IOBUF_LVCMOS18_F_8 (O, IO, I, T);
8896 
output O;
8897 
inout IO;
8898 
input I;
8899 
input T;
8900 
endmodule
8901 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8902 
module IOBUF_LVCMOS18_S_12 (O, IO, I, T);
8903 
output O;
8904 
inout IO;
8905 
input I;
8906 
input T;
8907 
endmodule
8908 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8909 
module IOBUF_LVCMOS18_S_16 (O, IO, I, T);
8910 
output O;
8911 
inout IO;
8912 
input I;
8913 
input T;
8914 
endmodule
8915 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8916 
module IOBUF_LVCMOS18_S_2 (O, IO, I, T);
8917 
output O;
8918 
inout IO;
8919 
input I;
8920 
input T;
8921 
endmodule
8922 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8923 
module IOBUF_LVCMOS18_S_4 (O, IO, I, T);
8924 
output O;
8925 
inout IO;
8926 
input I;
8927 
input T;
8928 
endmodule
8929 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8930 
module IOBUF_LVCMOS18_S_6 (O, IO, I, T);
8931 
output O;
8932 
inout IO;
8933 
input I;
8934 
input T;
8935 
endmodule
8936 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8937 
module IOBUF_LVCMOS18_S_8 (O, IO, I, T);
8938 
output O;
8939 
inout IO;
8940 
input I;
8941 
input T;
8942 
endmodule
8943 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8944 
module IOBUF_LVCMOS18 (O, IO, I, T);
8945 
output O;
8946 
inout IO;
8947 
input I;
8948 
input T;
8949 
endmodule
8950 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8951 
module IOBUF_LVCMOS25_F_12 (O, IO, I, T);
8952 
output O;
8953 
inout IO;
8954 
input I;
8955 
input T;
8956 
endmodule
8957 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8958 
module IOBUF_LVCMOS25_F_16 (O, IO, I, T);
8959 
output O;
8960 
inout IO;
8961 
input I;
8962 
input T;
8963 
endmodule
8964 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8965 
module IOBUF_LVCMOS25_F_24 (O, IO, I, T);
8966 
output O;
8967 
inout IO;
8968 
input I;
8969 
input T;
8970 
endmodule
8971 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8972 
module IOBUF_LVCMOS25_F_2 (O, IO, I, T);
8973 
output O;
8974 
inout IO;
8975 
input I;
8976 
input T;
8977 
endmodule
8978 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8979 
module IOBUF_LVCMOS25_F_4 (O, IO, I, T);
8980 
output O;
8981 
inout IO;
8982 
input I;
8983 
input T;
8984 
endmodule
8985 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8986 
module IOBUF_LVCMOS25_F_6 (O, IO, I, T);
8987 
output O;
8988 
inout IO;
8989 
input I;
8990 
input T;
8991 
endmodule
8992 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
8993 
module IOBUF_LVCMOS25_F_8 (O, IO, I, T);
8994 
output O;
8995 
inout IO;
8996 
input I;
8997 
input T;
8998 
endmodule
8999 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9000 
module IOBUF_LVCMOS25_S_12 (O, IO, I, T);
9001 
output O;
9002 
inout IO;
9003 
input I;
9004 
input T;
9005 
endmodule
9006 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9007 
module IOBUF_LVCMOS25_S_16 (O, IO, I, T);
9008 
output O;
9009 
inout IO;
9010 
input I;
9011 
input T;
9012 
endmodule
9013 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9014 
module IOBUF_LVCMOS25_S_24 (O, IO, I, T);
9015 
output O;
9016 
inout IO;
9017 
input I;
9018 
input T;
9019 
endmodule
9020 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9021 
module IOBUF_LVCMOS25_S_2 (O, IO, I, T);
9022 
output O;
9023 
inout IO;
9024 
input I;
9025 
input T;
9026 
endmodule
9027 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9028 
module IOBUF_LVCMOS25_S_4 (O, IO, I, T);
9029 
output O;
9030 
inout IO;
9031 
input I;
9032 
input T;
9033 
endmodule
9034 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9035 
module IOBUF_LVCMOS25_S_6 (O, IO, I, T);
9036 
output O;
9037 
inout IO;
9038 
input I;
9039 
input T;
9040 
endmodule
9041 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9042 
module IOBUF_LVCMOS25_S_8 (O, IO, I, T);
9043 
output O;
9044 
inout IO;
9045 
input I;
9046 
input T;
9047 
endmodule
9048 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9049 
module IOBUF_LVCMOS25 (O, IO, I, T);
9050 
output O;
9051 
inout IO;
9052 
input I;
9053 
input T;
9054 
endmodule
9055 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9056 
module IOBUF_LVCMOS2 (O, IO, I, T);
9057 
output O;
9058 
inout IO;
9059 
input I;
9060 
input T;
9061 
endmodule
9062 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9063 
module IOBUF_LVCMOS33_F_12 (O, IO, I, T);
9064 
output O;
9065 
inout IO;
9066 
input I;
9067 
input T;
9068 
endmodule
9069 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9070 
module IOBUF_LVCMOS33_F_16 (O, IO, I, T);
9071 
output O;
9072 
inout IO;
9073 
input I;
9074 
input T;
9075 
endmodule
9076 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9077 
module IOBUF_LVCMOS33_F_24 (O, IO, I, T);
9078 
output O;
9079 
inout IO;
9080 
input I;
9081 
input T;
9082 
endmodule
9083 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9084 
module IOBUF_LVCMOS33_F_2 (O, IO, I, T);
9085 
output O;
9086 
inout IO;
9087 
input I;
9088 
input T;
9089 
endmodule
9090 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9091 
module IOBUF_LVCMOS33_F_4 (O, IO, I, T);
9092 
output O;
9093 
inout IO;
9094 
input I;
9095 
input T;
9096 
endmodule
9097 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9098 
module IOBUF_LVCMOS33_F_6 (O, IO, I, T);
9099 
output O;
9100 
inout IO;
9101 
input I;
9102 
input T;
9103 
endmodule
9104 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9105 
module IOBUF_LVCMOS33_F_8 (O, IO, I, T);
9106 
output O;
9107 
inout IO;
9108 
input I;
9109 
input T;
9110 
endmodule
9111 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9112 
module IOBUF_LVCMOS33_S_12 (O, IO, I, T);
9113 
output O;
9114 
inout IO;
9115 
input I;
9116 
input T;
9117 
endmodule
9118 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9119 
module IOBUF_LVCMOS33_S_16 (O, IO, I, T);
9120 
output O;
9121 
inout IO;
9122 
input I;
9123 
input T;
9124 
endmodule
9125 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9126 
module IOBUF_LVCMOS33_S_24 (O, IO, I, T);
9127 
output O;
9128 
inout IO;
9129 
input I;
9130 
input T;
9131 
endmodule
9132 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9133 
module IOBUF_LVCMOS33_S_2 (O, IO, I, T);
9134 
output O;
9135 
inout IO;
9136 
input I;
9137 
input T;
9138 
endmodule
9139 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9140 
module IOBUF_LVCMOS33_S_4 (O, IO, I, T);
9141 
output O;
9142 
inout IO;
9143 
input I;
9144 
input T;
9145 
endmodule
9146 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9147 
module IOBUF_LVCMOS33_S_6 (O, IO, I, T);
9148 
output O;
9149 
inout IO;
9150 
input I;
9151 
input T;
9152 
endmodule
9153 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9154 
module IOBUF_LVCMOS33_S_8 (O, IO, I, T);
9155 
output O;
9156 
inout IO;
9157 
input I;
9158 
input T;
9159 
endmodule
9160 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9161 
module IOBUF_LVCMOS33 (O, IO, I, T);
9162 
output O;
9163 
inout IO;
9164 
input I;
9165 
input T;
9166 
endmodule
9167 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9168 
module IOBUF_LVDCI_15 (O, IO, I, T);
9169 
output O;
9170 
inout IO;
9171 
input I;
9172 
input T;
9173 
endmodule
9174 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9175 
module IOBUF_LVDCI_18 (O, IO, I, T);
9176 
output O;
9177 
inout IO;
9178 
input I;
9179 
input T;
9180 
endmodule
9181 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9182 
module IOBUF_LVDCI_25 (O, IO, I, T);
9183 
output O;
9184 
inout IO;
9185 
input I;
9186 
input T;
9187 
endmodule
9188 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9189 
module IOBUF_LVDCI_33 (O, IO, I, T);
9190 
output O;
9191 
inout IO;
9192 
input I;
9193 
input T;
9194 
endmodule
9195 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9196 
module IOBUF_LVDCI_DV2_15 (O, IO, I, T);
9197 
output O;
9198 
inout IO;
9199 
input I;
9200 
input T;
9201 
endmodule
9202 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9203 
module IOBUF_LVDCI_DV2_18 (O, IO, I, T);
9204 
output O;
9205 
inout IO;
9206 
input I;
9207 
input T;
9208 
endmodule
9209 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9210 
module IOBUF_LVDCI_DV2_25 (O, IO, I, T);
9211 
output O;
9212 
inout IO;
9213 
input I;
9214 
input T;
9215 
endmodule
9216 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9217 
module IOBUF_LVDCI_DV2_33 (O, IO, I, T);
9218 
output O;
9219 
inout IO;
9220 
input I;
9221 
input T;
9222 
endmodule
9223 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9224 
module IOBUF_LVDS (O, IO, I, T);
9225 
output O;
9226 
inout IO;
9227 
input I;
9228 
input T;
9229 
endmodule
9230 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9231 
module IOBUF_LVPECL (O, IO, I, T);
9232 
output O;
9233 
inout IO;
9234 
input I;
9235 
input T;
9236 
endmodule
9237 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9238 
module IOBUF_LVTTL_F_12 (O, IO, I, T);
9239 
output O;
9240 
inout IO;
9241 
input I;
9242 
input T;
9243 
endmodule
9244 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9245 
module IOBUF_LVTTL_F_16 (O, IO, I, T);
9246 
output O;
9247 
inout IO;
9248 
input I;
9249 
input T;
9250 
endmodule
9251 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9252 
module IOBUF_LVTTL_F_24 (O, IO, I, T);
9253 
output O;
9254 
inout IO;
9255 
input I;
9256 
input T;
9257 
endmodule
9258 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9259 
module IOBUF_LVTTL_F_2 (O, IO, I, T);
9260 
output O;
9261 
inout IO;
9262 
input I;
9263 
input T;
9264 
endmodule
9265 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9266 
module IOBUF_LVTTL_F_4 (O, IO, I, T);
9267 
output O;
9268 
inout IO;
9269 
input I;
9270 
input T;
9271 
endmodule
9272 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9273 
module IOBUF_LVTTL_F_6 (O, IO, I, T);
9274 
output O;
9275 
inout IO;
9276 
input I;
9277 
input T;
9278 
endmodule
9279 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9280 
module IOBUF_LVTTL_F_8 (O, IO, I, T);
9281 
output O;
9282 
inout IO;
9283 
input I;
9284 
input T;
9285 
endmodule
9286 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9287 
module IOBUF_LVTTL_S_12 (O, IO, I, T);
9288 
output O;
9289 
inout IO;
9290 
input I;
9291 
input T;
9292 
endmodule
9293 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9294 
module IOBUF_LVTTL_S_16 (O, IO, I, T);
9295 
output O;
9296 
inout IO;
9297 
input I;
9298 
input T;
9299 
endmodule
9300 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9301 
module IOBUF_LVTTL_S_24 (O, IO, I, T);
9302 
output O;
9303 
inout IO;
9304 
input I;
9305 
input T;
9306 
endmodule
9307 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9308 
module IOBUF_LVTTL_S_2 (O, IO, I, T);
9309 
output O;
9310 
inout IO;
9311 
input I;
9312 
input T;
9313 
endmodule
9314 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9315 
module IOBUF_LVTTL_S_4 (O, IO, I, T);
9316 
output O;
9317 
inout IO;
9318 
input I;
9319 
input T;
9320 
endmodule
9321 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9322 
module IOBUF_LVTTL_S_6 (O, IO, I, T);
9323 
output O;
9324 
inout IO;
9325 
input I;
9326 
input T;
9327 
endmodule
9328 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9329 
module IOBUF_LVTTL_S_8 (O, IO, I, T);
9330 
output O;
9331 
inout IO;
9332 
input I;
9333 
input T;
9334 
endmodule
9335 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9336 
module IOBUF_LVTTL (O, IO, I, T);
9337 
output O;
9338 
inout IO;
9339 
input I;
9340 
input T;
9341 
endmodule
9342 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9343 
module IOBUF_PCI33_3 (O, IO, I, T);
9344 
output O;
9345 
inout IO;
9346 
input I;
9347 
input T;
9348 
endmodule
9349 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9350 
module IOBUF_PCI33_5 (O, IO, I, T);
9351 
output O;
9352 
inout IO;
9353 
input I;
9354 
input T;
9355 
endmodule
9356 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9357 
module IOBUF_PCI66_3 (O, IO, I, T);
9358 
output O;
9359 
inout IO;
9360 
input I;
9361 
input T;
9362 
endmodule
9363 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9364 
module IOBUF_PCIX66_3 (O, IO, I, T);
9365 
output O;
9366 
inout IO;
9367 
input I;
9368 
input T;
9369 
endmodule
9370 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9371 
module IOBUF_PCIX (O, IO, I, T);
9372 
output O;
9373 
inout IO;
9374 
input I;
9375 
input T;
9376 
endmodule
9377 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9378 
module IOBUF_S_12 (O, IO, I, T);
9379 
output O;
9380 
inout IO;
9381 
input I;
9382 
input T;
9383 
endmodule
9384 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9385 
module IOBUF_S_16 (O, IO, I, T);
9386 
output O;
9387 
inout IO;
9388 
input I;
9389 
input T;
9390 
endmodule
9391 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9392 
module IOBUF_S_24 (O, IO, I, T);
9393 
output O;
9394 
inout IO;
9395 
input I;
9396 
input T;
9397 
endmodule
9398 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9399 
module IOBUF_S_2 (O, IO, I, T);
9400 
output O;
9401 
inout IO;
9402 
input I;
9403 
input T;
9404 
endmodule
9405 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9406 
module IOBUF_S_4 (O, IO, I, T);
9407 
output O;
9408 
inout IO;
9409 
input I;
9410 
input T;
9411 
endmodule
9412 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9413 
module IOBUF_S_6 (O, IO, I, T);
9414 
output O;
9415 
inout IO;
9416 
input I;
9417 
input T;
9418 
endmodule
9419 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9420 
module IOBUF_S_8 (O, IO, I, T);
9421 
output O;
9422 
inout IO;
9423 
input I;
9424 
input T;
9425 
endmodule
9426 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9427 
module IOBUF_SSTL18_II_DCI (O, IO, I, T);
9428 
output O;
9429 
inout IO;
9430 
input I;
9431 
input T;
9432 
endmodule
9433 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9434 
module IOBUF_SSTL18_II (O, IO, I, T);
9435 
output O;
9436 
inout IO;
9437 
input I;
9438 
input T;
9439 
endmodule
9440 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9441 
module IOBUF_SSTL18_I (O, IO, I, T);
9442 
output O;
9443 
inout IO;
9444 
input I;
9445 
input T;
9446 
endmodule
9447 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9448 
module IOBUF_SSTL2_II_DCI (O, IO, I, T);
9449 
output O;
9450 
inout IO;
9451 
input I;
9452 
input T;
9453 
endmodule
9454 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9455 
module IOBUF_SSTL2_II (O, IO, I, T);
9456 
output O;
9457 
inout IO;
9458 
input I;
9459 
input T;
9460 
endmodule
9461 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9462 
module IOBUF_SSTL2_I (O, IO, I, T);
9463 
output O;
9464 
inout IO;
9465 
input I;
9466 
input T;
9467 
endmodule
9468 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9469 
module IOBUF_SSTL3_II_DCI (O, IO, I, T);
9470 
output O;
9471 
inout IO;
9472 
input I;
9473 
input T;
9474 
endmodule
9475 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9476 
module IOBUF_SSTL3_II (O, IO, I, T);
9477 
output O;
9478 
inout IO;
9479 
input I;
9480 
input T;
9481 
endmodule
9482 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9483 
module IOBUF_SSTL3_I (O, IO, I, T);
9484 
output O;
9485 
inout IO;
9486 
input I;
9487 
input T;
9488 
endmodule
9489 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9490 
module IOBUF (O, IO, I, T);
9491 
parameter CAPACITANCE = "DONT_CARE";
9492 
parameter integer DRIVE = 12;
9493 
parameter IBUF_DELAY_VALUE = "0";
9494 
parameter IFD_DELAY_VALUE = "AUTO";
9495 
parameter IOSTANDARD = "DEFAULT";
9496 
parameter SLEW = "SLOW";
9497 
output O;
9498 
inout IO;
9499 
input I;
9500 
input T;
9501 
endmodule
9502 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9503 
module IODELAY (DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T);
9504 
parameter DELAY_SRC = "I";
9505 
parameter HIGH_PERFORMANCE_MODE = "TRUE";
9506 
parameter IDELAY_TYPE = "DEFAULT";
9507 
parameter integer IDELAY_VALUE = 0;
9508 
parameter integer ODELAY_VALUE = 0;
9509 
parameter real REFCLK_FREQUENCY = 200.0;
9510 
parameter SIGNAL_PATTERN = "DATA";
9511 
output DATAOUT;
9512 
input C;
9513 
input CE;
9514 
input DATAIN;
9515 
input IDATAIN;
9516 
input INC;
9517 
input ODATAIN;
9518 
input RST;
9519 
input T;
9520 
endmodule
9521 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9522 
module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
9523 
parameter BITSLIP_ENABLE = "FALSE";
9524 
parameter DATA_RATE = "DDR";
9525 
parameter integer DATA_WIDTH = 4;
9526 
parameter INIT_Q1 = 1'b0;
9527 
parameter INIT_Q2 = 1'b0;
9528 
parameter INIT_Q3 = 1'b0;
9529 
parameter INIT_Q4 = 1'b0;
9530 
parameter INTERFACE_TYPE = "MEMORY";
9531 
parameter integer NUM_CE = 2;
9532 
parameter SERDES_MODE = "MASTER";
9533 
output Q1;
9534 
output Q2;
9535 
output Q3;
9536 
output Q4;
9537 
output Q5;
9538 
output Q6;
9539 
output SHIFTOUT1;
9540 
output SHIFTOUT2;
9541 
input BITSLIP;
9542 
input CE1;
9543 
input CE2;
9544 
input CLK;
9545 
input CLKB;
9546 
input CLKDIV;
9547 
input D;
9548 
input OCLK;
9549 
input RST;
9550 
input SHIFTIN1;
9551 
input SHIFTIN2;
9552 
endmodule
9553 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9554 
module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR);
9555 
parameter BITSLIP_ENABLE = "FALSE";
9556 
parameter DATA_RATE = "DDR";
9557 
parameter integer DATA_WIDTH = 4;
9558 
parameter INIT_Q1 = 1'b0;
9559 
parameter INIT_Q2 = 1'b0;
9560 
parameter INIT_Q3 = 1'b0;
9561 
parameter INIT_Q4 = 1'b0;
9562 
parameter INTERFACE_TYPE = "MEMORY";
9563 
parameter IOBDELAY = "NONE";
9564 
parameter IOBDELAY_TYPE = "DEFAULT";
9565 
parameter integer IOBDELAY_VALUE = 0;
9566 
parameter integer NUM_CE = 2;
9567 
parameter SERDES_MODE = "MASTER";
9568 
parameter SRVAL_Q1 = 1'b0;
9569 
parameter SRVAL_Q2 = 1'b0;
9570 
parameter SRVAL_Q3 = 1'b0;
9571 
parameter SRVAL_Q4 = 1'b0;
9572 
output O;
9573 
output Q1;
9574 
output Q2;
9575 
output Q3;
9576 
output Q4;
9577 
output Q5;
9578 
output Q6;
9579 
output SHIFTOUT1;
9580 
output SHIFTOUT2;
9581 
input BITSLIP;
9582 
input CE1;
9583 
input CE2;
9584 
input CLK;
9585 
input CLKDIV;
9586 
input D;
9587 
input DLYCE;
9588 
input DLYINC;
9589 
input DLYRST;
9590 
input OCLK;
9591 
input REV;
9592 
input SHIFTIN1;
9593 
input SHIFTIN2;
9594 
input SR;
9595 
endmodule
9596 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9597 
module JTAGPPC440 (TCK, TDIPPC, TMS, TDOPPC);
9598 
output TCK;
9599 
output TDIPPC;
9600 
output TMS;
9601 
input TDOPPC;
9602 
endmodule
9603 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9604 
module JTAGPPC (TCK, TDIPPC, TMS, TDOPPC, TDOTSPPC);
9605 
output TCK;
9606 
output TDIPPC;
9607 
output TMS;
9608 
input TDOPPC;
9609 
input TDOTSPPC;
9610 
endmodule
9611 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9612 
module JTAG_SIM_SPARTAN3A (TDO, TCK, TDI, TMS);
9613 
parameter PART_NAME = "3S200A";
9614 
output TDO;
9615 
input TCK;
9616 
input TDI;
9617 
input TMS;
9618 
endmodule
9619 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9620 
module JTAG_SIM_VIRTEX4 (TDO, TCK, TDI, TMS);
9621 
parameter PART_NAME = "LX15";
9622 
output TDO;
9623 
input TCK;
9624 
input TDI;
9625 
input TMS;
9626 
endmodule
9627 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9628 
module JTAG_SIM_VIRTEX5 (TDO, TCK, TDI, TMS);
9629 
parameter PART_NAME = "LX30";
9630 
output TDO;
9631 
input TCK;
9632 
input TDI;
9633 
input TMS;
9634 
endmodule
9635 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9636 
module KEEPER (O);
9637 
inout O;
9638 
endmodule
9639 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9640 
module KEEP (O, I);
9641 
output O;
9642 
input I;
9643 
endmodule
9644 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9645 
module KEY_CLEAR (KEYCLEARB);
9646 
input KEYCLEARB;
9647 
endmodule
9648 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9649 
module LD_1 (Q, D, G);
9650 
parameter INIT = 1'b0;
9651 
output Q;
9652 
input D;
9653 
input G;
9654 
endmodule
9655 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9656 
module LDC_1 (Q, CLR, D, G);
9657 
parameter INIT = 1'b0;
9658 
output Q;
9659 
input CLR;
9660 
input D;
9661 
input G;
9662 
endmodule
9663 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9664 
module LDCE_1 (Q, CLR, D, G, GE);
9665 
parameter INIT = 1'b0;
9666 
output Q;
9667 
input CLR;
9668 
input D;
9669 
input G;
9670 
input GE;
9671 
endmodule
9672 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9673 
module LDCE (Q, CLR, D, G, GE);
9674 
parameter INIT = 1'b0;
9675 
output Q;
9676 
input CLR;
9677 
input D;
9678 
input G;
9679 
input GE;
9680 
endmodule
9681 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9682 
module LDCP_1 (Q, CLR, D, G, PRE);
9683 
parameter INIT = 1'b0;
9684 
output Q;
9685 
input CLR;
9686 
input D;
9687 
input G;
9688 
input PRE;
9689 
endmodule
9690 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9691 
module LDCPE_1 (Q, CLR, D, G, GE, PRE);
9692 
parameter INIT = 1'b0;
9693 
output Q;
9694 
input CLR;
9695 
input D;
9696 
input G;
9697 
input GE;
9698 
input PRE;
9699 
endmodule
9700 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9701 
module LDCPE (Q, CLR, D, G, GE, PRE);
9702 
parameter INIT = 1'b0;
9703 
output Q;
9704 
input CLR;
9705 
input D;
9706 
input G;
9707 
input GE;
9708 
input PRE;
9709 
endmodule
9710 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9711 
module LDCP (Q, CLR, D, G, PRE);
9712 
parameter INIT = 1'b0;
9713 
output Q;
9714 
input CLR;
9715 
input D;
9716 
input G;
9717 
input PRE;
9718 
endmodule
9719 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9720 
module LDC (Q, CLR, D, G);
9721 
parameter INIT = 1'b0;
9722 
output Q;
9723 
input CLR;
9724 
input D;
9725 
input G;
9726 
endmodule
9727 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9728 
module LDE_1 (Q, D, G, GE);
9729 
parameter INIT = 1'b0;
9730 
output Q;
9731 
input D;
9732 
input G;
9733 
input GE;
9734 
endmodule
9735 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9736 
module LDE (Q, D, G, GE);
9737 
parameter INIT = 1'b0;
9738 
output Q;
9739 
input D;
9740 
input G;
9741 
input GE;
9742 
endmodule
9743 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9744 
module LDG (Q, D, G);
9745 
parameter INIT = 1'b0;
9746 
output Q;
9747 
input D;
9748 
input G;
9749 
endmodule
9750 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9751 
module LDP_1 (Q, D, G, PRE);
9752 
parameter INIT = 1'b1;
9753 
output Q;
9754 
input D;
9755 
input G;
9756 
input PRE;
9757 
endmodule
9758 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9759 
module LDPE_1 (Q, D, G, GE, PRE);
9760 
parameter INIT = 1'b1;
9761 
output Q;
9762 
input D;
9763 
input G;
9764 
input GE;
9765 
input PRE;
9766 
endmodule
9767 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9768 
module LDPE (Q, D, G, GE, PRE);
9769 
parameter INIT = 1'b1;
9770 
output Q;
9771 
input D;
9772 
input G;
9773 
input GE;
9774 
input PRE;
9775 
endmodule
9776 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9777 
module LDP (Q, D, G, PRE);
9778 
parameter INIT = 1'b1;
9779 
output Q;
9780 
input D;
9781 
input G;
9782 
input PRE;
9783 
endmodule
9784 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9785 
module LD (Q, D, G);
9786 
parameter INIT = 1'b0;
9787 
output Q;
9788 
input D;
9789 
input G;
9790 
endmodule
9791 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9792 
module LUT1_D (LO, O, I0);
9793 
parameter INIT = 2'h0;
9794 
output LO;
9795 
output O;
9796 
input I0;
9797 
endmodule
9798 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9799 
module LUT1_L (LO, I0);
9800 
parameter INIT = 2'h0;
9801 
output LO;
9802 
input I0;
9803 
endmodule
9804 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9805 
module LUT1 (O, I0);
9806 
parameter INIT = 2'h0;
9807 
output O;
9808 
input I0;
9809 
endmodule
9810 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9811 
module LUT2_D (LO, O, I0, I1);
9812 
parameter INIT = 4'h0;
9813 
output LO;
9814 
output O;
9815 
input I0;
9816 
input I1;
9817 
endmodule
9818 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9819 
module LUT2_L (LO, I0, I1);
9820 
parameter INIT = 4'h0;
9821 
output LO;
9822 
input I0;
9823 
input I1;
9824 
endmodule
9825 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9826 
module LUT2 (O, I0, I1);
9827 
parameter INIT = 4'h0;
9828 
output O;
9829 
input I0;
9830 
input I1;
9831 
endmodule
9832 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9833 
module LUT3_D (LO, O, I0, I1, I2);
9834 
parameter INIT = 8'h00;
9835 
output LO;
9836 
output O;
9837 
input I0;
9838 
input I1;
9839 
input I2;
9840 
endmodule
9841 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9842 
module LUT3_L (LO, I0, I1, I2);
9843 
parameter INIT = 8'h00;
9844 
output LO;
9845 
input I0;
9846 
input I1;
9847 
input I2;
9848 
endmodule
9849 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9850 
module LUT3 (O, I0, I1, I2);
9851 
parameter INIT = 8'h00;
9852 
output O;
9853 
input I0;
9854 
input I1;
9855 
input I2;
9856 
endmodule
9857 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9858 
module LUT4_D (LO, O, I0, I1, I2, I3);
9859 
parameter INIT = 16'h0000;
9860 
output LO;
9861 
output O;
9862 
input I0;
9863 
input I1;
9864 
input I2;
9865 
input I3;
9866 
endmodule
9867 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9868 
module LUT4_L (LO, I0, I1, I2, I3);
9869 
parameter INIT = 16'h0000;
9870 
output LO;
9871 
input I0;
9872 
input I1;
9873 
input I2;
9874 
input I3;
9875 
endmodule
9876 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9877 
module LUT4 (O, I0, I1, I2, I3);
9878 
parameter INIT = 16'h0000;
9879 
output O;
9880 
input I0;
9881 
input I1;
9882 
input I2;
9883 
input I3;
9884 
endmodule
9885 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9886 
module LUT5_D (LO, O, I0, I1, I2, I3, I4);
9887 
parameter INIT = 32'h00000000;
9888 
output LO;
9889 
output O;
9890 
input I0;
9891 
input I1;
9892 
input I2;
9893 
input I3;
9894 
input I4;
9895 
endmodule
9896 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9897 
module LUT5_L (LO, I0, I1, I2, I3, I4);
9898 
parameter INIT = 32'h00000000;
9899 
output LO;
9900 
input I0;
9901 
input I1;
9902 
input I2;
9903 
input I3;
9904 
input I4;
9905 
endmodule
9906 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9907 
module LUT5 (O, I0, I1, I2, I3, I4);
9908 
parameter INIT = 32'h00000000;
9909 
output O;
9910 
input I0;
9911 
input I1;
9912 
input I2;
9913 
input I3;
9914 
input I4;
9915 
endmodule
9916 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9917 
module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5);
9918 
parameter INIT = 64'h0000000000000000;
9919 
output O5;
9920 
output O6;
9921 
input I0;
9922 
input I1;
9923 
input I2;
9924 
input I3;
9925 
input I4;
9926 
input I5;
9927 
endmodule
9928 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9929 
module LUT6_D (LO, O, I0, I1, I2, I3, I4, I5);
9930 
parameter INIT = 64'h0000000000000000;
9931 
output LO;
9932 
output O;
9933 
input I0;
9934 
input I1;
9935 
input I2;
9936 
input I3;
9937 
input I4;
9938 
input I5;
9939 
endmodule
9940 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9941 
module LUT6_L (LO, I0, I1, I2, I3, I4, I5);
9942 
parameter INIT = 64'h0000000000000000;
9943 
output LO;
9944 
input I0;
9945 
input I1;
9946 
input I2;
9947 
input I3;
9948 
input I4;
9949 
input I5;
9950 
endmodule
9951 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9952 
module LUT6 (O, I0, I1, I2, I3, I4, I5);
9953 
parameter INIT = 64'h0000000000000000;
9954 
output O;
9955 
input I0;
9956 
input I1;
9957 
input I2;
9958 
input I3;
9959 
input I4;
9960 
input I5;
9961 
endmodule
9962 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9963 
module MERGE (I);
9964 
input I;
9965 
endmodule
9966 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9967 
module MIN_OFF (I);
9968 
input I;
9969 
endmodule
9970 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9971 
module MULT18X18SIO (BCOUT, P, A, B, BCIN, CEA, CEB, CEP, CLK, RSTA, RSTB, RSTP);
9972 
parameter integer AREG = 1;
9973 
parameter integer BREG = 1;
9974 
parameter B_INPUT = "DIRECT";
9975 
parameter integer PREG = 1;
9976 
output [17:0] BCOUT;
9977 
output [35:0] P;
9978 
input [17:0] A;
9979 
input [17:0] B;
9980 
input [17:0] BCIN;
9981 
input CEA;
9982 
input CEB;
9983 
input CEP;
9984 
input CLK;
9985 
input RSTA;
9986 
input RSTB;
9987 
input RSTP;
9988 
endmodule
9989 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9990 
module MULT18X18S (P, A, B, C, CE, R);
9991 
output [35:0] P;
9992 
input [17:0] A;
9993 
input [17:0] B;
9994 
input C;
9995 
input CE;
9996 
input R;
9997 
endmodule
9998 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
9999 
module MULT18X18 (P, A, B);
10000 
output [35:0] P;
10001 
input [17:0] A;
10002 
input [17:0] B;
10003 
endmodule
10004 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10005 
module MULT_AND (LO, I0, I1);
10006 
output LO;
10007 
input I0;
10008 
input I1;
10009 
endmodule
10010 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10011 
module MUXCY_D (LO, O, CI, DI, S);
10012 
output LO;
10013 
output O;
10014 
input CI;
10015 
input DI;
10016 
input S;
10017 
endmodule
10018 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10019 
module MUXCY_L (LO, CI, DI, S);
10020 
output LO;
10021 
input CI;
10022 
input DI;
10023 
input S;
10024 
endmodule
10025 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10026 
module MUXCY (O, CI, DI, S);
10027 
output O;
10028 
input CI;
10029 
input DI;
10030 
input S;
10031 
endmodule
10032 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10033 
module MUXF5_D (LO, O, I0, I1, S);
10034 
output LO;
10035 
output O;
10036 
input I0;
10037 
input I1;
10038 
input S;
10039 
endmodule
10040 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10041 
module MUXF5_L (LO, I0, I1, S);
10042 
output LO;
10043 
input I0;
10044 
input I1;
10045 
input S;
10046 
endmodule
10047 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10048 
module MUXF5 (O, I0, I1, S);
10049 
output O;
10050 
input I0;
10051 
input I1;
10052 
input S;
10053 
endmodule
10054 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10055 
module MUXF6_D (LO, O, I0, I1, S);
10056 
output LO;
10057 
output O;
10058 
input I0;
10059 
input I1;
10060 
input S;
10061 
endmodule
10062 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10063 
module MUXF6_L (LO, I0, I1, S);
10064 
output LO;
10065 
input I0;
10066 
input I1;
10067 
input S;
10068 
endmodule
10069 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10070 
module MUXF6 (O, I0, I1, S);
10071 
output O;
10072 
input I0;
10073 
input I1;
10074 
input S;
10075 
endmodule
10076 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10077 
module MUXF7_D (LO, O, I0, I1, S);
10078 
output LO;
10079 
output O;
10080 
input I0;
10081 
input I1;
10082 
input S;
10083 
endmodule
10084 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10085 
module MUXF7_L (LO, I0, I1, S);
10086 
output LO;
10087 
input I0;
10088 
input I1;
10089 
input S;
10090 
endmodule
10091 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10092 
module MUXF7 (O, I0, I1, S);
10093 
output O;
10094 
input I0;
10095 
input I1;
10096 
input S;
10097 
endmodule
10098 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10099 
module MUXF8_D (LO, O, I0, I1, S);
10100 
output LO;
10101 
output O;
10102 
input I0;
10103 
input I1;
10104 
input S;
10105 
endmodule
10106 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10107 
module MUXF8_L (LO, I0, I1, S);
10108 
output LO;
10109 
input I0;
10110 
input I1;
10111 
input S;
10112 
endmodule
10113 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10114 
module MUXF8 (O, I0, I1, S);
10115 
output O;
10116 
input I0;
10117 
input I1;
10118 
input S;
10119 
endmodule
10120 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10121 
module NAND2B1 (O, I0, I1);
10122 
output O;
10123 
input I0;
10124 
input I1;
10125 
endmodule
10126 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10127 
module NAND2B2 (O, I0, I1);
10128 
output O;
10129 
input I0;
10130 
input I1;
10131 
endmodule
10132 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10133 
module NAND2 (O, I0, I1);
10134 
output O;
10135 
input I0;
10136 
input I1;
10137 
endmodule
10138 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10139 
module NAND3B1 (O, I0, I1, I2);
10140 
output O;
10141 
input I0;
10142 
input I1;
10143 
input I2;
10144 
endmodule
10145 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10146 
module NAND3B2 (O, I0, I1, I2);
10147 
output O;
10148 
input I0;
10149 
input I1;
10150 
input I2;
10151 
endmodule
10152 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10153 
module NAND3B3 (O, I0, I1, I2);
10154 
output O;
10155 
input I0;
10156 
input I1;
10157 
input I2;
10158 
endmodule
10159 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10160 
module NAND3 (O, I0, I1, I2);
10161 
output O;
10162 
input I0;
10163 
input I1;
10164 
input I2;
10165 
endmodule
10166 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10167 
module NAND4B1 (O, I0, I1, I2, I3);
10168 
output O;
10169 
input I0;
10170 
input I1;
10171 
input I2;
10172 
input I3;
10173 
endmodule
10174 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10175 
module NAND4B2 (O, I0, I1, I2, I3);
10176 
output O;
10177 
input I0;
10178 
input I1;
10179 
input I2;
10180 
input I3;
10181 
endmodule
10182 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10183 
module NAND4B3 (O, I0, I1, I2, I3);
10184 
output O;
10185 
input I0;
10186 
input I1;
10187 
input I2;
10188 
input I3;
10189 
endmodule
10190 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10191 
module NAND4B4 (O, I0, I1, I2, I3);
10192 
output O;
10193 
input I0;
10194 
input I1;
10195 
input I2;
10196 
input I3;
10197 
endmodule
10198 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10199 
module NAND4 (O, I0, I1, I2, I3);
10200 
output O;
10201 
input I0;
10202 
input I1;
10203 
input I2;
10204 
input I3;
10205 
endmodule
10206 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10207 
module NAND5B1 (O, I0, I1, I2, I3, I4);
10208 
output O;
10209 
input I0;
10210 
input I1;
10211 
input I2;
10212 
input I3;
10213 
input I4;
10214 
endmodule
10215 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10216 
module NAND5B2 (O, I0, I1, I2, I3, I4);
10217 
output O;
10218 
input I0;
10219 
input I1;
10220 
input I2;
10221 
input I3;
10222 
input I4;
10223 
endmodule
10224 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10225 
module NAND5B3 (O, I0, I1, I2, I3, I4);
10226 
output O;
10227 
input I0;
10228 
input I1;
10229 
input I2;
10230 
input I3;
10231 
input I4;
10232 
endmodule
10233 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10234 
module NAND5B4 (O, I0, I1, I2, I3, I4);
10235 
output O;
10236 
input I0;
10237 
input I1;
10238 
input I2;
10239 
input I3;
10240 
input I4;
10241 
endmodule
10242 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10243 
module NAND5B5 (O, I0, I1, I2, I3, I4);
10244 
output O;
10245 
input I0;
10246 
input I1;
10247 
input I2;
10248 
input I3;
10249 
input I4;
10250 
endmodule
10251 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10252 
module NAND5 (O, I0, I1, I2, I3, I4);
10253 
output O;
10254 
input I0;
10255 
input I1;
10256 
input I2;
10257 
input I3;
10258 
input I4;
10259 
endmodule
10260 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10261 
module NOR2B1 (O, I0, I1);
10262 
output O;
10263 
input I0;
10264 
input I1;
10265 
endmodule
10266 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10267 
module NOR2B2 (O, I0, I1);
10268 
output O;
10269 
input I0;
10270 
input I1;
10271 
endmodule
10272 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10273 
module NOR2 (O, I0, I1);
10274 
output O;
10275 
input I0;
10276 
input I1;
10277 
endmodule
10278 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10279 
module NOR3B1 (O, I0, I1, I2);
10280 
output O;
10281 
input I0;
10282 
input I1;
10283 
input I2;
10284 
endmodule
10285 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10286 
module NOR3B2 (O, I0, I1, I2);
10287 
output O;
10288 
input I0;
10289 
input I1;
10290 
input I2;
10291 
endmodule
10292 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10293 
module NOR3B3 (O, I0, I1, I2);
10294 
output O;
10295 
input I0;
10296 
input I1;
10297 
input I2;
10298 
endmodule
10299 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10300 
module NOR3 (O, I0, I1, I2);
10301 
output O;
10302 
input I0;
10303 
input I1;
10304 
input I2;
10305 
endmodule
10306 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10307 
module NOR4B1 (O, I0, I1, I2, I3);
10308 
output O;
10309 
input I0;
10310 
input I1;
10311 
input I2;
10312 
input I3;
10313 
endmodule
10314 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10315 
module NOR4B2 (O, I0, I1, I2, I3);
10316 
output O;
10317 
input I0;
10318 
input I1;
10319 
input I2;
10320 
input I3;
10321 
endmodule
10322 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10323 
module NOR4B3 (O, I0, I1, I2, I3);
10324 
output O;
10325 
input I0;
10326 
input I1;
10327 
input I2;
10328 
input I3;
10329 
endmodule
10330 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10331 
module NOR4B4 (O, I0, I1, I2, I3);
10332 
output O;
10333 
input I0;
10334 
input I1;
10335 
input I2;
10336 
input I3;
10337 
endmodule
10338 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10339 
module NOR4 (O, I0, I1, I2, I3);
10340 
output O;
10341 
input I0;
10342 
input I1;
10343 
input I2;
10344 
input I3;
10345 
endmodule
10346 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10347 
module NOR5B1 (O, I0, I1, I2, I3, I4);
10348 
output O;
10349 
input I0;
10350 
input I1;
10351 
input I2;
10352 
input I3;
10353 
input I4;
10354 
endmodule
10355 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10356 
module NOR5B2 (O, I0, I1, I2, I3, I4);
10357 
output O;
10358 
input I0;
10359 
input I1;
10360 
input I2;
10361 
input I3;
10362 
input I4;
10363 
endmodule
10364 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10365 
module NOR5B3 (O, I0, I1, I2, I3, I4);
10366 
output O;
10367 
input I0;
10368 
input I1;
10369 
input I2;
10370 
input I3;
10371 
input I4;
10372 
endmodule
10373 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10374 
module NOR5B4 (O, I0, I1, I2, I3, I4);
10375 
output O;
10376 
input I0;
10377 
input I1;
10378 
input I2;
10379 
input I3;
10380 
input I4;
10381 
endmodule
10382 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10383 
module NOR5B5 (O, I0, I1, I2, I3, I4);
10384 
output O;
10385 
input I0;
10386 
input I1;
10387 
input I2;
10388 
input I3;
10389 
input I4;
10390 
endmodule
10391 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10392 
module NOR5 (O, I0, I1, I2, I3, I4);
10393 
output O;
10394 
input I0;
10395 
input I1;
10396 
input I2;
10397 
input I3;
10398 
input I4;
10399 
endmodule
10400 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10401 
module OBUF_AGP (O, I);
10402 
output O;
10403 
input I;
10404 
endmodule
10405 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10406 
module OBUF_CTT (O, I);
10407 
output O;
10408 
input I;
10409 
endmodule
10410 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10411 
module OBUFDS_BLVDS_25 (O, OB, I);
10412 
output O;
10413 
output OB;
10414 
input I;
10415 
endmodule
10416 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10417 
module OBUFDS_LDT_25 (O, OB, I);
10418 
output O;
10419 
output OB;
10420 
input I;
10421 
endmodule
10422 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10423 
module OBUFDS_LVDS_25 (O, OB, I);
10424 
output O;
10425 
output OB;
10426 
input I;
10427 
endmodule
10428 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10429 
module OBUFDS_LVDS_33 (O, OB, I);
10430 
output O;
10431 
output OB;
10432 
input I;
10433 
endmodule
10434 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10435 
module OBUFDS_LVDSEXT_25 (O, OB, I);
10436 
output O;
10437 
output OB;
10438 
input I;
10439 
endmodule
10440 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10441 
module OBUFDS_LVDSEXT_33 (O, OB, I);
10442 
output O;
10443 
output OB;
10444 
input I;
10445 
endmodule
10446 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10447 
module OBUFDS_LVPECL_25 (O, OB, I);
10448 
output O;
10449 
output OB;
10450 
input I;
10451 
endmodule
10452 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10453 
module OBUFDS_LVPECL_33 (O, OB, I);
10454 
output O;
10455 
output OB;
10456 
input I;
10457 
endmodule
10458 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10459 
module OBUFDS_ULVDS_25 (O, OB, I);
10460 
output O;
10461 
output OB;
10462 
input I;
10463 
endmodule
10464 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10465 
module OBUFDS (O, OB, I);
10466 
parameter CAPACITANCE = "DONT_CARE";
10467 
parameter IOSTANDARD = "DEFAULT";
10468 
output O;
10469 
output OB;
10470 
input I;
10471 
endmodule
10472 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10473 
module OBUFE (O, E, I);
10474 
output O;
10475 
input E;
10476 
input I;
10477 
endmodule
10478 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10479 
module OBUF_F_12 (O, I);
10480 
output O;
10481 
input I;
10482 
endmodule
10483 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10484 
module OBUF_F_16 (O, I);
10485 
output O;
10486 
input I;
10487 
endmodule
10488 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10489 
module OBUF_F_24 (O, I);
10490 
output O;
10491 
input I;
10492 
endmodule
10493 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10494 
module OBUF_F_2 (O, I);
10495 
output O;
10496 
input I;
10497 
endmodule
10498 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10499 
module OBUF_F_4 (O, I);
10500 
output O;
10501 
input I;
10502 
endmodule
10503 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10504 
module OBUF_F_6 (O, I);
10505 
output O;
10506 
input I;
10507 
endmodule
10508 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10509 
module OBUF_F_8 (O, I);
10510 
output O;
10511 
input I;
10512 
endmodule
10513 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10514 
module OBUF_GTL_DCI (O, I);
10515 
output O;
10516 
input I;
10517 
endmodule
10518 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10519 
module OBUF_GTLP_DCI (O, I);
10520 
output O;
10521 
input I;
10522 
endmodule
10523 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10524 
module OBUF_GTLP (O, I);
10525 
output O;
10526 
input I;
10527 
endmodule
10528 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10529 
module OBUF_GTL (O, I);
10530 
output O;
10531 
input I;
10532 
endmodule
10533 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10534 
module OBUF_HSTL_I_18 (O, I);
10535 
output O;
10536 
input I;
10537 
endmodule
10538 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10539 
module OBUF_HSTL_I_DCI_18 (O, I);
10540 
output O;
10541 
input I;
10542 
endmodule
10543 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10544 
module OBUF_HSTL_I_DCI (O, I);
10545 
output O;
10546 
input I;
10547 
endmodule
10548 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10549 
module OBUF_HSTL_II_18 (O, I);
10550 
output O;
10551 
input I;
10552 
endmodule
10553 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10554 
module OBUF_HSTL_II_DCI_18 (O, I);
10555 
output O;
10556 
input I;
10557 
endmodule
10558 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10559 
module OBUF_HSTL_II_DCI (O, I);
10560 
output O;
10561 
input I;
10562 
endmodule
10563 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10564 
module OBUF_HSTL_III_18 (O, I);
10565 
output O;
10566 
input I;
10567 
endmodule
10568 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10569 
module OBUF_HSTL_III_DCI_18 (O, I);
10570 
output O;
10571 
input I;
10572 
endmodule
10573 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10574 
module OBUF_HSTL_III_DCI (O, I);
10575 
output O;
10576 
input I;
10577 
endmodule
10578 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10579 
module OBUF_HSTL_III (O, I);
10580 
output O;
10581 
input I;
10582 
endmodule
10583 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10584 
module OBUF_HSTL_II (O, I);
10585 
output O;
10586 
input I;
10587 
endmodule
10588 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10589 
module OBUF_HSTL_I (O, I);
10590 
output O;
10591 
input I;
10592 
endmodule
10593 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10594 
module OBUF_HSTL_IV_18 (O, I);
10595 
output O;
10596 
input I;
10597 
endmodule
10598 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10599 
module OBUF_HSTL_IV_DCI_18 (O, I);
10600 
output O;
10601 
input I;
10602 
endmodule
10603 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10604 
module OBUF_HSTL_IV_DCI (O, I);
10605 
output O;
10606 
input I;
10607 
endmodule
10608 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10609 
module OBUF_HSTL_IV (O, I);
10610 
output O;
10611 
input I;
10612 
endmodule
10613 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10614 
module OBUF_LVCMOS12_F_2 (O, I);
10615 
output O;
10616 
input I;
10617 
endmodule
10618 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10619 
module OBUF_LVCMOS12_F_4 (O, I);
10620 
output O;
10621 
input I;
10622 
endmodule
10623 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10624 
module OBUF_LVCMOS12_F_6 (O, I);
10625 
output O;
10626 
input I;
10627 
endmodule
10628 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10629 
module OBUF_LVCMOS12_F_8 (O, I);
10630 
output O;
10631 
input I;
10632 
endmodule
10633 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10634 
module OBUF_LVCMOS12_S_2 (O, I);
10635 
output O;
10636 
input I;
10637 
endmodule
10638 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10639 
module OBUF_LVCMOS12_S_4 (O, I);
10640 
output O;
10641 
input I;
10642 
endmodule
10643 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10644 
module OBUF_LVCMOS12_S_6 (O, I);
10645 
output O;
10646 
input I;
10647 
endmodule
10648 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10649 
module OBUF_LVCMOS12_S_8 (O, I);
10650 
output O;
10651 
input I;
10652 
endmodule
10653 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10654 
module OBUF_LVCMOS12 (O, I);
10655 
output O;
10656 
input I;
10657 
endmodule
10658 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10659 
module OBUF_LVCMOS15_F_12 (O, I);
10660 
output O;
10661 
input I;
10662 
endmodule
10663 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10664 
module OBUF_LVCMOS15_F_16 (O, I);
10665 
output O;
10666 
input I;
10667 
endmodule
10668 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10669 
module OBUF_LVCMOS15_F_2 (O, I);
10670 
output O;
10671 
input I;
10672 
endmodule
10673 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10674 
module OBUF_LVCMOS15_F_4 (O, I);
10675 
output O;
10676 
input I;
10677 
endmodule
10678 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10679 
module OBUF_LVCMOS15_F_6 (O, I);
10680 
output O;
10681 
input I;
10682 
endmodule
10683 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10684 
module OBUF_LVCMOS15_F_8 (O, I);
10685 
output O;
10686 
input I;
10687 
endmodule
10688 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10689 
module OBUF_LVCMOS15_S_12 (O, I);
10690 
output O;
10691 
input I;
10692 
endmodule
10693 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10694 
module OBUF_LVCMOS15_S_16 (O, I);
10695 
output O;
10696 
input I;
10697 
endmodule
10698 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10699 
module OBUF_LVCMOS15_S_2 (O, I);
10700 
output O;
10701 
input I;
10702 
endmodule
10703 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10704 
module OBUF_LVCMOS15_S_4 (O, I);
10705 
output O;
10706 
input I;
10707 
endmodule
10708 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10709 
module OBUF_LVCMOS15_S_6 (O, I);
10710 
output O;
10711 
input I;
10712 
endmodule
10713 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10714 
module OBUF_LVCMOS15_S_8 (O, I);
10715 
output O;
10716 
input I;
10717 
endmodule
10718 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10719 
module OBUF_LVCMOS15 (O, I);
10720 
output O;
10721 
input I;
10722 
endmodule
10723 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10724 
module OBUF_LVCMOS18_F_12 (O, I);
10725 
output O;
10726 
input I;
10727 
endmodule
10728 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10729 
module OBUF_LVCMOS18_F_16 (O, I);
10730 
output O;
10731 
input I;
10732 
endmodule
10733 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10734 
module OBUF_LVCMOS18_F_2 (O, I);
10735 
output O;
10736 
input I;
10737 
endmodule
10738 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10739 
module OBUF_LVCMOS18_F_4 (O, I);
10740 
output O;
10741 
input I;
10742 
endmodule
10743 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10744 
module OBUF_LVCMOS18_F_6 (O, I);
10745 
output O;
10746 
input I;
10747 
endmodule
10748 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10749 
module OBUF_LVCMOS18_F_8 (O, I);
10750 
output O;
10751 
input I;
10752 
endmodule
10753 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10754 
module OBUF_LVCMOS18_S_12 (O, I);
10755 
output O;
10756 
input I;
10757 
endmodule
10758 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10759 
module OBUF_LVCMOS18_S_16 (O, I);
10760 
output O;
10761 
input I;
10762 
endmodule
10763 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10764 
module OBUF_LVCMOS18_S_2 (O, I);
10765 
output O;
10766 
input I;
10767 
endmodule
10768 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10769 
module OBUF_LVCMOS18_S_4 (O, I);
10770 
output O;
10771 
input I;
10772 
endmodule
10773 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10774 
module OBUF_LVCMOS18_S_6 (O, I);
10775 
output O;
10776 
input I;
10777 
endmodule
10778 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10779 
module OBUF_LVCMOS18_S_8 (O, I);
10780 
output O;
10781 
input I;
10782 
endmodule
10783 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10784 
module OBUF_LVCMOS18 (O, I);
10785 
output O;
10786 
input I;
10787 
endmodule
10788 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10789 
module OBUF_LVCMOS25_F_12 (O, I);
10790 
output O;
10791 
input I;
10792 
endmodule
10793 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10794 
module OBUF_LVCMOS25_F_16 (O, I);
10795 
output O;
10796 
input I;
10797 
endmodule
10798 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10799 
module OBUF_LVCMOS25_F_24 (O, I);
10800 
output O;
10801 
input I;
10802 
endmodule
10803 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10804 
module OBUF_LVCMOS25_F_2 (O, I);
10805 
output O;
10806 
input I;
10807 
endmodule
10808 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10809 
module OBUF_LVCMOS25_F_4 (O, I);
10810 
output O;
10811 
input I;
10812 
endmodule
10813 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10814 
module OBUF_LVCMOS25_F_6 (O, I);
10815 
output O;
10816 
input I;
10817 
endmodule
10818 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10819 
module OBUF_LVCMOS25_F_8 (O, I);
10820 
output O;
10821 
input I;
10822 
endmodule
10823 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10824 
module OBUF_LVCMOS25_S_12 (O, I);
10825 
output O;
10826 
input I;
10827 
endmodule
10828 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10829 
module OBUF_LVCMOS25_S_16 (O, I);
10830 
output O;
10831 
input I;
10832 
endmodule
10833 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10834 
module OBUF_LVCMOS25_S_24 (O, I);
10835 
output O;
10836 
input I;
10837 
endmodule
10838 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10839 
module OBUF_LVCMOS25_S_2 (O, I);
10840 
output O;
10841 
input I;
10842 
endmodule
10843 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10844 
module OBUF_LVCMOS25_S_4 (O, I);
10845 
output O;
10846 
input I;
10847 
endmodule
10848 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10849 
module OBUF_LVCMOS25_S_6 (O, I);
10850 
output O;
10851 
input I;
10852 
endmodule
10853 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10854 
module OBUF_LVCMOS25_S_8 (O, I);
10855 
output O;
10856 
input I;
10857 
endmodule
10858 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10859 
module OBUF_LVCMOS25 (O, I);
10860 
output O;
10861 
input I;
10862 
endmodule
10863 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10864 
module OBUF_LVCMOS2 (O, I);
10865 
output O;
10866 
input I;
10867 
endmodule
10868 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10869 
module OBUF_LVCMOS33_F_12 (O, I);
10870 
output O;
10871 
input I;
10872 
endmodule
10873 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10874 
module OBUF_LVCMOS33_F_16 (O, I);
10875 
output O;
10876 
input I;
10877 
endmodule
10878 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10879 
module OBUF_LVCMOS33_F_24 (O, I);
10880 
output O;
10881 
input I;
10882 
endmodule
10883 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10884 
module OBUF_LVCMOS33_F_2 (O, I);
10885 
output O;
10886 
input I;
10887 
endmodule
10888 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10889 
module OBUF_LVCMOS33_F_4 (O, I);
10890 
output O;
10891 
input I;
10892 
endmodule
10893 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10894 
module OBUF_LVCMOS33_F_6 (O, I);
10895 
output O;
10896 
input I;
10897 
endmodule
10898 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10899 
module OBUF_LVCMOS33_F_8 (O, I);
10900 
output O;
10901 
input I;
10902 
endmodule
10903 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10904 
module OBUF_LVCMOS33_S_12 (O, I);
10905 
output O;
10906 
input I;
10907 
endmodule
10908 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10909 
module OBUF_LVCMOS33_S_16 (O, I);
10910 
output O;
10911 
input I;
10912 
endmodule
10913 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10914 
module OBUF_LVCMOS33_S_24 (O, I);
10915 
output O;
10916 
input I;
10917 
endmodule
10918 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10919 
module OBUF_LVCMOS33_S_2 (O, I);
10920 
output O;
10921 
input I;
10922 
endmodule
10923 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10924 
module OBUF_LVCMOS33_S_4 (O, I);
10925 
output O;
10926 
input I;
10927 
endmodule
10928 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10929 
module OBUF_LVCMOS33_S_6 (O, I);
10930 
output O;
10931 
input I;
10932 
endmodule
10933 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10934 
module OBUF_LVCMOS33_S_8 (O, I);
10935 
output O;
10936 
input I;
10937 
endmodule
10938 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10939 
module OBUF_LVCMOS33 (O, I);
10940 
output O;
10941 
input I;
10942 
endmodule
10943 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10944 
module OBUF_LVDCI_15 (O, I);
10945 
output O;
10946 
input I;
10947 
endmodule
10948 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10949 
module OBUF_LVDCI_18 (O, I);
10950 
output O;
10951 
input I;
10952 
endmodule
10953 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10954 
module OBUF_LVDCI_25 (O, I);
10955 
output O;
10956 
input I;
10957 
endmodule
10958 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10959 
module OBUF_LVDCI_33 (O, I);
10960 
output O;
10961 
input I;
10962 
endmodule
10963 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10964 
module OBUF_LVDCI_DV2_15 (O, I);
10965 
output O;
10966 
input I;
10967 
endmodule
10968 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10969 
module OBUF_LVDCI_DV2_18 (O, I);
10970 
output O;
10971 
input I;
10972 
endmodule
10973 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10974 
module OBUF_LVDCI_DV2_25 (O, I);
10975 
output O;
10976 
input I;
10977 
endmodule
10978 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10979 
module OBUF_LVDCI_DV2_33 (O, I);
10980 
output O;
10981 
input I;
10982 
endmodule
10983 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10984 
module OBUF_LVDS (O, I);
10985 
output O;
10986 
input I;
10987 
endmodule
10988 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10989 
module OBUF_LVPECL (O, I);
10990 
output O;
10991 
input I;
10992 
endmodule
10993 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10994 
module OBUF_LVTTL_F_12 (O, I);
10995 
output O;
10996 
input I;
10997 
endmodule
10998 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
10999 
module OBUF_LVTTL_F_16 (O, I);
11000 
output O;
11001 
input I;
11002 
endmodule
11003 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11004 
module OBUF_LVTTL_F_24 (O, I);
11005 
output O;
11006 
input I;
11007 
endmodule
11008 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11009 
module OBUF_LVTTL_F_2 (O, I);
11010 
output O;
11011 
input I;
11012 
endmodule
11013 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11014 
module OBUF_LVTTL_F_4 (O, I);
11015 
output O;
11016 
input I;
11017 
endmodule
11018 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11019 
module OBUF_LVTTL_F_6 (O, I);
11020 
output O;
11021 
input I;
11022 
endmodule
11023 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11024 
module OBUF_LVTTL_F_8 (O, I);
11025 
output O;
11026 
input I;
11027 
endmodule
11028 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11029 
module OBUF_LVTTL_S_12 (O, I);
11030 
output O;
11031 
input I;
11032 
endmodule
11033 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11034 
module OBUF_LVTTL_S_16 (O, I);
11035 
output O;
11036 
input I;
11037 
endmodule
11038 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11039 
module OBUF_LVTTL_S_24 (O, I);
11040 
output O;
11041 
input I;
11042 
endmodule
11043 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11044 
module OBUF_LVTTL_S_2 (O, I);
11045 
output O;
11046 
input I;
11047 
endmodule
11048 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11049 
module OBUF_LVTTL_S_4 (O, I);
11050 
output O;
11051 
input I;
11052 
endmodule
11053 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11054 
module OBUF_LVTTL_S_6 (O, I);
11055 
output O;
11056 
input I;
11057 
endmodule
11058 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11059 
module OBUF_LVTTL_S_8 (O, I);
11060 
output O;
11061 
input I;
11062 
endmodule
11063 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11064 
module OBUF_LVTTL (O, I);
11065 
output O;
11066 
input I;
11067 
endmodule
11068 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11069 
module OBUF_PCI33_3 (O, I);
11070 
output O;
11071 
input I;
11072 
endmodule
11073 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11074 
module OBUF_PCI33_5 (O, I);
11075 
output O;
11076 
input I;
11077 
endmodule
11078 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11079 
module OBUF_PCI66_3 (O, I);
11080 
output O;
11081 
input I;
11082 
endmodule
11083 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11084 
module OBUF_PCIX66_3 (O, I);
11085 
output O;
11086 
input I;
11087 
endmodule
11088 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11089 
module OBUF_PCIX (O, I);
11090 
output O;
11091 
input I;
11092 
endmodule
11093 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11094 
module OBUF_S_12 (O, I);
11095 
output O;
11096 
input I;
11097 
endmodule
11098 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11099 
module OBUF_S_16 (O, I);
11100 
output O;
11101 
input I;
11102 
endmodule
11103 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11104 
module OBUF_S_24 (O, I);
11105 
output O;
11106 
input I;
11107 
endmodule
11108 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11109 
module OBUF_S_2 (O, I);
11110 
output O;
11111 
input I;
11112 
endmodule
11113 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11114 
module OBUF_S_4 (O, I);
11115 
output O;
11116 
input I;
11117 
endmodule
11118 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11119 
module OBUF_S_6 (O, I);
11120 
output O;
11121 
input I;
11122 
endmodule
11123 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11124 
module OBUF_S_8 (O, I);
11125 
output O;
11126 
input I;
11127 
endmodule
11128 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11129 
module OBUF_SSTL18_I_DCI (O, I);
11130 
output O;
11131 
input I;
11132 
endmodule
11133 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11134 
module OBUF_SSTL18_II_DCI (O, I);
11135 
output O;
11136 
input I;
11137 
endmodule
11138 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11139 
module OBUF_SSTL18_II (O, I);
11140 
output O;
11141 
input I;
11142 
endmodule
11143 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11144 
module OBUF_SSTL18_I (O, I);
11145 
output O;
11146 
input I;
11147 
endmodule
11148 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11149 
module OBUF_SSTL2_I_DCI (O, I);
11150 
output O;
11151 
input I;
11152 
endmodule
11153 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11154 
module OBUF_SSTL2_II_DCI (O, I);
11155 
output O;
11156 
input I;
11157 
endmodule
11158 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11159 
module OBUF_SSTL2_II (O, I);
11160 
output O;
11161 
input I;
11162 
endmodule
11163 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11164 
module OBUF_SSTL2_I (O, I);
11165 
output O;
11166 
input I;
11167 
endmodule
11168 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11169 
module OBUF_SSTL3_I_DCI (O, I);
11170 
output O;
11171 
input I;
11172 
endmodule
11173 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11174 
module OBUF_SSTL3_II_DCI (O, I);
11175 
output O;
11176 
input I;
11177 
endmodule
11178 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11179 
module OBUF_SSTL3_II (O, I);
11180 
output O;
11181 
input I;
11182 
endmodule
11183 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11184 
module OBUF_SSTL3_I (O, I);
11185 
output O;
11186 
input I;
11187 
endmodule
11188 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11189 
module OBUFT_AGP (O, I, T);
11190 
output O;
11191 
input I;
11192 
input T;
11193 
endmodule
11194 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11195 
module OBUFT_CTT (O, I, T);
11196 
output O;
11197 
input I;
11198 
input T;
11199 
endmodule
11200 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11201 
module OBUFTDS_BLVDS_25 (O, OB, I, T);
11202 
output O;
11203 
output OB;
11204 
input I;
11205 
input T;
11206 
endmodule
11207 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11208 
module OBUFTDS_LDT_25 (O, OB, I, T);
11209 
output O;
11210 
output OB;
11211 
input I;
11212 
input T;
11213 
endmodule
11214 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11215 
module OBUFTDS_LVDS_25 (O, OB, I, T);
11216 
output O;
11217 
output OB;
11218 
input I;
11219 
input T;
11220 
endmodule
11221 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11222 
module OBUFTDS_LVDS_33 (O, OB, I, T);
11223 
output O;
11224 
output OB;
11225 
input I;
11226 
input T;
11227 
endmodule
11228 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11229 
module OBUFTDS_LVDSEXT_25 (O, OB, I, T);
11230 
output O;
11231 
output OB;
11232 
input I;
11233 
input T;
11234 
endmodule
11235 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11236 
module OBUFTDS_LVDSEXT_33 (O, OB, I, T);
11237 
output O;
11238 
output OB;
11239 
input I;
11240 
input T;
11241 
endmodule
11242 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11243 
module OBUFTDS_LVPECL_25 (O, OB, I, T);
11244 
output O;
11245 
output OB;
11246 
input I;
11247 
input T;
11248 
endmodule
11249 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11250 
module OBUFTDS_LVPECL_33 (O, OB, I, T);
11251 
output O;
11252 
output OB;
11253 
input I;
11254 
input T;
11255 
endmodule
11256 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11257 
module OBUFTDS_ULVDS_25 (O, OB, I, T);
11258 
output O;
11259 
output OB;
11260 
input I;
11261 
input T;
11262 
endmodule
11263 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11264 
module OBUFTDS (O, OB, I, T);
11265 
parameter CAPACITANCE = "DONT_CARE";
11266 
parameter IOSTANDARD = "DEFAULT";
11267 
output O;
11268 
output OB;
11269 
input I;
11270 
input T;
11271 
endmodule
11272 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11273 
module OBUFT_F_12 (O, I, T);
11274 
output O;
11275 
input I;
11276 
input T;
11277 
endmodule
11278 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11279 
module OBUFT_F_16 (O, I, T);
11280 
output O;
11281 
input I;
11282 
input T;
11283 
endmodule
11284 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11285 
module OBUFT_F_24 (O, I, T);
11286 
output O;
11287 
input I;
11288 
input T;
11289 
endmodule
11290 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11291 
module OBUFT_F_2 (O, I, T);
11292 
output O;
11293 
input I;
11294 
input T;
11295 
endmodule
11296 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11297 
module OBUFT_F_4 (O, I, T);
11298 
output O;
11299 
input I;
11300 
input T;
11301 
endmodule
11302 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11303 
module OBUFT_F_6 (O, I, T);
11304 
output O;
11305 
input I;
11306 
input T;
11307 
endmodule
11308 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11309 
module OBUFT_F_8 (O, I, T);
11310 
output O;
11311 
input I;
11312 
input T;
11313 
endmodule
11314 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11315 
module OBUFT_GTL_DCI (O, I, T);
11316 
output O;
11317 
input I;
11318 
input T;
11319 
endmodule
11320 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11321 
module OBUFT_GTLP_DCI (O, I, T);
11322 
output O;
11323 
input I;
11324 
input T;
11325 
endmodule
11326 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11327 
module OBUFT_GTLP (O, I, T);
11328 
output O;
11329 
input I;
11330 
input T;
11331 
endmodule
11332 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11333 
module OBUFT_GTL (O, I, T);
11334 
output O;
11335 
input I;
11336 
input T;
11337 
endmodule
11338 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11339 
module OBUFT_HSTL_I_18 (O, I, T);
11340 
output O;
11341 
input I;
11342 
input T;
11343 
endmodule
11344 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11345 
module OBUFT_HSTL_I_DCI_18 (O, I, T);
11346 
output O;
11347 
input I;
11348 
input T;
11349 
endmodule
11350 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11351 
module OBUFT_HSTL_I_DCI (O, I, T);
11352 
output O;
11353 
input I;
11354 
input T;
11355 
endmodule
11356 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11357 
module OBUFT_HSTL_II_18 (O, I, T);
11358 
output O;
11359 
input I;
11360 
input T;
11361 
endmodule
11362 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11363 
module OBUFT_HSTL_II_DCI_18 (O, I, T);
11364 
output O;
11365 
input I;
11366 
input T;
11367 
endmodule
11368 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11369 
module OBUFT_HSTL_II_DCI (O, I, T);
11370 
output O;
11371 
input I;
11372 
input T;
11373 
endmodule
11374 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11375 
module OBUFT_HSTL_III_18 (O, I, T);
11376 
output O;
11377 
input I;
11378 
input T;
11379 
endmodule
11380 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11381 
module OBUFT_HSTL_III_DCI_18 (O, I, T);
11382 
output O;
11383 
input I;
11384 
input T;
11385 
endmodule
11386 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11387 
module OBUFT_HSTL_III_DCI (O, I, T);
11388 
output O;
11389 
input I;
11390 
input T;
11391 
endmodule
11392 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11393 
module OBUFT_HSTL_III (O, I, T);
11394 
output O;
11395 
input I;
11396 
input T;
11397 
endmodule
11398 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11399 
module OBUFT_HSTL_II (O, I, T);
11400 
output O;
11401 
input I;
11402 
input T;
11403 
endmodule
11404 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11405 
module OBUFT_HSTL_I (O, I, T);
11406 
output O;
11407 
input I;
11408 
input T;
11409 
endmodule
11410 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11411 
module OBUFT_HSTL_IV_18 (O, I, T);
11412 
output O;
11413 
input I;
11414 
input T;
11415 
endmodule
11416 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11417 
module OBUFT_HSTL_IV_DCI_18 (O, I, T);
11418 
output O;
11419 
input I;
11420 
input T;
11421 
endmodule
11422 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11423 
module OBUFT_HSTL_IV_DCI (O, I, T);
11424 
output O;
11425 
input I;
11426 
input T;
11427 
endmodule
11428 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11429 
module OBUFT_HSTL_IV (O, I, T);
11430 
output O;
11431 
input I;
11432 
input T;
11433 
endmodule
11434 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11435 
module OBUFT_LVCMOS12_F_2 (O, I, T);
11436 
output O;
11437 
input I;
11438 
input T;
11439 
endmodule
11440 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11441 
module OBUFT_LVCMOS12_F_4 (O, I, T);
11442 
output O;
11443 
input I;
11444 
input T;
11445 
endmodule
11446 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11447 
module OBUFT_LVCMOS12_F_6 (O, I, T);
11448 
output O;
11449 
input I;
11450 
input T;
11451 
endmodule
11452 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11453 
module OBUFT_LVCMOS12_F_8 (O, I, T);
11454 
output O;
11455 
input I;
11456 
input T;
11457 
endmodule
11458 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11459 
module OBUFT_LVCMOS12_S_2 (O, I, T);
11460 
output O;
11461 
input I;
11462 
input T;
11463 
endmodule
11464 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11465 
module OBUFT_LVCMOS12_S_4 (O, I, T);
11466 
output O;
11467 
input I;
11468 
input T;
11469 
endmodule
11470 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11471 
module OBUFT_LVCMOS12_S_6 (O, I, T);
11472 
output O;
11473 
input I;
11474 
input T;
11475 
endmodule
11476 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11477 
module OBUFT_LVCMOS12_S_8 (O, I, T);
11478 
output O;
11479 
input I;
11480 
input T;
11481 
endmodule
11482 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11483 
module OBUFT_LVCMOS12 (O, I, T);
11484 
output O;
11485 
input I;
11486 
input T;
11487 
endmodule
11488 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11489 
module OBUFT_LVCMOS15_F_12 (O, I, T);
11490 
output O;
11491 
input I;
11492 
input T;
11493 
endmodule
11494 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11495 
module OBUFT_LVCMOS15_F_16 (O, I, T);
11496 
output O;
11497 
input I;
11498 
input T;
11499 
endmodule
11500 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11501 
module OBUFT_LVCMOS15_F_2 (O, I, T);
11502 
output O;
11503 
input I;
11504 
input T;
11505 
endmodule
11506 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11507 
module OBUFT_LVCMOS15_F_4 (O, I, T);
11508 
output O;
11509 
input I;
11510 
input T;
11511 
endmodule
11512 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11513 
module OBUFT_LVCMOS15_F_6 (O, I, T);
11514 
output O;
11515 
input I;
11516 
input T;
11517 
endmodule
11518 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11519 
module OBUFT_LVCMOS15_F_8 (O, I, T);
11520 
output O;
11521 
input I;
11522 
input T;
11523 
endmodule
11524 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11525 
module OBUFT_LVCMOS15_S_12 (O, I, T);
11526 
output O;
11527 
input I;
11528 
input T;
11529 
endmodule
11530 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11531 
module OBUFT_LVCMOS15_S_16 (O, I, T);
11532 
output O;
11533 
input I;
11534 
input T;
11535 
endmodule
11536 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11537 
module OBUFT_LVCMOS15_S_2 (O, I, T);
11538 
output O;
11539 
input I;
11540 
input T;
11541 
endmodule
11542 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11543 
module OBUFT_LVCMOS15_S_4 (O, I, T);
11544 
output O;
11545 
input I;
11546 
input T;
11547 
endmodule
11548 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11549 
module OBUFT_LVCMOS15_S_6 (O, I, T);
11550 
output O;
11551 
input I;
11552 
input T;
11553 
endmodule
11554 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11555 
module OBUFT_LVCMOS15_S_8 (O, I, T);
11556 
output O;
11557 
input I;
11558 
input T;
11559 
endmodule
11560 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11561 
module OBUFT_LVCMOS15 (O, I, T);
11562 
output O;
11563 
input I;
11564 
input T;
11565 
endmodule
11566 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11567 
module OBUFT_LVCMOS18_F_12 (O, I, T);
11568 
output O;
11569 
input I;
11570 
input T;
11571 
endmodule
11572 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11573 
module OBUFT_LVCMOS18_F_16 (O, I, T);
11574 
output O;
11575 
input I;
11576 
input T;
11577 
endmodule
11578 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11579 
module OBUFT_LVCMOS18_F_2 (O, I, T);
11580 
output O;
11581 
input I;
11582 
input T;
11583 
endmodule
11584 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11585 
module OBUFT_LVCMOS18_F_4 (O, I, T);
11586 
output O;
11587 
input I;
11588 
input T;
11589 
endmodule
11590 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11591 
module OBUFT_LVCMOS18_F_6 (O, I, T);
11592 
output O;
11593 
input I;
11594 
input T;
11595 
endmodule
11596 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11597 
module OBUFT_LVCMOS18_F_8 (O, I, T);
11598 
output O;
11599 
input I;
11600 
input T;
11601 
endmodule
11602 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11603 
module OBUFT_LVCMOS18_S_12 (O, I, T);
11604 
output O;
11605 
input I;
11606 
input T;
11607 
endmodule
11608 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11609 
module OBUFT_LVCMOS18_S_16 (O, I, T);
11610 
output O;
11611 
input I;
11612 
input T;
11613 
endmodule
11614 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11615 
module OBUFT_LVCMOS18_S_2 (O, I, T);
11616 
output O;
11617 
input I;
11618 
input T;
11619 
endmodule
11620 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11621 
module OBUFT_LVCMOS18_S_4 (O, I, T);
11622 
output O;
11623 
input I;
11624 
input T;
11625 
endmodule
11626 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11627 
module OBUFT_LVCMOS18_S_6 (O, I, T);
11628 
output O;
11629 
input I;
11630 
input T;
11631 
endmodule
11632 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11633 
module OBUFT_LVCMOS18_S_8 (O, I, T);
11634 
output O;
11635 
input I;
11636 
input T;
11637 
endmodule
11638 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11639 
module OBUFT_LVCMOS18 (O, I, T);
11640 
output O;
11641 
input I;
11642 
input T;
11643 
endmodule
11644 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11645 
module OBUFT_LVCMOS25_F_12 (O, I, T);
11646 
output O;
11647 
input I;
11648 
input T;
11649 
endmodule
11650 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11651 
module OBUFT_LVCMOS25_F_16 (O, I, T);
11652 
output O;
11653 
input I;
11654 
input T;
11655 
endmodule
11656 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11657 
module OBUFT_LVCMOS25_F_24 (O, I, T);
11658 
output O;
11659 
input I;
11660 
input T;
11661 
endmodule
11662 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11663 
module OBUFT_LVCMOS25_F_2 (O, I, T);
11664 
output O;
11665 
input I;
11666 
input T;
11667 
endmodule
11668 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11669 
module OBUFT_LVCMOS25_F_4 (O, I, T);
11670 
output O;
11671 
input I;
11672 
input T;
11673 
endmodule
11674 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11675 
module OBUFT_LVCMOS25_F_6 (O, I, T);
11676 
output O;
11677 
input I;
11678 
input T;
11679 
endmodule
11680 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11681 
module OBUFT_LVCMOS25_F_8 (O, I, T);
11682 
output O;
11683 
input I;
11684 
input T;
11685 
endmodule
11686 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11687 
module OBUFT_LVCMOS25_S_12 (O, I, T);
11688 
output O;
11689 
input I;
11690 
input T;
11691 
endmodule
11692 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11693 
module OBUFT_LVCMOS25_S_16 (O, I, T);
11694 
output O;
11695 
input I;
11696 
input T;
11697 
endmodule
11698 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11699 
module OBUFT_LVCMOS25_S_24 (O, I, T);
11700 
output O;
11701 
input I;
11702 
input T;
11703 
endmodule
11704 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11705 
module OBUFT_LVCMOS25_S_2 (O, I, T);
11706 
output O;
11707 
input I;
11708 
input T;
11709 
endmodule
11710 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11711 
module OBUFT_LVCMOS25_S_4 (O, I, T);
11712 
output O;
11713 
input I;
11714 
input T;
11715 
endmodule
11716 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11717 
module OBUFT_LVCMOS25_S_6 (O, I, T);
11718 
output O;
11719 
input I;
11720 
input T;
11721 
endmodule
11722 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11723 
module OBUFT_LVCMOS25_S_8 (O, I, T);
11724 
output O;
11725 
input I;
11726 
input T;
11727 
endmodule
11728 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11729 
module OBUFT_LVCMOS25 (O, I, T);
11730 
output O;
11731 
input I;
11732 
input T;
11733 
endmodule
11734 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11735 
module OBUFT_LVCMOS2 (O, I, T);
11736 
output O;
11737 
input I;
11738 
input T;
11739 
endmodule
11740 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11741 
module OBUFT_LVCMOS33_F_12 (O, I, T);
11742 
output O;
11743 
input I;
11744 
input T;
11745 
endmodule
11746 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11747 
module OBUFT_LVCMOS33_F_16 (O, I, T);
11748 
output O;
11749 
input I;
11750 
input T;
11751 
endmodule
11752 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11753 
module OBUFT_LVCMOS33_F_24 (O, I, T);
11754 
output O;
11755 
input I;
11756 
input T;
11757 
endmodule
11758 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11759 
module OBUFT_LVCMOS33_F_2 (O, I, T);
11760 
output O;
11761 
input I;
11762 
input T;
11763 
endmodule
11764 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11765 
module OBUFT_LVCMOS33_F_4 (O, I, T);
11766 
output O;
11767 
input I;
11768 
input T;
11769 
endmodule
11770 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11771 
module OBUFT_LVCMOS33_F_6 (O, I, T);
11772 
output O;
11773 
input I;
11774 
input T;
11775 
endmodule
11776 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11777 
module OBUFT_LVCMOS33_F_8 (O, I, T);
11778 
output O;
11779 
input I;
11780 
input T;
11781 
endmodule
11782 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11783 
module OBUFT_LVCMOS33_S_12 (O, I, T);
11784 
output O;
11785 
input I;
11786 
input T;
11787 
endmodule
11788 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11789 
module OBUFT_LVCMOS33_S_16 (O, I, T);
11790 
output O;
11791 
input I;
11792 
input T;
11793 
endmodule
11794 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11795 
module OBUFT_LVCMOS33_S_24 (O, I, T);
11796 
output O;
11797 
input I;
11798 
input T;
11799 
endmodule
11800 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11801 
module OBUFT_LVCMOS33_S_2 (O, I, T);
11802 
output O;
11803 
input I;
11804 
input T;
11805 
endmodule
11806 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11807 
module OBUFT_LVCMOS33_S_4 (O, I, T);
11808 
output O;
11809 
input I;
11810 
input T;
11811 
endmodule
11812 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11813 
module OBUFT_LVCMOS33_S_6 (O, I, T);
11814 
output O;
11815 
input I;
11816 
input T;
11817 
endmodule
11818 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11819 
module OBUFT_LVCMOS33_S_8 (O, I, T);
11820 
output O;
11821 
input I;
11822 
input T;
11823 
endmodule
11824 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11825 
module OBUFT_LVCMOS33 (O, I, T);
11826 
output O;
11827 
input I;
11828 
input T;
11829 
endmodule
11830 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11831 
module OBUFT_LVDCI_15 (O, I, T);
11832 
output O;
11833 
input I;
11834 
input T;
11835 
endmodule
11836 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11837 
module OBUFT_LVDCI_18 (O, I, T);
11838 
output O;
11839 
input I;
11840 
input T;
11841 
endmodule
11842 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11843 
module OBUFT_LVDCI_25 (O, I, T);
11844 
output O;
11845 
input I;
11846 
input T;
11847 
endmodule
11848 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11849 
module OBUFT_LVDCI_33 (O, I, T);
11850 
output O;
11851 
input I;
11852 
input T;
11853 
endmodule
11854 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11855 
module OBUFT_LVDCI_DV2_15 (O, I, T);
11856 
output O;
11857 
input I;
11858 
input T;
11859 
endmodule
11860 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11861 
module OBUFT_LVDCI_DV2_18 (O, I, T);
11862 
output O;
11863 
input I;
11864 
input T;
11865 
endmodule
11866 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11867 
module OBUFT_LVDCI_DV2_25 (O, I, T);
11868 
output O;
11869 
input I;
11870 
input T;
11871 
endmodule
11872 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11873 
module OBUFT_LVDCI_DV2_33 (O, I, T);
11874 
output O;
11875 
input I;
11876 
input T;
11877 
endmodule
11878 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11879 
module OBUFT_LVDS (O, I, T);
11880 
output O;
11881 
input I;
11882 
input T;
11883 
endmodule
11884 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11885 
module OBUFT_LVPECL (O, I, T);
11886 
output O;
11887 
input I;
11888 
input T;
11889 
endmodule
11890 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11891 
module OBUFT_LVTTL_F_12 (O, I, T);
11892 
output O;
11893 
input I;
11894 
input T;
11895 
endmodule
11896 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11897 
module OBUFT_LVTTL_F_16 (O, I, T);
11898 
output O;
11899 
input I;
11900 
input T;
11901 
endmodule
11902 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11903 
module OBUFT_LVTTL_F_24 (O, I, T);
11904 
output O;
11905 
input I;
11906 
input T;
11907 
endmodule
11908 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11909 
module OBUFT_LVTTL_F_2 (O, I, T);
11910 
output O;
11911 
input I;
11912 
input T;
11913 
endmodule
11914 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11915 
module OBUFT_LVTTL_F_4 (O, I, T);
11916 
output O;
11917 
input I;
11918 
input T;
11919 
endmodule
11920 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11921 
module OBUFT_LVTTL_F_6 (O, I, T);
11922 
output O;
11923 
input I;
11924 
input T;
11925 
endmodule
11926 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11927 
module OBUFT_LVTTL_F_8 (O, I, T);
11928 
output O;
11929 
input I;
11930 
input T;
11931 
endmodule
11932 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11933 
module OBUFT_LVTTL_S_12 (O, I, T);
11934 
output O;
11935 
input I;
11936 
input T;
11937 
endmodule
11938 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11939 
module OBUFT_LVTTL_S_16 (O, I, T);
11940 
output O;
11941 
input I;
11942 
input T;
11943 
endmodule
11944 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11945 
module OBUFT_LVTTL_S_24 (O, I, T);
11946 
output O;
11947 
input I;
11948 
input T;
11949 
endmodule
11950 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11951 
module OBUFT_LVTTL_S_2 (O, I, T);
11952 
output O;
11953 
input I;
11954 
input T;
11955 
endmodule
11956 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11957 
module OBUFT_LVTTL_S_4 (O, I, T);
11958 
output O;
11959 
input I;
11960 
input T;
11961 
endmodule
11962 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11963 
module OBUFT_LVTTL_S_6 (O, I, T);
11964 
output O;
11965 
input I;
11966 
input T;
11967 
endmodule
11968 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11969 
module OBUFT_LVTTL_S_8 (O, I, T);
11970 
output O;
11971 
input I;
11972 
input T;
11973 
endmodule
11974 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11975 
module OBUFT_LVTTL (O, I, T);
11976 
output O;
11977 
input I;
11978 
input T;
11979 
endmodule
11980 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11981 
module OBUFT_PCI33_3 (O, I, T);
11982 
output O;
11983 
input I;
11984 
input T;
11985 
endmodule
11986 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11987 
module OBUFT_PCI33_5 (O, I, T);
11988 
output O;
11989 
input I;
11990 
input T;
11991 
endmodule
11992 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11993 
module OBUFT_PCI66_3 (O, I, T);
11994 
output O;
11995 
input I;
11996 
input T;
11997 
endmodule
11998 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
11999 
module OBUFT_PCIX66_3 (O, I, T);
12000 
output O;
12001 
input I;
12002 
input T;
12003 
endmodule
12004 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12005 
module OBUFT_PCIX (O, I, T);
12006 
output O;
12007 
input I;
12008 
input T;
12009 
endmodule
12010 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12011 
module OBUFT_S_12 (O, I, T);
12012 
output O;
12013 
input I;
12014 
input T;
12015 
endmodule
12016 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12017 
module OBUFT_S_16 (O, I, T);
12018 
output O;
12019 
input I;
12020 
input T;
12021 
endmodule
12022 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12023 
module OBUFT_S_24 (O, I, T);
12024 
output O;
12025 
input I;
12026 
input T;
12027 
endmodule
12028 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12029 
module OBUFT_S_2 (O, I, T);
12030 
output O;
12031 
input I;
12032 
input T;
12033 
endmodule
12034 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12035 
module OBUFT_S_4 (O, I, T);
12036 
output O;
12037 
input I;
12038 
input T;
12039 
endmodule
12040 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12041 
module OBUFT_S_6 (O, I, T);
12042 
output O;
12043 
input I;
12044 
input T;
12045 
endmodule
12046 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12047 
module OBUFT_S_8 (O, I, T);
12048 
output O;
12049 
input I;
12050 
input T;
12051 
endmodule
12052 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12053 
module OBUFT_SSTL18_I_DCI (O, I, T);
12054 
output O;
12055 
input I;
12056 
input T;
12057 
endmodule
12058 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12059 
module OBUFT_SSTL18_II_DCI (O, I, T);
12060 
output O;
12061 
input I;
12062 
input T;
12063 
endmodule
12064 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12065 
module OBUFT_SSTL18_II (O, I, T);
12066 
output O;
12067 
input I;
12068 
input T;
12069 
endmodule
12070 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12071 
module OBUFT_SSTL18_I (O, I, T);
12072 
output O;
12073 
input I;
12074 
input T;
12075 
endmodule
12076 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12077 
module OBUFT_SSTL2_I_DCI (O, I, T);
12078 
output O;
12079 
input I;
12080 
input T;
12081 
endmodule
12082 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12083 
module OBUFT_SSTL2_II_DCI (O, I, T);
12084 
output O;
12085 
input I;
12086 
input T;
12087 
endmodule
12088 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12089 
module OBUFT_SSTL2_II (O, I, T);
12090 
output O;
12091 
input I;
12092 
input T;
12093 
endmodule
12094 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12095 
module OBUFT_SSTL2_I (O, I, T);
12096 
output O;
12097 
input I;
12098 
input T;
12099 
endmodule
12100 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12101 
module OBUFT_SSTL3_I_DCI (O, I, T);
12102 
output O;
12103 
input I;
12104 
input T;
12105 
endmodule
12106 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12107 
module OBUFT_SSTL3_II_DCI (O, I, T);
12108 
output O;
12109 
input I;
12110 
input T;
12111 
endmodule
12112 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12113 
module OBUFT_SSTL3_II (O, I, T);
12114 
output O;
12115 
input I;
12116 
input T;
12117 
endmodule
12118 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12119 
module OBUFT_SSTL3_I (O, I, T);
12120 
output O;
12121 
input I;
12122 
input T;
12123 
endmodule
12124 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12125 
module OBUFT (O, I, T);
12126 
parameter CAPACITANCE = "DONT_CARE";
12127 
parameter integer DRIVE = 12;
12128 
parameter IOSTANDARD = "DEFAULT";
12129 
parameter SLEW = "SLOW";
12130 
output O;
12131 
input I;
12132 
input T;
12133 
endmodule
12134 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12135 
module OBUF (O, I);
12136 
parameter CAPACITANCE = "DONT_CARE";
12137 
parameter integer DRIVE = 12;
12138 
parameter IOSTANDARD = "DEFAULT";
12139 
parameter SLEW = "SLOW";
12140 
output O;
12141 
input I;
12142 
endmodule
12143 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12144 
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
12145 
parameter DDR_ALIGNMENT = "NONE";
12146 
parameter INIT = 1'b0;
12147 
parameter SRTYPE = "SYNC";
12148 
output Q;
12149 
input C0;
12150 
input C1;
12151 
input CE;
12152 
input D0;
12153 
input D1;
12154 
input R;
12155 
input S;
12156 
endmodule
12157 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12158 
module ODDR (Q, C, CE, D1, D2, R, S);
12159 
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
12160 
parameter INIT = 1'b0;
12161 
parameter SRTYPE = "SYNC";
12162 
output Q;
12163 
input C;
12164 
input CE;
12165 
input D1;
12166 
input D2;
12167 
input R;
12168 
input S;
12169 
endmodule
12170 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12171 
module OFDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);
12172 
output Q;
12173 
input C0;
12174 
input C1;
12175 
input CE;
12176 
input CLR;
12177 
input D0;
12178 
input D1;
12179 
input PRE;
12180 
endmodule
12181 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12182 
module OFDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
12183 
output Q;
12184 
input C0;
12185 
input C1;
12186 
input CE;
12187 
input D0;
12188 
input D1;
12189 
input R;
12190 
input S;
12191 
endmodule
12192 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12193 
module OFDDRTCPE (O, C0, C1, CE, CLR, D0, D1, PRE, T);
12194 
output O;
12195 
input C0;
12196 
input C1;
12197 
input CE;
12198 
input CLR;
12199 
input D0;
12200 
input D1;
12201 
input PRE;
12202 
input T;
12203 
endmodule
12204 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12205 
module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T);
12206 
output O;
12207 
input C0;
12208 
input C1;
12209 
input CE;
12210 
input D0;
12211 
input D1;
12212 
input R;
12213 
input S;
12214 
input T;
12215 
endmodule
12216 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12217 
module OPT_OFF (I);
12218 
input I;
12219 
endmodule
12220 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12221 
module OPT_UIM (I);
12222 
input I;
12223 
endmodule
12224 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12225 
module OR2B1 (O, I0, I1);
12226 
output O;
12227 
input I0;
12228 
input I1;
12229 
endmodule
12230 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12231 
module OR2B2 (O, I0, I1);
12232 
output O;
12233 
input I0;
12234 
input I1;
12235 
endmodule
12236 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12237 
module OR2 (O, I0, I1);
12238 
output O;
12239 
input I0;
12240 
input I1;
12241 
endmodule
12242 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12243 
module OR3B1 (O, I0, I1, I2);
12244 
output O;
12245 
input I0;
12246 
input I1;
12247 
input I2;
12248 
endmodule
12249 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12250 
module OR3B2 (O, I0, I1, I2);
12251 
output O;
12252 
input I0;
12253 
input I1;
12254 
input I2;
12255 
endmodule
12256 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12257 
module OR3B3 (O, I0, I1, I2);
12258 
output O;
12259 
input I0;
12260 
input I1;
12261 
input I2;
12262 
endmodule
12263 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12264 
module OR3 (O, I0, I1, I2);
12265 
output O;
12266 
input I0;
12267 
input I1;
12268 
input I2;
12269 
endmodule
12270 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12271 
module OR4B1 (O, I0, I1, I2, I3);
12272 
output O;
12273 
input I0;
12274 
input I1;
12275 
input I2;
12276 
input I3;
12277 
endmodule
12278 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12279 
module OR4B2 (O, I0, I1, I2, I3);
12280 
output O;
12281 
input I0;
12282 
input I1;
12283 
input I2;
12284 
input I3;
12285 
endmodule
12286 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12287 
module OR4B3 (O, I0, I1, I2, I3);
12288 
output O;
12289 
input I0;
12290 
input I1;
12291 
input I2;
12292 
input I3;
12293 
endmodule
12294 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12295 
module OR4B4 (O, I0, I1, I2, I3);
12296 
output O;
12297 
input I0;
12298 
input I1;
12299 
input I2;
12300 
input I3;
12301 
endmodule
12302 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12303 
module OR4 (O, I0, I1, I2, I3);
12304 
output O;
12305 
input I0;
12306 
input I1;
12307 
input I2;
12308 
input I3;
12309 
endmodule
12310 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12311 
module OR5B1 (O, I0, I1, I2, I3, I4);
12312 
output O;
12313 
input I0;
12314 
input I1;
12315 
input I2;
12316 
input I3;
12317 
input I4;
12318 
endmodule
12319 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12320 
module OR5B2 (O, I0, I1, I2, I3, I4);
12321 
output O;
12322 
input I0;
12323 
input I1;
12324 
input I2;
12325 
input I3;
12326 
input I4;
12327 
endmodule
12328 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12329 
module OR5B3 (O, I0, I1, I2, I3, I4);
12330 
output O;
12331 
input I0;
12332 
input I1;
12333 
input I2;
12334 
input I3;
12335 
input I4;
12336 
endmodule
12337 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12338 
module OR5B4 (O, I0, I1, I2, I3, I4);
12339 
output O;
12340 
input I0;
12341 
input I1;
12342 
input I2;
12343 
input I3;
12344 
input I4;
12345 
endmodule
12346 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12347 
module OR5B5 (O, I0, I1, I2, I3, I4);
12348 
output O;
12349 
input I0;
12350 
input I1;
12351 
input I2;
12352 
input I3;
12353 
input I4;
12354 
endmodule
12355 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12356 
module OR5 (O, I0, I1, I2, I3, I4);
12357 
output O;
12358 
input I0;
12359 
input I1;
12360 
input I2;
12361 
input I3;
12362 
input I4;
12363 
endmodule
12364 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12365 
module OR6 (O, I0, I1, I2, I3, I4, I5);
12366 
output O;
12367 
input I0;
12368 
input I1;
12369 
input I2;
12370 
input I3;
12371 
input I4;
12372 
input I5;
12373 
endmodule
12374 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12375 
module OR7 (O, I0, I1, I2, I3, I4, I5, I6);
12376 
output O;
12377 
input I0;
12378 
input I1;
12379 
input I2;
12380 
input I3;
12381 
input I4;
12382 
input I5;
12383 
input I6;
12384 
endmodule
12385 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12386 
module OR8 (O, I0, I1, I2, I3, I4, I5, I6, I7);
12387 
output O;
12388 
input I0;
12389 
input I1;
12390 
input I2;
12391 
input I3;
12392 
input I4;
12393 
input I5;
12394 
input I6;
12395 
input I7;
12396 
endmodule
12397 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12398 
module ORCY (O, CI, I);
12399 
output O;
12400 
input CI;
12401 
input I;
12402 
endmodule
12403 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12404 
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
12405 
parameter DATA_RATE_OQ = "DDR";
12406 
parameter DATA_RATE_TQ = "DDR";
12407 
parameter integer DATA_WIDTH = 4;
12408 
parameter INIT_OQ = 1'b0;
12409 
parameter INIT_TQ = 1'b0;
12410 
parameter SERDES_MODE = "MASTER";
12411 
parameter SRVAL_OQ = 1'b0;
12412 
parameter SRVAL_TQ = 1'b0;
12413 
parameter integer TRISTATE_WIDTH = 4;
12414 
output OQ;
12415 
output SHIFTOUT1;
12416 
output SHIFTOUT2;
12417 
output TQ;
12418 
input CLK;
12419 
input CLKDIV;
12420 
input D1;
12421 
input D2;
12422 
input D3;
12423 
input D4;
12424 
input D5;
12425 
input D6;
12426 
input OCE;
12427 
input REV;
12428 
input SHIFTIN1;
12429 
input SHIFTIN2;
12430 
input SR;
12431 
input T1;
12432 
input T2;
12433 
input T3;
12434 
input T4;
12435 
input TCE;
12436 
endmodule
12437 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12438 
module PCIE_EP (BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0CFGLOOPBACKACK, L0COMPLETERID, L0DLLERRORVECTOR, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0DLLVCSTATUS, L0DLUPDOWN, L0FIRSTCFGWRITEOCCURRED, L0LTSSMSTATE, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEGOTIATEDLINKWIDTH, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MSIENABLE0, L0MULTIMSGEN0, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0PWRL1STATE, L0PWRL23READYSTATE, L0PWRSTATE0, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RXDLLPM, L0RXDLLPMTYPE, L0RXMACLINKERROR, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0UNLOCKRECEIVED, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHNONPOSTEDAVAILABLEN, LLKRXCHPOSTEDAVAILABLEN, LLKRXDATA, LLKRXEOFN, LLKRXEOPN, LLKRXPREFERREDTYPE, LLKRXSOFN, LLKRXSOPN, LLKRXSRCLASTREQN, LLKRXSRCRDYN, LLKRXVALIDN, LLKTCSTATUS, LLKTXCHANSPACE, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MEMSPACEENABLE, MGMTPSO, MGMTRDATA, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBREN, MIMDLLBWADD, MIMDLLBWDATA, MIMDLLBWEN, MIMRXBRADD, MIMRXBREN, MIMRXBWADD, MIMRXBWDATA, MIMRXBWEN, MIMTXBRADD, MIMTXBREN, MIMTXBWADD, MIMTXBWDATA, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, PIPERESETL0, PIPERESETL1, PIPERESETL2, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, AUXPOWER, COMPLIANCEAVOID, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, L0CFGDISABLESCRAMBLE, L0CFGLOOPBACKMASTER, L0LEGACYINTFUNCT0, L0MSIREQUEST0, L0PACKETHEADERFROMUSER, L0PMEREQIN, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TRANSACTIONSPENDING, LLKRXCHFIFO, LLKRXCHTC, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTXCHFIFO, LLKTXCHTC, LLKTXDATA, LLKTXENABLEN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MGMTADDR, MGMTBWREN, MGMTRDEN, MGMTSTATSCREDITSEL, MGMTWDATA, MGMTWREN, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7);
12439 
parameter BAR0EXIST = "TRUE";
12440 
parameter BAR0PREFETCHABLE = "TRUE";
12441 
parameter BAR1EXIST = "FALSE";
12442 
parameter BAR1PREFETCHABLE = "FALSE";
12443 
parameter BAR2EXIST = "FALSE";
12444 
parameter BAR2PREFETCHABLE = "FALSE";
12445 
parameter BAR3EXIST = "FALSE";
12446 
parameter BAR3PREFETCHABLE = "FALSE";
12447 
parameter BAR4EXIST = "FALSE";
12448 
parameter BAR4PREFETCHABLE = "FALSE";
12449 
parameter BAR5EXIST = "FALSE";
12450 
parameter BAR5PREFETCHABLE = "FALSE";
12451 
parameter CLKDIVIDED = "FALSE";
12452 
parameter INFINITECOMPLETIONS = "TRUE";
12453 
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE";
12454 
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
12455 
parameter PMCAPABILITYD1SUPPORT = "FALSE";
12456 
parameter PMCAPABILITYD2SUPPORT = "FALSE";
12457 
parameter PMCAPABILITYDSI = "TRUE";
12458 
parameter RESETMODE = "FALSE";
12459 
parameter [10:0] VC0TOTALCREDITSCD = 11'h0;
12460 
parameter [10:0] VC0TOTALCREDITSPD = 11'h34;
12461 
parameter [10:0] VC1TOTALCREDITSCD = 11'h0;
12462 
parameter [10:0] VC1TOTALCREDITSPD = 11'h0;
12463 
parameter [11:0] AERBASEPTR = 12'h110;
12464 
parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138;
12465 
parameter [11:0] DSNBASEPTR = 12'h148;
12466 
parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154;
12467 
parameter [11:0] MSIBASEPTR = 12'h48;
12468 
parameter [11:0] PBBASEPTR = 12'h138;
12469 
parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148;
12470 
parameter [11:0] PMBASEPTR = 12'h40;
12471 
parameter [11:0] RETRYRAMSIZE = 12'h9;
12472 
parameter [11:0] VCBASEPTR = 12'h154;
12473 
parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0;
12474 
parameter [12:0] VC0RXFIFOBASEC = 13'h98;
12475 
parameter [12:0] VC0RXFIFOBASENP = 13'h80;
12476 
parameter [12:0] VC0RXFIFOBASEP = 13'h0;
12477 
parameter [12:0] VC0RXFIFOLIMITC = 13'h117;
12478 
parameter [12:0] VC0RXFIFOLIMITNP = 13'h97;
12479 
parameter [12:0] VC0RXFIFOLIMITP = 13'h7f;
12480 
parameter [12:0] VC0TXFIFOBASEC = 13'h98;
12481 
parameter [12:0] VC0TXFIFOBASENP = 13'h80;
12482 
parameter [12:0] VC0TXFIFOBASEP = 13'h0;
12483 
parameter [12:0] VC0TXFIFOLIMITC = 13'h117;
12484 
parameter [12:0] VC0TXFIFOLIMITNP = 13'h97;
12485 
parameter [12:0] VC0TXFIFOLIMITP = 13'h7f;
12486 
parameter [12:0] VC1RXFIFOBASEC = 13'h118;
12487 
parameter [12:0] VC1RXFIFOBASENP = 13'h118;
12488 
parameter [12:0] VC1RXFIFOBASEP = 13'h118;
12489 
parameter [12:0] VC1RXFIFOLIMITC = 13'h118;
12490 
parameter [12:0] VC1RXFIFOLIMITNP = 13'h118;
12491 
parameter [12:0] VC1RXFIFOLIMITP = 13'h118;
12492 
parameter [12:0] VC1TXFIFOBASEC = 13'h118;
12493 
parameter [12:0] VC1TXFIFOBASENP = 13'h118;
12494 
parameter [12:0] VC1TXFIFOBASEP = 13'h118;
12495 
parameter [12:0] VC1TXFIFOLIMITC = 13'h118;
12496 
parameter [12:0] VC1TXFIFOLIMITNP = 13'h118;
12497 
parameter [12:0] VC1TXFIFOLIMITP = 13'h118;
12498 
parameter [15:0] DEVICEID = 16'h5050;
12499 
parameter [15:0] SUBSYSTEMID = 16'h5050;
12500 
parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE;
12501 
parameter [15:0] VENDORID = 16'h10EE;
12502 
parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1;
12503 
parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0;
12504 
parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0;
12505 
parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0;
12506 
parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0;
12507 
parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0;
12508 
parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0;
12509 
parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0;
12510 
parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0;
12511 
parameter [23:0] CLASSCODE = 24'h058000;
12512 
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0;
12513 
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0;
12514 
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0;
12515 
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0;
12516 
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0;
12517 
parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0;
12518 
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0;
12519 
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0;
12520 
parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0;
12521 
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0;
12522 
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0;
12523 
parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0;
12524 
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0;
12525 
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0;
12526 
parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0;
12527 
parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0;
12528 
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0;
12529 
parameter [31:0] CARDBUSCISPOINTER = 32'h0;
12530 
parameter [3:0] XPDEVICEPORTTYPE = 4'h0;
12531 
parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0;
12532 
parameter [5:0] BAR0MASKWIDTH = 6'h14;
12533 
parameter [5:0] BAR1MASKWIDTH = 6'h0;
12534 
parameter [5:0] BAR2MASKWIDTH = 6'h0;
12535 
parameter [5:0] BAR3MASKWIDTH = 6'h0;
12536 
parameter [5:0] BAR4MASKWIDTH = 6'h0;
12537 
parameter [5:0] BAR5MASKWIDTH = 6'h0;
12538 
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01;
12539 
parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35;
12540 
parameter [6:0] VC0TOTALCREDITSCH = 7'h0;
12541 
parameter [6:0] VC0TOTALCREDITSNPH = 7'h08;
12542 
parameter [6:0] VC0TOTALCREDITSPH = 7'h08;
12543 
parameter [6:0] VC1TOTALCREDITSCH = 7'h0;
12544 
parameter [6:0] VC1TOTALCREDITSNPH = 7'h0;
12545 
parameter [6:0] VC1TOTALCREDITSPH = 7'h0;
12546 
parameter [7:0] ACTIVELANESIN = 8'h1;
12547 
parameter [7:0] CAPABILITIESPOINTER = 8'h40;
12548 
parameter [7:0] INTERRUPTPIN = 8'h0;
12549 
parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60;
12550 
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0;
12551 
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0;
12552 
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0;
12553 
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0;
12554 
parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0;
12555 
parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60;
12556 
parameter [7:0] PMDATA0 = 8'h0;
12557 
parameter [7:0] PMDATA1 = 8'h0;
12558 
parameter [7:0] PMDATA2 = 8'h0;
12559 
parameter [7:0] PMDATA3 = 8'h0;
12560 
parameter [7:0] PMDATA4 = 8'h0;
12561 
parameter [7:0] PMDATA5 = 8'h0;
12562 
parameter [7:0] PMDATA6 = 8'h0;
12563 
parameter [7:0] PMDATA7 = 8'h0;
12564 
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0;
12565 
parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0;
12566 
parameter [7:0] REVISIONID = 8'h0;
12567 
parameter [7:0] XPBASEPTR = 8'h60;
12568 
parameter integer BAR0ADDRWIDTH = 0;
12569 
parameter integer BAR0IOMEMN = 0;
12570 
parameter integer BAR1ADDRWIDTH = 0;
12571 
parameter integer BAR1IOMEMN = 0;
12572 
parameter integer BAR2ADDRWIDTH = 0;
12573 
parameter integer BAR2IOMEMN = 0;
12574 
parameter integer BAR3ADDRWIDTH = 0;
12575 
parameter integer BAR3IOMEMN = 0;
12576 
parameter integer BAR4ADDRWIDTH = 0;
12577 
parameter integer BAR4IOMEMN = 0;
12578 
parameter integer BAR5IOMEMN = 0;
12579 
parameter integer L0SEXITLATENCY = 7;
12580 
parameter integer L0SEXITLATENCYCOMCLK = 7;
12581 
parameter integer L1EXITLATENCY = 7;
12582 
parameter integer L1EXITLATENCYCOMCLK = 7;
12583 
parameter integer LOWPRIORITYVCCOUNT = 0;
12584 
parameter integer PMDATASCALE0 = 0;
12585 
parameter integer PMDATASCALE1 = 0;
12586 
parameter integer PMDATASCALE2 = 0;
12587 
parameter integer PMDATASCALE3 = 0;
12588 
parameter integer PMDATASCALE4 = 0;
12589 
parameter integer PMDATASCALE5 = 0;
12590 
parameter integer PMDATASCALE6 = 0;
12591 
parameter integer PMDATASCALE7 = 0;
12592 
parameter integer RETRYRAMREADLATENCY = 3;
12593 
parameter integer RETRYRAMWRITELATENCY = 1;
12594 
parameter integer TLRAMREADLATENCY = 3;
12595 
parameter integer TLRAMWRITELATENCY = 1;
12596 
parameter integer TXTSNFTS = 255;
12597 
parameter integer TXTSNFTSCOMCLK = 255;
12598 
parameter integer XPMAXPAYLOAD = 0;
12599 
output BUSMASTERENABLE;
12600 
output CRMDOHOTRESETN;
12601 
output CRMPWRSOFTRESETN;
12602 
output DLLTXPMDLLPOUTSTANDING;
12603 
output INTERRUPTDISABLE;
12604 
output IOSPACEENABLE;
12605 
output L0CFGLOOPBACKACK;
12606 
output [12:0] L0COMPLETERID;
12607 
output [6:0] L0DLLERRORVECTOR;
12608 
output L0DLLRXACKOUTSTANDING;
12609 
output L0DLLTXNONFCOUTSTANDING;
12610 
output L0DLLTXOUTSTANDING;
12611 
output [7:0] L0DLLVCSTATUS;
12612 
output [7:0] L0DLUPDOWN;
12613 
output L0FIRSTCFGWRITEOCCURRED;
12614 
output [3:0] L0LTSSMSTATE;
12615 
output L0MACENTEREDL0;
12616 
output L0MACLINKTRAINING;
12617 
output L0MACLINKUP;
12618 
output [3:0] L0MACNEGOTIATEDLINKWIDTH;
12619 
output L0MACNEWSTATEACK;
12620 
output L0MACRXL0SSTATE;
12621 
output L0MSIENABLE0;
12622 
output [2:0] L0MULTIMSGEN0;
12623 
output L0PMEACK;
12624 
output L0PMEEN;
12625 
output L0PMEREQOUT;
12626 
output L0PWRL1STATE;
12627 
output L0PWRL23READYSTATE;
12628 
output [1:0] L0PWRSTATE0;
12629 
output L0PWRTURNOFFREQ;
12630 
output L0PWRTXL0SSTATE;
12631 
output L0RXDLLPM;
12632 
output [2:0] L0RXDLLPMTYPE;
12633 
output [1:0] L0RXMACLINKERROR;
12634 
output L0STATSCFGOTHERRECEIVED;
12635 
output L0STATSCFGOTHERTRANSMITTED;
12636 
output L0STATSCFGRECEIVED;
12637 
output L0STATSCFGTRANSMITTED;
12638 
output L0STATSDLLPRECEIVED;
12639 
output L0STATSDLLPTRANSMITTED;
12640 
output L0STATSOSRECEIVED;
12641 
output L0STATSOSTRANSMITTED;
12642 
output L0STATSTLPRECEIVED;
12643 
output L0STATSTLPTRANSMITTED;
12644 
output L0UNLOCKRECEIVED;
12645 
output [7:0] LLKRXCHCOMPLETIONAVAILABLEN;
12646 
output [7:0] LLKRXCHNONPOSTEDAVAILABLEN;
12647 
output [7:0] LLKRXCHPOSTEDAVAILABLEN;
12648 
output [63:0] LLKRXDATA;
12649 
output LLKRXEOFN;
12650 
output LLKRXEOPN;
12651 
output [15:0] LLKRXPREFERREDTYPE;
12652 
output LLKRXSOFN;
12653 
output LLKRXSOPN;
12654 
output LLKRXSRCLASTREQN;
12655 
output LLKRXSRCRDYN;
12656 
output [1:0] LLKRXVALIDN;
12657 
output [7:0] LLKTCSTATUS;
12658 
output [9:0] LLKTXCHANSPACE;
12659 
output [7:0] LLKTXCHCOMPLETIONREADYN;
12660 
output [7:0] LLKTXCHNONPOSTEDREADYN;
12661 
output [7:0] LLKTXCHPOSTEDREADYN;
12662 
output LLKTXCONFIGREADYN;
12663 
output LLKTXDSTRDYN;
12664 
output [2:0] MAXPAYLOADSIZE;
12665 
output [2:0] MAXREADREQUESTSIZE;
12666 
output MEMSPACEENABLE;
12667 
output [16:0] MGMTPSO;
12668 
output [31:0] MGMTRDATA;
12669 
output [11:0] MGMTSTATSCREDIT;
12670 
output [11:0] MIMDLLBRADD;
12671 
output MIMDLLBREN;
12672 
output [11:0] MIMDLLBWADD;
12673 
output [63:0] MIMDLLBWDATA;
12674 
output MIMDLLBWEN;
12675 
output [12:0] MIMRXBRADD;
12676 
output MIMRXBREN;
12677 
output [12:0] MIMRXBWADD;
12678 
output [63:0] MIMRXBWDATA;
12679 
output MIMRXBWEN;
12680 
output [12:0] MIMTXBRADD;
12681 
output MIMTXBREN;
12682 
output [12:0] MIMTXBWADD;
12683 
output [63:0] MIMTXBWDATA;
12684 
output MIMTXBWEN;
12685 
output PARITYERRORRESPONSE;
12686 
output PIPEDESKEWLANESL0;
12687 
output PIPEDESKEWLANESL1;
12688 
output PIPEDESKEWLANESL2;
12689 
output PIPEDESKEWLANESL3;
12690 
output PIPEDESKEWLANESL4;
12691 
output PIPEDESKEWLANESL5;
12692 
output PIPEDESKEWLANESL6;
12693 
output PIPEDESKEWLANESL7;
12694 
output [1:0] PIPEPOWERDOWNL0;
12695 
output [1:0] PIPEPOWERDOWNL1;
12696 
output [1:0] PIPEPOWERDOWNL2;
12697 
output [1:0] PIPEPOWERDOWNL3;
12698 
output [1:0] PIPEPOWERDOWNL4;
12699 
output [1:0] PIPEPOWERDOWNL5;
12700 
output [1:0] PIPEPOWERDOWNL6;
12701 
output [1:0] PIPEPOWERDOWNL7;
12702 
output PIPERESETL0;
12703 
output PIPERESETL1;
12704 
output PIPERESETL2;
12705 
output PIPERESETL3;
12706 
output PIPERESETL4;
12707 
output PIPERESETL5;
12708 
output PIPERESETL6;
12709 
output PIPERESETL7;
12710 
output PIPERXPOLARITYL0;
12711 
output PIPERXPOLARITYL1;
12712 
output PIPERXPOLARITYL2;
12713 
output PIPERXPOLARITYL3;
12714 
output PIPERXPOLARITYL4;
12715 
output PIPERXPOLARITYL5;
12716 
output PIPERXPOLARITYL6;
12717 
output PIPERXPOLARITYL7;
12718 
output PIPETXCOMPLIANCEL0;
12719 
output PIPETXCOMPLIANCEL1;
12720 
output PIPETXCOMPLIANCEL2;
12721 
output PIPETXCOMPLIANCEL3;
12722 
output PIPETXCOMPLIANCEL4;
12723 
output PIPETXCOMPLIANCEL5;
12724 
output PIPETXCOMPLIANCEL6;
12725 
output PIPETXCOMPLIANCEL7;
12726 
output PIPETXDATAKL0;
12727 
output PIPETXDATAKL1;
12728 
output PIPETXDATAKL2;
12729 
output PIPETXDATAKL3;
12730 
output PIPETXDATAKL4;
12731 
output PIPETXDATAKL5;
12732 
output PIPETXDATAKL6;
12733 
output PIPETXDATAKL7;
12734 
output [7:0] PIPETXDATAL0;
12735 
output [7:0] PIPETXDATAL1;
12736 
output [7:0] PIPETXDATAL2;
12737 
output [7:0] PIPETXDATAL3;
12738 
output [7:0] PIPETXDATAL4;
12739 
output [7:0] PIPETXDATAL5;
12740 
output [7:0] PIPETXDATAL6;
12741 
output [7:0] PIPETXDATAL7;
12742 
output PIPETXDETECTRXLOOPBACKL0;
12743 
output PIPETXDETECTRXLOOPBACKL1;
12744 
output PIPETXDETECTRXLOOPBACKL2;
12745 
output PIPETXDETECTRXLOOPBACKL3;
12746 
output PIPETXDETECTRXLOOPBACKL4;
12747 
output PIPETXDETECTRXLOOPBACKL5;
12748 
output PIPETXDETECTRXLOOPBACKL6;
12749 
output PIPETXDETECTRXLOOPBACKL7;
12750 
output PIPETXELECIDLEL0;
12751 
output PIPETXELECIDLEL1;
12752 
output PIPETXELECIDLEL2;
12753 
output PIPETXELECIDLEL3;
12754 
output PIPETXELECIDLEL4;
12755 
output PIPETXELECIDLEL5;
12756 
output PIPETXELECIDLEL6;
12757 
output PIPETXELECIDLEL7;
12758 
output SERRENABLE;
12759 
output URREPORTINGENABLE;
12760 
input AUXPOWER;
12761 
input COMPLIANCEAVOID;
12762 
input CRMCORECLK;
12763 
input CRMCORECLKDLO;
12764 
input CRMCORECLKRXO;
12765 
input CRMCORECLKTXO;
12766 
input CRMLINKRSTN;
12767 
input CRMMACRSTN;
12768 
input CRMMGMTRSTN;
12769 
input CRMNVRSTN;
12770 
input CRMURSTN;
12771 
input CRMUSERCFGRSTN;
12772 
input CRMUSERCLK;
12773 
input CRMUSERCLKRXO;
12774 
input CRMUSERCLKTXO;
12775 
input L0CFGDISABLESCRAMBLE;
12776 
input L0CFGLOOPBACKMASTER;
12777 
input L0LEGACYINTFUNCT0;
12778 
input [3:0] L0MSIREQUEST0;
12779 
input [127:0] L0PACKETHEADERFROMUSER;
12780 
input L0PMEREQIN;
12781 
input L0SETCOMPLETERABORTERROR;
12782 
input L0SETCOMPLETIONTIMEOUTCORRERROR;
12783 
input L0SETCOMPLETIONTIMEOUTUNCORRERROR;
12784 
input L0SETDETECTEDCORRERROR;
12785 
input L0SETDETECTEDFATALERROR;
12786 
input L0SETDETECTEDNONFATALERROR;
12787 
input L0SETUNEXPECTEDCOMPLETIONCORRERROR;
12788 
input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR;
12789 
input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR;
12790 
input L0SETUNSUPPORTEDREQUESTOTHERERROR;
12791 
input L0SETUSERDETECTEDPARITYERROR;
12792 
input L0SETUSERMASTERDATAPARITY;
12793 
input L0SETUSERRECEIVEDMASTERABORT;
12794 
input L0SETUSERRECEIVEDTARGETABORT;
12795 
input L0SETUSERSIGNALLEDTARGETABORT;
12796 
input L0SETUSERSYSTEMERROR;
12797 
input L0TRANSACTIONSPENDING;
12798 
input [1:0] LLKRXCHFIFO;
12799 
input [2:0] LLKRXCHTC;
12800 
input LLKRXDSTCONTREQN;
12801 
input LLKRXDSTREQN;
12802 
input [1:0] LLKTXCHFIFO;
12803 
input [2:0] LLKTXCHTC;
12804 
input [63:0] LLKTXDATA;
12805 
input [1:0] LLKTXENABLEN;
12806 
input LLKTXEOFN;
12807 
input LLKTXEOPN;
12808 
input LLKTXSOFN;
12809 
input LLKTXSOPN;
12810 
input LLKTXSRCDSCN;
12811 
input LLKTXSRCRDYN;
12812 
input [10:0] MGMTADDR;
12813 
input [3:0] MGMTBWREN;
12814 
input MGMTRDEN;
12815 
input [6:0] MGMTSTATSCREDITSEL;
12816 
input [31:0] MGMTWDATA;
12817 
input MGMTWREN;
12818 
input [63:0] MIMDLLBRDATA;
12819 
input [63:0] MIMRXBRDATA;
12820 
input [63:0] MIMTXBRDATA;
12821 
input PIPEPHYSTATUSL0;
12822 
input PIPEPHYSTATUSL1;
12823 
input PIPEPHYSTATUSL2;
12824 
input PIPEPHYSTATUSL3;
12825 
input PIPEPHYSTATUSL4;
12826 
input PIPEPHYSTATUSL5;
12827 
input PIPEPHYSTATUSL6;
12828 
input PIPEPHYSTATUSL7;
12829 
input PIPERXCHANISALIGNEDL0;
12830 
input PIPERXCHANISALIGNEDL1;
12831 
input PIPERXCHANISALIGNEDL2;
12832 
input PIPERXCHANISALIGNEDL3;
12833 
input PIPERXCHANISALIGNEDL4;
12834 
input PIPERXCHANISALIGNEDL5;
12835 
input PIPERXCHANISALIGNEDL6;
12836 
input PIPERXCHANISALIGNEDL7;
12837 
input PIPERXDATAKL0;
12838 
input PIPERXDATAKL1;
12839 
input PIPERXDATAKL2;
12840 
input PIPERXDATAKL3;
12841 
input PIPERXDATAKL4;
12842 
input PIPERXDATAKL5;
12843 
input PIPERXDATAKL6;
12844 
input PIPERXDATAKL7;
12845 
input [7:0] PIPERXDATAL0;
12846 
input [7:0] PIPERXDATAL1;
12847 
input [7:0] PIPERXDATAL2;
12848 
input [7:0] PIPERXDATAL3;
12849 
input [7:0] PIPERXDATAL4;
12850 
input [7:0] PIPERXDATAL5;
12851 
input [7:0] PIPERXDATAL6;
12852 
input [7:0] PIPERXDATAL7;
12853 
input PIPERXELECIDLEL0;
12854 
input PIPERXELECIDLEL1;
12855 
input PIPERXELECIDLEL2;
12856 
input PIPERXELECIDLEL3;
12857 
input PIPERXELECIDLEL4;
12858 
input PIPERXELECIDLEL5;
12859 
input PIPERXELECIDLEL6;
12860 
input PIPERXELECIDLEL7;
12861 
input [2:0] PIPERXSTATUSL0;
12862 
input [2:0] PIPERXSTATUSL1;
12863 
input [2:0] PIPERXSTATUSL2;
12864 
input [2:0] PIPERXSTATUSL3;
12865 
input [2:0] PIPERXSTATUSL4;
12866 
input [2:0] PIPERXSTATUSL5;
12867 
input [2:0] PIPERXSTATUSL6;
12868 
input [2:0] PIPERXSTATUSL7;
12869 
input PIPERXVALIDL0;
12870 
input PIPERXVALIDL1;
12871 
input PIPERXVALIDL2;
12872 
input PIPERXVALIDL3;
12873 
input PIPERXVALIDL4;
12874 
input PIPERXVALIDL5;
12875 
input PIPERXVALIDL6;
12876 
input PIPERXVALIDL7;
12877 
endmodule
12878 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
12879 
module PCIE_INTERNAL_1_1 (BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, CRMRXHOTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0ASAUTONOMOUSINITCOMPLETED, L0ATTENTIONINDICATORCONTROL, L0CFGLOOPBACKACK, L0COMPLETERID, L0CORRERRMSGRCVD, L0DLLASRXSTATE, L0DLLASTXSTATE, L0DLLERRORVECTOR, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0DLLVCSTATUS, L0DLUPDOWN, L0ERRMSGREQID, L0FATALERRMSGRCVD, L0FIRSTCFGWRITEOCCURRED, L0FWDCORRERROUT, L0FWDFATALERROUT, L0FWDNONFATALERROUT, L0LTSSMSTATE, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEGOTIATEDLINKWIDTH, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MACUPSTREAMDOWNSTREAM, L0MCFOUND, L0MSIENABLE0, L0MULTIMSGEN0, L0NONFATALERRMSGRCVD, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0POWERCONTROLLERCONTROL, L0POWERINDICATORCONTROL, L0PWRINHIBITTRANSFERS, L0PWRL1STATE, L0PWRL23READYDEVICE, L0PWRL23READYSTATE, L0PWRSTATE0, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RECEIVEDASSERTINTALEGACYINT, L0RECEIVEDASSERTINTBLEGACYINT, L0RECEIVEDASSERTINTCLEGACYINT, L0RECEIVEDASSERTINTDLEGACYINT, L0RECEIVEDDEASSERTINTALEGACYINT, L0RECEIVEDDEASSERTINTBLEGACYINT, L0RECEIVEDDEASSERTINTCLEGACYINT, L0RECEIVEDDEASSERTINTDLEGACYINT, L0RXBEACON, L0RXDLLFCCMPLMCCRED, L0RXDLLFCCMPLMCUPDATE, L0RXDLLFCNPOSTBYPCRED, L0RXDLLFCNPOSTBYPUPDATE, L0RXDLLFCPOSTORDCRED, L0RXDLLFCPOSTORDUPDATE, L0RXDLLPM, L0RXDLLPMTYPE, L0RXDLLSBFCDATA, L0RXDLLSBFCUPDATE, L0RXDLLTLPECRCOK, L0RXDLLTLPEND, L0RXMACLINKERROR, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0TOGGLEELECTROMECHANICALINTERLOCK, L0TRANSFORMEDVC, L0TXDLLFCCMPLMCUPDATED, L0TXDLLFCNPOSTBYPUPDATED, L0TXDLLFCPOSTORDUPDATED, L0TXDLLPMUPDATED, L0TXDLLSBFCUPDATED, L0UCBYPFOUND, L0UCORDFOUND, L0UNLOCKRECEIVED, LLKRX4DWHEADERN, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHCOMPLETIONPARTIALN, LLKRXCHCONFIGAVAILABLEN, LLKRXCHCONFIGPARTIALN, LLKRXCHNONPOSTEDAVAILABLEN, LLKRXCHNONPOSTEDPARTIALN, LLKRXCHPOSTEDAVAILABLEN, LLKRXCHPOSTEDPARTIALN, LLKRXDATA, LLKRXECRCBADN, LLKRXEOFN, LLKRXEOPN, LLKRXPREFERREDTYPE, LLKRXSOFN, LLKRXSOPN, LLKRXSRCDSCN, LLKRXSRCLASTREQN, LLKRXSRCRDYN, LLKRXVALIDN, LLKTCSTATUS, LLKTXCHANSPACE, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MEMSPACEENABLE, MGMTPSO, MGMTRDATA, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBREN, MIMDLLBWADD, MIMDLLBWDATA, MIMDLLBWEN, MIMRXBRADD, MIMRXBREN, MIMRXBWADD, MIMRXBWDATA, MIMRXBWEN, MIMTXBRADD, MIMTXBREN, MIMTXBWADD, MIMTXBWDATA, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, PIPERESETL0, PIPERESETL1, PIPERESETL2, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, AUXPOWER, CFGNEGOTIATEDLINKWIDTH, COMPLIANCEAVOID, CRMCFGBRIDGEHOTRESET, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMTXHOTRESETN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, CROSSLINKSEED, L0ACKNAKTIMERADJUSTMENT, L0ALLDOWNPORTSINL1, L0ALLDOWNRXPORTSINL0S, L0ASE, L0ASPORTCOUNT, L0ASTURNPOOLBITSCONSUMED, L0ATTENTIONBUTTONPRESSED, L0CFGASSPANTREEOWNEDSTATE, L0CFGASSTATECHANGECMD, L0CFGDISABLESCRAMBLE, L0CFGEXTENDEDSYNC, L0CFGL0SENTRYENABLE, L0CFGL0SENTRYSUP, L0CFGL0SEXITLAT, L0CFGLINKDISABLE, L0CFGLOOPBACKMASTER, L0CFGNEGOTIATEDMAXP, L0CFGVCENABLE, L0CFGVCID, L0DLLHOLDLINKUP, L0ELECTROMECHANICALINTERLOCKENGAGED, L0FWDASSERTINTALEGACYINT, L0FWDASSERTINTBLEGACYINT, L0FWDASSERTINTCLEGACYINT, L0FWDASSERTINTDLEGACYINT, L0FWDCORRERRIN, L0FWDDEASSERTINTALEGACYINT, L0FWDDEASSERTINTBLEGACYINT, L0FWDDEASSERTINTCLEGACYINT, L0FWDDEASSERTINTDLEGACYINT, L0FWDFATALERRIN, L0FWDNONFATALERRIN, L0LEGACYINTFUNCT0, L0MRLSENSORCLOSEDN, L0MSIREQUEST0, L0PACKETHEADERFROMUSER, L0PMEREQIN, L0PORTNUMBER, L0POWERFAULTDETECTED, L0PRESENCEDETECTSLOTEMPTYN, L0PWRNEWSTATEREQ, L0PWRNEXTLINKSTATE, L0REPLAYTIMERADJUSTMENT, L0ROOTTURNOFFREQ, L0RXTLTLPNONINITIALIZEDVC, L0SENDUNLOCKMESSAGE, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETLINKDETECTEDPARITYERROR, L0SETLINKMASTERDATAPARITY, L0SETLINKRECEIVEDMASTERABORT, L0SETLINKRECEIVEDTARGETABORT, L0SETLINKSIGNALLEDTARGETABORT, L0SETLINKSYSTEMERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TLASFCCREDSTARVATION, L0TLLINKRETRAIN, L0TRANSACTIONSPENDING, L0TXBEACON, L0TXCFGPM, L0TXCFGPMTYPE, L0TXTLFCCMPLMCCRED, L0TXTLFCCMPLMCUPDATE, L0TXTLFCNPOSTBYPCRED, L0TXTLFCNPOSTBYPUPDATE, L0TXTLFCPOSTORDCRED, L0TXTLFCPOSTORDUPDATE, L0TXTLSBFCDATA, L0TXTLSBFCUPDATE, L0TXTLTLPDATA, L0TXTLTLPEDB, L0TXTLTLPENABLE, L0TXTLTLPEND, L0TXTLTLPLATENCY, L0TXTLTLPREQ, L0TXTLTLPREQEND, L0TXTLTLPWIDTH, L0UPSTREAMRXPORTINL0S, L0VC0PREVIEWEXPAND, L0WAKEN, LLKRXCHFIFO, LLKRXCHTC, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTX4DWHEADERN, LLKTXCHFIFO, LLKTXCHTC, LLKTXCOMPLETEN, LLKTXCREATEECRCN, LLKTXDATA, LLKTXENABLEN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MAINPOWER, MGMTADDR, MGMTBWREN, MGMTRDEN, MGMTSTATSCREDITSEL, MGMTWDATA, MGMTWREN, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7);
12880 
parameter AERCAPABILITYECRCCHECKCAPABLE = "FALSE";
12881 
parameter AERCAPABILITYECRCGENCAPABLE = "FALSE";
12882 
parameter BAR0EXIST = "TRUE";
12883 
parameter BAR0PREFETCHABLE = "TRUE";
12884 
parameter BAR1EXIST = "FALSE";
12885 
parameter BAR1PREFETCHABLE = "FALSE";
12886 
parameter BAR2EXIST = "FALSE";
12887 
parameter BAR2PREFETCHABLE = "FALSE";
12888 
parameter BAR3EXIST = "FALSE";
12889 
parameter BAR3PREFETCHABLE = "FALSE";
12890 
parameter BAR4EXIST = "FALSE";
12891 
parameter BAR4PREFETCHABLE = "FALSE";
12892 
parameter BAR5EXIST = "FALSE";
12893 
parameter BAR5PREFETCHABLE = "FALSE";
12894 
parameter CLKDIVIDED = "FALSE";
12895 
parameter DUALCOREENABLE = "FALSE";
12896 
parameter DUALCORESLAVE = "FALSE";
12897 
parameter INFINITECOMPLETIONS = "TRUE";
12898 
parameter ISSWITCH = "FALSE";
12899 
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE";
12900 
parameter LLKBYPASS = "FALSE";
12901 
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
12902 
parameter PCIECAPABILITYSLOTIMPL = "FALSE";
12903 
parameter PMCAPABILITYD1SUPPORT = "FALSE";
12904 
parameter PMCAPABILITYD2SUPPORT = "FALSE";
12905 
parameter PMCAPABILITYDSI = "TRUE";
12906 
parameter RAMSHARETXRX = "FALSE";
12907 
parameter RESETMODE = "FALSE";
12908 
parameter RETRYREADADDRPIPE = "FALSE";
12909 
parameter RETRYREADDATAPIPE = "FALSE";
12910 
parameter RETRYWRITEPIPE = "FALSE";
12911 
parameter RXREADADDRPIPE = "FALSE";
12912 
parameter RXREADDATAPIPE = "FALSE";
12913 
parameter RXWRITEPIPE = "FALSE";
12914 
parameter SELECTASMODE = "FALSE";
12915 
parameter SELECTDLLIF = "FALSE";
12916 
parameter SLOTCAPABILITYATTBUTTONPRESENT = "FALSE";
12917 
parameter SLOTCAPABILITYATTINDICATORPRESENT = "FALSE";
12918 
parameter SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE";
12919 
parameter SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE";
12920 
parameter SLOTCAPABILITYMSLSENSORPRESENT = "FALSE";
12921 
parameter SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE";
12922 
parameter SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE";
12923 
parameter SLOTIMPLEMENTED = "FALSE";
12924 
parameter TXREADADDRPIPE = "FALSE";
12925 
parameter TXREADDATAPIPE = "FALSE";
12926 
parameter TXWRITEPIPE = "FALSE";
12927 
parameter UPSTREAMFACING = "TRUE";
12928 
parameter XLINKSUPPORTED = "FALSE";
12929 
parameter [10:0] VC0TOTALCREDITSCD = 11'h0;
12930 
parameter [10:0] VC0TOTALCREDITSPD = 11'h34;
12931 
parameter [10:0] VC1TOTALCREDITSCD = 11'h0;
12932 
parameter [10:0] VC1TOTALCREDITSPD = 11'h0;
12933 
parameter [11:0] AERBASEPTR = 12'h110;
12934 
parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138;
12935 
parameter [11:0] DSNBASEPTR = 12'h148;
12936 
parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154;
12937 
parameter [11:0] EXTCFGXPCAPPTR = 12'h0;
12938 
parameter [11:0] MSIBASEPTR = 12'h48;
12939 
parameter [11:0] PBBASEPTR = 12'h138;
12940 
parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148;
12941 
parameter [11:0] PMBASEPTR = 12'h40;
12942 
parameter [11:0] RETRYRAMSIZE = 12'h9;
12943 
parameter [11:0] VCBASEPTR = 12'h154;
12944 
parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0;
12945 
parameter [12:0] SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0;
12946 
parameter [12:0] VC0RXFIFOBASEC = 13'h98;
12947 
parameter [12:0] VC0RXFIFOBASENP = 13'h80;
12948 
parameter [12:0] VC0RXFIFOBASEP = 13'h0;
12949 
parameter [12:0] VC0RXFIFOLIMITC = 13'h117;
12950 
parameter [12:0] VC0RXFIFOLIMITNP = 13'h97;
12951 
parameter [12:0] VC0RXFIFOLIMITP = 13'h7f;
12952 
parameter [12:0] VC0TXFIFOBASEC = 13'h98;
12953 
parameter [12:0] VC0TXFIFOBASENP = 13'h80;
12954 
parameter [12:0] VC0TXFIFOBASEP = 13'h0;
12955 
parameter [12:0] VC0TXFIFOLIMITC = 13'h117;
12956 
parameter [12:0] VC0TXFIFOLIMITNP = 13'h97;
12957 
parameter [12:0] VC0TXFIFOLIMITP = 13'h7f;
12958 
parameter [12:0] VC1RXFIFOBASEC = 13'h118;
12959 
parameter [12:0] VC1RXFIFOBASENP = 13'h118;
12960 
parameter [12:0] VC1RXFIFOBASEP = 13'h118;
12961 
parameter [12:0] VC1RXFIFOLIMITC = 13'h118;
12962 
parameter [12:0] VC1RXFIFOLIMITNP = 13'h118;
12963 
parameter [12:0] VC1RXFIFOLIMITP = 13'h118;
12964 
parameter [12:0] VC1TXFIFOBASEC = 13'h118;
12965 
parameter [12:0] VC1TXFIFOBASENP = 13'h118;
12966 
parameter [12:0] VC1TXFIFOBASEP = 13'h118;
12967 
parameter [12:0] VC1TXFIFOLIMITC = 13'h118;
12968 
parameter [12:0] VC1TXFIFOLIMITNP = 13'h118;
12969 
parameter [12:0] VC1TXFIFOLIMITP = 13'h118;
12970 
parameter [15:0] DEVICEID = 16'h5050;
12971 
parameter [15:0] SUBSYSTEMID = 16'h5050;
12972 
parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE;
12973 
parameter [15:0] VENDORID = 16'h10EE;
12974 
parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1;
12975 
parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0;
12976 
parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0;
12977 
parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0;
12978 
parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0;
12979 
parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0;
12980 
parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0;
12981 
parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0;
12982 
parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0;
12983 
parameter [1:0] PMSTATUSCONTROLDATASCALE = 2'h0;
12984 
parameter [1:0] SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'h0;
12985 
parameter [23:0] CLASSCODE = 24'h058000;
12986 
parameter [2:0] CONFIGROUTING = 3'h1;
12987 
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0;
12988 
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0;
12989 
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0;
12990 
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0;
12991 
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0;
12992 
parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0;
12993 
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0;
12994 
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0;
12995 
parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0;
12996 
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0;
12997 
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0;
12998 
parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0;
12999 
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0;
13000 
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0;
13001 
parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0;
13002 
parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0;
13003 
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0;
13004 
parameter [31:0] CARDBUSCISPOINTER = 32'h0;
13005 
parameter [3:0] XPDEVICEPORTTYPE = 4'h0;
13006 
parameter [4:0] PCIECAPABILITYINTMSGNUM = 5'h0;
13007 
parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0;
13008 
parameter [5:0] BAR0MASKWIDTH = 6'h14;
13009 
parameter [5:0] BAR1MASKWIDTH = 6'h0;
13010 
parameter [5:0] BAR2MASKWIDTH = 6'h0;
13011 
parameter [5:0] BAR3MASKWIDTH = 6'h0;
13012 
parameter [5:0] BAR4MASKWIDTH = 6'h0;
13013 
parameter [5:0] BAR5MASKWIDTH = 6'h0;
13014 
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01;
13015 
parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35;
13016 
parameter [6:0] VC0TOTALCREDITSCH = 7'h0;
13017 
parameter [6:0] VC0TOTALCREDITSNPH = 7'h08;
13018 
parameter [6:0] VC0TOTALCREDITSPH = 7'h08;
13019 
parameter [6:0] VC1TOTALCREDITSCH = 7'h0;
13020 
parameter [6:0] VC1TOTALCREDITSNPH = 7'h0;
13021 
parameter [6:0] VC1TOTALCREDITSPH = 7'h0;
13022 
parameter [7:0] ACTIVELANESIN = 8'h1;
13023 
parameter [7:0] CAPABILITIESPOINTER = 8'h40;
13024 
parameter [7:0] EXTCFGCAPPTR = 8'h0;
13025 
parameter [7:0] HEADERTYPE = 8'h0;
13026 
parameter [7:0] INTERRUPTPIN = 8'h0;
13027 
parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60;
13028 
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0;
13029 
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0;
13030 
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0;
13031 
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0;
13032 
parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0;
13033 
parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60;
13034 
parameter [7:0] PMDATA0 = 8'h0;
13035 
parameter [7:0] PMDATA1 = 8'h0;
13036 
parameter [7:0] PMDATA2 = 8'h0;
13037 
parameter [7:0] PMDATA3 = 8'h0;
13038 
parameter [7:0] PMDATA4 = 8'h0;
13039 
parameter [7:0] PMDATA5 = 8'h0;
13040 
parameter [7:0] PMDATA6 = 8'h0;
13041 
parameter [7:0] PMDATA7 = 8'h0;
13042 
parameter [7:0] PMDATA8 = 8'h0;
13043 
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0;
13044 
parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0;
13045 
parameter [7:0] REVISIONID = 8'h0;
13046 
parameter [7:0] SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h0;
13047 
parameter [7:0] XPBASEPTR = 8'h60;
13048 
parameter integer BAR0ADDRWIDTH = 0;
13049 
parameter integer BAR0IOMEMN = 0;
13050 
parameter integer BAR1ADDRWIDTH = 0;
13051 
parameter integer BAR1IOMEMN = 0;
13052 
parameter integer BAR2ADDRWIDTH = 0;
13053 
parameter integer BAR2IOMEMN = 0;
13054 
parameter integer BAR3ADDRWIDTH = 0;
13055 
parameter integer BAR3IOMEMN = 0;
13056 
parameter integer BAR4ADDRWIDTH = 0;
13057 
parameter integer BAR4IOMEMN = 0;
13058 
parameter integer BAR5IOMEMN = 0;
13059 
parameter integer DUALROLECFGCNTRLROOTEPN = 0;
13060 
parameter integer L0SEXITLATENCY = 7;
13061 
parameter integer L0SEXITLATENCYCOMCLK = 7;
13062 
parameter integer L1EXITLATENCY = 7;
13063 
parameter integer L1EXITLATENCYCOMCLK = 7;
13064 
parameter integer LOWPRIORITYVCCOUNT = 0;
13065 
parameter integer PCIEREVISION = 1;
13066 
parameter integer PMDATASCALE0 = 0;
13067 
parameter integer PMDATASCALE1 = 0;
13068 
parameter integer PMDATASCALE2 = 0;
13069 
parameter integer PMDATASCALE3 = 0;
13070 
parameter integer PMDATASCALE4 = 0;
13071 
parameter integer PMDATASCALE5 = 0;
13072 
parameter integer PMDATASCALE6 = 0;
13073 
parameter integer PMDATASCALE7 = 0;
13074 
parameter integer PMDATASCALE8 = 0;
13075 
parameter integer RETRYRAMREADLATENCY = 3;
13076 
parameter integer RETRYRAMWIDTH = 0;
13077 
parameter integer RETRYRAMWRITELATENCY = 1;
13078 
parameter integer TLRAMREADLATENCY = 3;
13079 
parameter integer TLRAMWIDTH = 0;
13080 
parameter integer TLRAMWRITELATENCY = 1;
13081 
parameter integer TXTSNFTS = 255;
13082 
parameter integer TXTSNFTSCOMCLK = 255;
13083 
parameter integer XPMAXPAYLOAD = 0;
13084 
parameter integer XPRCBCONTROL = 0;
13085 
output BUSMASTERENABLE;
13086 
output CRMDOHOTRESETN;
13087 
output CRMPWRSOFTRESETN;
13088 
output CRMRXHOTRESETN;
13089 
output DLLTXPMDLLPOUTSTANDING;
13090 
output INTERRUPTDISABLE;
13091 
output IOSPACEENABLE;
13092 
output L0ASAUTONOMOUSINITCOMPLETED;
13093 
output [1:0] L0ATTENTIONINDICATORCONTROL;
13094 
output L0CFGLOOPBACKACK;
13095 
output [12:0] L0COMPLETERID;
13096 
output L0CORRERRMSGRCVD;
13097 
output [1:0] L0DLLASRXSTATE;
13098 
output L0DLLASTXSTATE;
13099 
output [6:0] L0DLLERRORVECTOR;
13100 
output L0DLLRXACKOUTSTANDING;
13101 
output L0DLLTXNONFCOUTSTANDING;
13102 
output L0DLLTXOUTSTANDING;
13103 
output [7:0] L0DLLVCSTATUS;
13104 
output [7:0] L0DLUPDOWN;
13105 
output [15:0] L0ERRMSGREQID;
13106 
output L0FATALERRMSGRCVD;
13107 
output L0FIRSTCFGWRITEOCCURRED;
13108 
output L0FWDCORRERROUT;
13109 
output L0FWDFATALERROUT;
13110 
output L0FWDNONFATALERROUT;
13111 
output [3:0] L0LTSSMSTATE;
13112 
output L0MACENTEREDL0;
13113 
output L0MACLINKTRAINING;
13114 
output L0MACLINKUP;
13115 
output [3:0] L0MACNEGOTIATEDLINKWIDTH;
13116 
output L0MACNEWSTATEACK;
13117 
output L0MACRXL0SSTATE;
13118 
output L0MACUPSTREAMDOWNSTREAM;
13119 
output [2:0] L0MCFOUND;
13120 
output L0MSIENABLE0;
13121 
output [2:0] L0MULTIMSGEN0;
13122 
output L0NONFATALERRMSGRCVD;
13123 
output L0PMEACK;
13124 
output L0PMEEN;
13125 
output L0PMEREQOUT;
13126 
output L0POWERCONTROLLERCONTROL;
13127 
output [1:0] L0POWERINDICATORCONTROL;
13128 
output L0PWRINHIBITTRANSFERS;
13129 
output L0PWRL1STATE;
13130 
output L0PWRL23READYDEVICE;
13131 
output L0PWRL23READYSTATE;
13132 
output [1:0] L0PWRSTATE0;
13133 
output L0PWRTURNOFFREQ;
13134 
output L0PWRTXL0SSTATE;
13135 
output L0RECEIVEDASSERTINTALEGACYINT;
13136 
output L0RECEIVEDASSERTINTBLEGACYINT;
13137 
output L0RECEIVEDASSERTINTCLEGACYINT;
13138 
output L0RECEIVEDASSERTINTDLEGACYINT;
13139 
output L0RECEIVEDDEASSERTINTALEGACYINT;
13140 
output L0RECEIVEDDEASSERTINTBLEGACYINT;
13141 
output L0RECEIVEDDEASSERTINTCLEGACYINT;
13142 
output L0RECEIVEDDEASSERTINTDLEGACYINT;
13143 
output L0RXBEACON;
13144 
output [23:0] L0RXDLLFCCMPLMCCRED;
13145 
output [7:0] L0RXDLLFCCMPLMCUPDATE;
13146 
output [19:0] L0RXDLLFCNPOSTBYPCRED;
13147 
output [7:0] L0RXDLLFCNPOSTBYPUPDATE;
13148 
output [23:0] L0RXDLLFCPOSTORDCRED;
13149 
output [7:0] L0RXDLLFCPOSTORDUPDATE;
13150 
output L0RXDLLPM;
13151 
output [2:0] L0RXDLLPMTYPE;
13152 
output [18:0] L0RXDLLSBFCDATA;
13153 
output L0RXDLLSBFCUPDATE;
13154 
output L0RXDLLTLPECRCOK;
13155 
output [1:0] L0RXDLLTLPEND;
13156 
output [1:0] L0RXMACLINKERROR;
13157 
output L0STATSCFGOTHERRECEIVED;
13158 
output L0STATSCFGOTHERTRANSMITTED;
13159 
output L0STATSCFGRECEIVED;
13160 
output L0STATSCFGTRANSMITTED;
13161 
output L0STATSDLLPRECEIVED;
13162 
output L0STATSDLLPTRANSMITTED;
13163 
output L0STATSOSRECEIVED;
13164 
output L0STATSOSTRANSMITTED;
13165 
output L0STATSTLPRECEIVED;
13166 
output L0STATSTLPTRANSMITTED;
13167 
output L0TOGGLEELECTROMECHANICALINTERLOCK;
13168 
output [2:0] L0TRANSFORMEDVC;
13169 
output [7:0] L0TXDLLFCCMPLMCUPDATED;
13170 
output [7:0] L0TXDLLFCNPOSTBYPUPDATED;
13171 
output [7:0] L0TXDLLFCPOSTORDUPDATED;
13172 
output L0TXDLLPMUPDATED;
13173 
output L0TXDLLSBFCUPDATED;
13174 
output [3:0] L0UCBYPFOUND;
13175 
output [3:0] L0UCORDFOUND;
13176 
output L0UNLOCKRECEIVED;
13177 
output LLKRX4DWHEADERN;
13178 
output [7:0] LLKRXCHCOMPLETIONAVAILABLEN;
13179 
output [7:0] LLKRXCHCOMPLETIONPARTIALN;
13180 
output LLKRXCHCONFIGAVAILABLEN;
13181 
output LLKRXCHCONFIGPARTIALN;
13182 
output [7:0] LLKRXCHNONPOSTEDAVAILABLEN;
13183 
output [7:0] LLKRXCHNONPOSTEDPARTIALN;
13184 
output [7:0] LLKRXCHPOSTEDAVAILABLEN;
13185 
output [7:0] LLKRXCHPOSTEDPARTIALN;
13186 
output [63:0] LLKRXDATA;
13187 
output LLKRXECRCBADN;
13188 
output LLKRXEOFN;
13189 
output LLKRXEOPN;
13190 
output [15:0] LLKRXPREFERREDTYPE;
13191 
output LLKRXSOFN;
13192 
output LLKRXSOPN;
13193 
output LLKRXSRCDSCN;
13194 
output LLKRXSRCLASTREQN;
13195 
output LLKRXSRCRDYN;
13196 
output [1:0] LLKRXVALIDN;
13197 
output [7:0] LLKTCSTATUS;
13198 
output [9:0] LLKTXCHANSPACE;
13199 
output [7:0] LLKTXCHCOMPLETIONREADYN;
13200 
output [7:0] LLKTXCHNONPOSTEDREADYN;
13201 
output [7:0] LLKTXCHPOSTEDREADYN;
13202 
output LLKTXCONFIGREADYN;
13203 
output LLKTXDSTRDYN;
13204 
output [2:0] MAXPAYLOADSIZE;
13205 
output [2:0] MAXREADREQUESTSIZE;
13206 
output MEMSPACEENABLE;
13207 
output [16:0] MGMTPSO;
13208 
output [31:0] MGMTRDATA;
13209 
output [11:0] MGMTSTATSCREDIT;
13210 
output [11:0] MIMDLLBRADD;
13211 
output MIMDLLBREN;
13212 
output [11:0] MIMDLLBWADD;
13213 
output [63:0] MIMDLLBWDATA;
13214 
output MIMDLLBWEN;
13215 
output [12:0] MIMRXBRADD;
13216 
output MIMRXBREN;
13217 
output [12:0] MIMRXBWADD;
13218 
output [63:0] MIMRXBWDATA;
13219 
output MIMRXBWEN;
13220 
output [12:0] MIMTXBRADD;
13221 
output MIMTXBREN;
13222 
output [12:0] MIMTXBWADD;
13223 
output [63:0] MIMTXBWDATA;
13224 
output MIMTXBWEN;
13225 
output PARITYERRORRESPONSE;
13226 
output PIPEDESKEWLANESL0;
13227 
output PIPEDESKEWLANESL1;
13228 
output PIPEDESKEWLANESL2;
13229 
output PIPEDESKEWLANESL3;
13230 
output PIPEDESKEWLANESL4;
13231 
output PIPEDESKEWLANESL5;
13232 
output PIPEDESKEWLANESL6;
13233 
output PIPEDESKEWLANESL7;
13234 
output [1:0] PIPEPOWERDOWNL0;
13235 
output [1:0] PIPEPOWERDOWNL1;
13236 
output [1:0] PIPEPOWERDOWNL2;
13237 
output [1:0] PIPEPOWERDOWNL3;
13238 
output [1:0] PIPEPOWERDOWNL4;
13239 
output [1:0] PIPEPOWERDOWNL5;
13240 
output [1:0] PIPEPOWERDOWNL6;
13241 
output [1:0] PIPEPOWERDOWNL7;
13242 
output PIPERESETL0;
13243 
output PIPERESETL1;
13244 
output PIPERESETL2;
13245 
output PIPERESETL3;
13246 
output PIPERESETL4;
13247 
output PIPERESETL5;
13248 
output PIPERESETL6;
13249 
output PIPERESETL7;
13250 
output PIPERXPOLARITYL0;
13251 
output PIPERXPOLARITYL1;
13252 
output PIPERXPOLARITYL2;
13253 
output PIPERXPOLARITYL3;
13254 
output PIPERXPOLARITYL4;
13255 
output PIPERXPOLARITYL5;
13256 
output PIPERXPOLARITYL6;
13257 
output PIPERXPOLARITYL7;
13258 
output PIPETXCOMPLIANCEL0;
13259 
output PIPETXCOMPLIANCEL1;
13260 
output PIPETXCOMPLIANCEL2;
13261 
output PIPETXCOMPLIANCEL3;
13262 
output PIPETXCOMPLIANCEL4;
13263 
output PIPETXCOMPLIANCEL5;
13264 
output PIPETXCOMPLIANCEL6;
13265 
output PIPETXCOMPLIANCEL7;
13266 
output PIPETXDATAKL0;
13267 
output PIPETXDATAKL1;
13268 
output PIPETXDATAKL2;
13269 
output PIPETXDATAKL3;
13270 
output PIPETXDATAKL4;
13271 
output PIPETXDATAKL5;
13272 
output PIPETXDATAKL6;
13273 
output PIPETXDATAKL7;
13274 
output [7:0] PIPETXDATAL0;
13275 
output [7:0] PIPETXDATAL1;
13276 
output [7:0] PIPETXDATAL2;
13277 
output [7:0] PIPETXDATAL3;
13278 
output [7:0] PIPETXDATAL4;
13279 
output [7:0] PIPETXDATAL5;
13280 
output [7:0] PIPETXDATAL6;
13281 
output [7:0] PIPETXDATAL7;
13282 
output PIPETXDETECTRXLOOPBACKL0;
13283 
output PIPETXDETECTRXLOOPBACKL1;
13284 
output PIPETXDETECTRXLOOPBACKL2;
13285 
output PIPETXDETECTRXLOOPBACKL3;
13286 
output PIPETXDETECTRXLOOPBACKL4;
13287 
output PIPETXDETECTRXLOOPBACKL5;
13288 
output PIPETXDETECTRXLOOPBACKL6;
13289 
output PIPETXDETECTRXLOOPBACKL7;
13290 
output PIPETXELECIDLEL0;
13291 
output PIPETXELECIDLEL1;
13292 
output PIPETXELECIDLEL2;
13293 
output PIPETXELECIDLEL3;
13294 
output PIPETXELECIDLEL4;
13295 
output PIPETXELECIDLEL5;
13296 
output PIPETXELECIDLEL6;
13297 
output PIPETXELECIDLEL7;
13298 
output SERRENABLE;
13299 
output URREPORTINGENABLE;
13300 
input AUXPOWER;
13301 
input [5:0] CFGNEGOTIATEDLINKWIDTH;
13302 
input COMPLIANCEAVOID;
13303 
input CRMCFGBRIDGEHOTRESET;
13304 
input CRMCORECLK;
13305 
input CRMCORECLKDLO;
13306 
input CRMCORECLKRXO;
13307 
input CRMCORECLKTXO;
13308 
input CRMLINKRSTN;
13309 
input CRMMACRSTN;
13310 
input CRMMGMTRSTN;
13311 
input CRMNVRSTN;
13312 
input CRMTXHOTRESETN;
13313 
input CRMURSTN;
13314 
input CRMUSERCFGRSTN;
13315 
input CRMUSERCLK;
13316 
input CRMUSERCLKRXO;
13317 
input CRMUSERCLKTXO;
13318 
input CROSSLINKSEED;
13319 
input [11:0] L0ACKNAKTIMERADJUSTMENT;
13320 
input L0ALLDOWNPORTSINL1;
13321 
input L0ALLDOWNRXPORTSINL0S;
13322 
input L0ASE;
13323 
input [7:0] L0ASPORTCOUNT;
13324 
input [2:0] L0ASTURNPOOLBITSCONSUMED;
13325 
input L0ATTENTIONBUTTONPRESSED;
13326 
input L0CFGASSPANTREEOWNEDSTATE;
13327 
input [3:0] L0CFGASSTATECHANGECMD;
13328 
input L0CFGDISABLESCRAMBLE;
13329 
input L0CFGEXTENDEDSYNC;
13330 
input L0CFGL0SENTRYENABLE;
13331 
input L0CFGL0SENTRYSUP;
13332 
input [2:0] L0CFGL0SEXITLAT;
13333 
input L0CFGLINKDISABLE;
13334 
input L0CFGLOOPBACKMASTER;
13335 
input [2:0] L0CFGNEGOTIATEDMAXP;
13336 
input [7:0] L0CFGVCENABLE;
13337 
input [23:0] L0CFGVCID;
13338 
input L0DLLHOLDLINKUP;
13339 
input L0ELECTROMECHANICALINTERLOCKENGAGED;
13340 
input L0FWDASSERTINTALEGACYINT;
13341 
input L0FWDASSERTINTBLEGACYINT;
13342 
input L0FWDASSERTINTCLEGACYINT;
13343 
input L0FWDASSERTINTDLEGACYINT;
13344 
input L0FWDCORRERRIN;
13345 
input L0FWDDEASSERTINTALEGACYINT;
13346 
input L0FWDDEASSERTINTBLEGACYINT;
13347 
input L0FWDDEASSERTINTCLEGACYINT;
13348 
input L0FWDDEASSERTINTDLEGACYINT;
13349 
input L0FWDFATALERRIN;
13350 
input L0FWDNONFATALERRIN;
13351 
input L0LEGACYINTFUNCT0;
13352 
input L0MRLSENSORCLOSEDN;
13353 
input [3:0] L0MSIREQUEST0;
13354 
input [127:0] L0PACKETHEADERFROMUSER;
13355 
input L0PMEREQIN;
13356 
input [7:0] L0PORTNUMBER;
13357 
input L0POWERFAULTDETECTED;
13358 
input L0PRESENCEDETECTSLOTEMPTYN;
13359 
input L0PWRNEWSTATEREQ;
13360 
input [1:0] L0PWRNEXTLINKSTATE;
13361 
input [11:0] L0REPLAYTIMERADJUSTMENT;
13362 
input L0ROOTTURNOFFREQ;
13363 
input [7:0] L0RXTLTLPNONINITIALIZEDVC;
13364 
input L0SENDUNLOCKMESSAGE;
13365 
input L0SETCOMPLETERABORTERROR;
13366 
input L0SETCOMPLETIONTIMEOUTCORRERROR;
13367 
input L0SETCOMPLETIONTIMEOUTUNCORRERROR;
13368 
input L0SETDETECTEDCORRERROR;
13369 
input L0SETDETECTEDFATALERROR;
13370 
input L0SETDETECTEDNONFATALERROR;
13371 
input L0SETLINKDETECTEDPARITYERROR;
13372 
input L0SETLINKMASTERDATAPARITY;
13373 
input L0SETLINKRECEIVEDMASTERABORT;
13374 
input L0SETLINKRECEIVEDTARGETABORT;
13375 
input L0SETLINKSIGNALLEDTARGETABORT;
13376 
input L0SETLINKSYSTEMERROR;
13377 
input L0SETUNEXPECTEDCOMPLETIONCORRERROR;
13378 
input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR;
13379 
input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR;
13380 
input L0SETUNSUPPORTEDREQUESTOTHERERROR;
13381 
input L0SETUSERDETECTEDPARITYERROR;
13382 
input L0SETUSERMASTERDATAPARITY;
13383 
input L0SETUSERRECEIVEDMASTERABORT;
13384 
input L0SETUSERRECEIVEDTARGETABORT;
13385 
input L0SETUSERSIGNALLEDTARGETABORT;
13386 
input L0SETUSERSYSTEMERROR;
13387 
input L0TLASFCCREDSTARVATION;
13388 
input L0TLLINKRETRAIN;
13389 
input L0TRANSACTIONSPENDING;
13390 
input L0TXBEACON;
13391 
input L0TXCFGPM;
13392 
input [2:0] L0TXCFGPMTYPE;
13393 
input [159:0] L0TXTLFCCMPLMCCRED;
13394 
input [15:0] L0TXTLFCCMPLMCUPDATE;
13395 
input [191:0] L0TXTLFCNPOSTBYPCRED;
13396 
input [15:0] L0TXTLFCNPOSTBYPUPDATE;
13397 
input [159:0] L0TXTLFCPOSTORDCRED;
13398 
input [15:0] L0TXTLFCPOSTORDUPDATE;
13399 
input [18:0] L0TXTLSBFCDATA;
13400 
input L0TXTLSBFCUPDATE;
13401 
input [63:0] L0TXTLTLPDATA;
13402 
input L0TXTLTLPEDB;
13403 
input [1:0] L0TXTLTLPENABLE;
13404 
input [1:0] L0TXTLTLPEND;
13405 
input [3:0] L0TXTLTLPLATENCY;
13406 
input L0TXTLTLPREQ;
13407 
input L0TXTLTLPREQEND;
13408 
input L0TXTLTLPWIDTH;
13409 
input L0UPSTREAMRXPORTINL0S;
13410 
input L0VC0PREVIEWEXPAND;
13411 
input L0WAKEN;
13412 
input [1:0] LLKRXCHFIFO;
13413 
input [2:0] LLKRXCHTC;
13414 
input LLKRXDSTCONTREQN;
13415 
input LLKRXDSTREQN;
13416 
input LLKTX4DWHEADERN;
13417 
input [1:0] LLKTXCHFIFO;
13418 
input [2:0] LLKTXCHTC;
13419 
input LLKTXCOMPLETEN;
13420 
input LLKTXCREATEECRCN;
13421 
input [63:0] LLKTXDATA;
13422 
input [1:0] LLKTXENABLEN;
13423 
input LLKTXEOFN;
13424 
input LLKTXEOPN;
13425 
input LLKTXSOFN;
13426 
input LLKTXSOPN;
13427 
input LLKTXSRCDSCN;
13428 
input LLKTXSRCRDYN;
13429 
input MAINPOWER;
13430 
input [10:0] MGMTADDR;
13431 
input [3:0] MGMTBWREN;
13432 
input MGMTRDEN;
13433 
input [6:0] MGMTSTATSCREDITSEL;
13434 
input [31:0] MGMTWDATA;
13435 
input MGMTWREN;
13436 
input [63:0] MIMDLLBRDATA;
13437 
input [63:0] MIMRXBRDATA;
13438 
input [63:0] MIMTXBRDATA;
13439 
input PIPEPHYSTATUSL0;
13440 
input PIPEPHYSTATUSL1;
13441 
input PIPEPHYSTATUSL2;
13442 
input PIPEPHYSTATUSL3;
13443 
input PIPEPHYSTATUSL4;
13444 
input PIPEPHYSTATUSL5;
13445 
input PIPEPHYSTATUSL6;
13446 
input PIPEPHYSTATUSL7;
13447 
input PIPERXCHANISALIGNEDL0;
13448 
input PIPERXCHANISALIGNEDL1;
13449 
input PIPERXCHANISALIGNEDL2;
13450 
input PIPERXCHANISALIGNEDL3;
13451 
input PIPERXCHANISALIGNEDL4;
13452 
input PIPERXCHANISALIGNEDL5;
13453 
input PIPERXCHANISALIGNEDL6;
13454 
input PIPERXCHANISALIGNEDL7;
13455 
input PIPERXDATAKL0;
13456 
input PIPERXDATAKL1;
13457 
input PIPERXDATAKL2;
13458 
input PIPERXDATAKL3;
13459 
input PIPERXDATAKL4;
13460 
input PIPERXDATAKL5;
13461 
input PIPERXDATAKL6;
13462 
input PIPERXDATAKL7;
13463 
input [7:0] PIPERXDATAL0;
13464 
input [7:0] PIPERXDATAL1;
13465 
input [7:0] PIPERXDATAL2;
13466 
input [7:0] PIPERXDATAL3;
13467 
input [7:0] PIPERXDATAL4;
13468 
input [7:0] PIPERXDATAL5;
13469 
input [7:0] PIPERXDATAL6;
13470 
input [7:0] PIPERXDATAL7;
13471 
input PIPERXELECIDLEL0;
13472 
input PIPERXELECIDLEL1;
13473 
input PIPERXELECIDLEL2;
13474 
input PIPERXELECIDLEL3;
13475 
input PIPERXELECIDLEL4;
13476 
input PIPERXELECIDLEL5;
13477 
input PIPERXELECIDLEL6;
13478 
input PIPERXELECIDLEL7;
13479 
input [2:0] PIPERXSTATUSL0;
13480 
input [2:0] PIPERXSTATUSL1;
13481 
input [2:0] PIPERXSTATUSL2;
13482 
input [2:0] PIPERXSTATUSL3;
13483 
input [2:0] PIPERXSTATUSL4;
13484 
input [2:0] PIPERXSTATUSL5;
13485 
input [2:0] PIPERXSTATUSL6;
13486 
input [2:0] PIPERXSTATUSL7;
13487 
input PIPERXVALIDL0;
13488 
input PIPERXVALIDL1;
13489 
input PIPERXVALIDL2;
13490 
input PIPERXVALIDL3;
13491 
input PIPERXVALIDL4;
13492 
input PIPERXVALIDL5;
13493 
input PIPERXVALIDL6;
13494 
input PIPERXVALIDL7;
13495 
endmodule
13496 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13497 
module PLL_ADV (CLKFBDCM, CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUTDCM0, CLKOUTDCM1, CLKOUTDCM2, CLKOUTDCM3, CLKOUTDCM4, CLKOUTDCM5, DO, DRDY, LOCKED, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, REL, RST);
13498 
parameter BANDWIDTH = "OPTIMIZED";
13499 
parameter CLKFBOUT_DESKEW_ADJUST = "NONE";
13500 
parameter CLKOUT0_DESKEW_ADJUST = "NONE";
13501 
parameter CLKOUT1_DESKEW_ADJUST = "NONE";
13502 
parameter CLKOUT2_DESKEW_ADJUST = "NONE";
13503 
parameter CLKOUT3_DESKEW_ADJUST = "NONE";
13504 
parameter CLKOUT4_DESKEW_ADJUST = "NONE";
13505 
parameter CLKOUT5_DESKEW_ADJUST = "NONE";
13506 
parameter integer CLKFBOUT_MULT = 1;
13507 
parameter real CLKFBOUT_PHASE = 0.0;
13508 
parameter real CLKIN1_PERIOD = 0.000;
13509 
parameter real CLKIN2_PERIOD = 0.000;
13510 
parameter integer CLKOUT0_DIVIDE = 1;
13511 
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
13512 
parameter real CLKOUT0_PHASE = 0.0;
13513 
parameter integer CLKOUT1_DIVIDE = 1;
13514 
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
13515 
parameter real CLKOUT1_PHASE = 0.0;
13516 
parameter integer CLKOUT2_DIVIDE = 1;
13517 
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
13518 
parameter real CLKOUT2_PHASE = 0.0;
13519 
parameter integer CLKOUT3_DIVIDE = 1;
13520 
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
13521 
parameter real CLKOUT3_PHASE = 0.0;
13522 
parameter integer CLKOUT4_DIVIDE = 1;
13523 
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
13524 
parameter real CLKOUT4_PHASE = 0.0;
13525 
parameter integer CLKOUT5_DIVIDE = 1;
13526 
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
13527 
parameter real CLKOUT5_PHASE = 0.0;
13528 
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
13529 
parameter integer DIVCLK_DIVIDE = 1;
13530 
parameter EN_REL = "FALSE";
13531 
parameter PLL_PMCD_MODE = "FALSE";
13532 
parameter real REF_JITTER = 0.100;
13533 
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
13534 
parameter RST_DEASSERT_CLK = "CLKIN1";
13535 
output CLKFBDCM;
13536 
output CLKFBOUT;
13537 
output CLKOUT0;
13538 
output CLKOUT1;
13539 
output CLKOUT2;
13540 
output CLKOUT3;
13541 
output CLKOUT4;
13542 
output CLKOUT5;
13543 
output CLKOUTDCM0;
13544 
output CLKOUTDCM1;
13545 
output CLKOUTDCM2;
13546 
output CLKOUTDCM3;
13547 
output CLKOUTDCM4;
13548 
output CLKOUTDCM5;
13549 
output [15:0] DO;
13550 
output DRDY;
13551 
output LOCKED;
13552 
input CLKFBIN;
13553 
input CLKIN1;
13554 
input CLKIN2;
13555 
input CLKINSEL;
13556 
input [4:0] DADDR;
13557 
input DCLK;
13558 
input DEN;
13559 
input [15:0] DI;
13560 
input DWE;
13561 
input REL;
13562 
input RST;
13563 
endmodule
13564 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13565 
module PLL_BASE (CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN, RST);
13566 
parameter BANDWIDTH = "OPTIMIZED";
13567 
parameter integer CLKFBOUT_MULT = 1;
13568 
parameter real CLKFBOUT_PHASE = 0.0;
13569 
parameter real CLKIN_PERIOD = 0.000;
13570 
parameter integer CLKOUT0_DIVIDE = 1;
13571 
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
13572 
parameter real CLKOUT0_PHASE = 0.0;
13573 
parameter integer CLKOUT1_DIVIDE = 1;
13574 
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
13575 
parameter real CLKOUT1_PHASE = 0.0;
13576 
parameter integer CLKOUT2_DIVIDE = 1;
13577 
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
13578 
parameter real CLKOUT2_PHASE = 0.0;
13579 
parameter integer CLKOUT3_DIVIDE = 1;
13580 
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
13581 
parameter real CLKOUT3_PHASE = 0.0;
13582 
parameter integer CLKOUT4_DIVIDE = 1;
13583 
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
13584 
parameter real CLKOUT4_PHASE = 0.0;
13585 
parameter integer CLKOUT5_DIVIDE = 1;
13586 
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
13587 
parameter real CLKOUT5_PHASE = 0.0;
13588 
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
13589 
parameter integer DIVCLK_DIVIDE = 1;
13590 
parameter real REF_JITTER = 0.100;
13591 
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
13592 
output CLKFBOUT;
13593 
output CLKOUT0;
13594 
output CLKOUT1;
13595 
output CLKOUT2;
13596 
output CLKOUT3;
13597 
output CLKOUT4;
13598 
output CLKOUT5;
13599 
output LOCKED;
13600 
input CLKFBIN;
13601 
input CLKIN;
13602 
input RST;
13603 
endmodule
13604 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13605 
module PMCD (CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST);
13606 
parameter EN_REL = "FALSE";
13607 
parameter RST_DEASSERT_CLK = "CLKA";
13608 
output CLKA1;
13609 
output CLKA1D2;
13610 
output CLKA1D4;
13611 
output CLKA1D8;
13612 
output CLKB1;
13613 
output CLKC1;
13614 
output CLKD1;
13615 
input CLKA;
13616 
input CLKB;
13617 
input CLKC;
13618 
input CLKD;
13619 
input REL;
13620 
input RST;
13621 
endmodule
13622 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13623 
module PPC405_ADV (APUFCMDECODED, APUFCMDECUDI, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRUCTION, APUFCMINSTRVALID, APUFCMLOADBYTEEN, APUFCMLOADDATA, APUFCMLOADDVALID, APUFCMOPERANDVALID, APUFCMRADATA, APUFCMRBDATA, APUFCMWRITEBACKOK, APUFCMXERCA, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGLOADDATAONAPUDBUS, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DBGWBIAR, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUABUS, C405PLBDCUBE, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUPRIORITY, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRDBUS, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUABUS, C405PLBICUCACHEABLE, C405PLBICUPRIORITY, C405PLBICUREQUEST, C405PLBICUSIZE, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, C405XXXMACHINECHECK, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLER, DCREMACREAD, DCREMACWRITE, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, DSOCMRDADDRVALID, DSOCMWRADDRVALID, EXTDCRABUS, EXTDCRDBUSOUT, EXTDCRREAD, EXTDCRWRITE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, ISOCMDCRBRAMEVENEN, ISOCMDCRBRAMODDEN, ISOCMDCRBRAMRDSELECT, BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, BRAMISOCMDCRRDDBUS, BRAMISOCMRDDBUS, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405SYNCBYPASS, CPMC405TIMERCLKEN, CPMC405TIMERTICK, CPMDCRCLK, CPMFCMCLK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DSARCVALUE, DSCNTLVALUE, DSOCMRWCOMPLETE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ, EMACDCRACK, EMACDCRDBUS, EXTDCRACK, EXTDCRDBUSIN, FCMAPUCR, FCMAPUDCDCREN, FCMAPUDCDFORCEALIGN, FCMAPUDCDFORCEBESTEERING, FCMAPUDCDFPUOP, FCMAPUDCDGPRWRITE, FCMAPUDCDLDSTBYTE, FCMAPUDCDLDSTDW, FCMAPUDCDLDSTHW, FCMAPUDCDLDSTQW, FCMAPUDCDLDSTWD, FCMAPUDCDLOAD, FCMAPUDCDPRIVOP, FCMAPUDCDRAEN, FCMAPUDCDRBEN, FCMAPUDCDSTORE, FCMAPUDCDTRAPBE, FCMAPUDCDTRAPLE, FCMAPUDCDUPDATE, FCMAPUDCDXERCAEN, FCMAPUDCDXEROVEN, FCMAPUDECODEBUSY, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUEXEBLOCKINGMCO, FCMAPUEXECRFIELD, FCMAPUEXENONBLOCKINGMCO, FCMAPUINSTRACK, FCMAPULOADWAIT, FCMAPURESULT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUXERCA, FCMAPUXEROV, ISARCVALUE, ISCNTLVALUE, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCURDDBUS, PLBC405DCURDWDADDR, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICURDDBUS, PLBC405ICURDWDADDR, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEAPUCONTROL, TIEAPUUDI1, TIEAPUUDI2, TIEAPUUDI3, TIEAPUUDI4, TIEAPUUDI5, TIEAPUUDI6, TIEAPUUDI7, TIEAPUUDI8, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEDCRADDR, TIEPVRBIT10, TIEPVRBIT11, TIEPVRBIT28, TIEPVRBIT29, TIEPVRBIT30, TIEPVRBIT31, TIEPVRBIT8, TIEPVRBIT9, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN);
13624 
output APUFCMDECODED;
13625 
output [0:2] APUFCMDECUDI;
13626 
output APUFCMDECUDIVALID;
13627 
output APUFCMENDIAN;
13628 
output APUFCMFLUSH;
13629 
output [0:31] APUFCMINSTRUCTION;
13630 
output APUFCMINSTRVALID;
13631 
output [0:3] APUFCMLOADBYTEEN;
13632 
output [0:31] APUFCMLOADDATA;
13633 
output APUFCMLOADDVALID;
13634 
output APUFCMOPERANDVALID;
13635 
output [0:31] APUFCMRADATA;
13636 
output [0:31] APUFCMRBDATA;
13637 
output APUFCMWRITEBACKOK;
13638 
output APUFCMXERCA;
13639 
output C405CPMCORESLEEPREQ;
13640 
output C405CPMMSRCE;
13641 
output C405CPMMSREE;
13642 
output C405CPMTIMERIRQ;
13643 
output C405CPMTIMERRESETREQ;
13644 
output C405DBGLOADDATAONAPUDBUS;
13645 
output C405DBGMSRWE;
13646 
output C405DBGSTOPACK;
13647 
output C405DBGWBCOMPLETE;
13648 
output C405DBGWBFULL;
13649 
output [0:29] C405DBGWBIAR;
13650 
output C405JTGCAPTUREDR;
13651 
output C405JTGEXTEST;
13652 
output C405JTGPGMOUT;
13653 
output C405JTGSHIFTDR;
13654 
output C405JTGTDO;
13655 
output C405JTGTDOEN;
13656 
output C405JTGUPDATEDR;
13657 
output C405PLBDCUABORT;
13658 
output [0:31] C405PLBDCUABUS;
13659 
output [0:7] C405PLBDCUBE;
13660 
output C405PLBDCUCACHEABLE;
13661 
output C405PLBDCUGUARDED;
13662 
output [0:1] C405PLBDCUPRIORITY;
13663 
output C405PLBDCUREQUEST;
13664 
output C405PLBDCURNW;
13665 
output C405PLBDCUSIZE2;
13666 
output C405PLBDCUU0ATTR;
13667 
output [0:63] C405PLBDCUWRDBUS;
13668 
output C405PLBDCUWRITETHRU;
13669 
output C405PLBICUABORT;
13670 
output [0:29] C405PLBICUABUS;
13671 
output C405PLBICUCACHEABLE;
13672 
output [0:1] C405PLBICUPRIORITY;
13673 
output C405PLBICUREQUEST;
13674 
output [2:3] C405PLBICUSIZE;
13675 
output C405PLBICUU0ATTR;
13676 
output C405RSTCHIPRESETREQ;
13677 
output C405RSTCORERESETREQ;
13678 
output C405RSTSYSRESETREQ;
13679 
output C405TRCCYCLE;
13680 
output [0:1] C405TRCEVENEXECUTIONSTATUS;
13681 
output [0:1] C405TRCODDEXECUTIONSTATUS;
13682 
output [0:3] C405TRCTRACESTATUS;
13683 
output C405TRCTRIGGEREVENTOUT;
13684 
output [0:10] C405TRCTRIGGEREVENTTYPE;
13685 
output C405XXXMACHINECHECK;
13686 
output [8:9] DCREMACABUS;
13687 
output DCREMACCLK;
13688 
output [0:31] DCREMACDBUS;
13689 
output DCREMACENABLER;
13690 
output DCREMACREAD;
13691 
output DCREMACWRITE;
13692 
output [8:29] DSOCMBRAMABUS;
13693 
output [0:3] DSOCMBRAMBYTEWRITE;
13694 
output DSOCMBRAMEN;
13695 
output [0:31] DSOCMBRAMWRDBUS;
13696 
output DSOCMBUSY;
13697 
output DSOCMRDADDRVALID;
13698 
output DSOCMWRADDRVALID;
13699 
output [0:9] EXTDCRABUS;
13700 
output [0:31] EXTDCRDBUSOUT;
13701 
output EXTDCRREAD;
13702 
output EXTDCRWRITE;
13703 
output ISOCMBRAMEN;
13704 
output ISOCMBRAMEVENWRITEEN;
13705 
output ISOCMBRAMODDWRITEEN;
13706 
output [8:28] ISOCMBRAMRDABUS;
13707 
output [8:28] ISOCMBRAMWRABUS;
13708 
output [0:31] ISOCMBRAMWRDBUS;
13709 
output ISOCMDCRBRAMEVENEN;
13710 
output ISOCMDCRBRAMODDEN;
13711 
output ISOCMDCRBRAMRDSELECT;
13712 
input BRAMDSOCMCLK;
13713 
input [0:31] BRAMDSOCMRDDBUS;
13714 
input BRAMISOCMCLK;
13715 
input [0:31] BRAMISOCMDCRRDDBUS;
13716 
input [0:63] BRAMISOCMRDDBUS;
13717 
input CPMC405CLOCK;
13718 
input CPMC405CORECLKINACTIVE;
13719 
input CPMC405CPUCLKEN;
13720 
input CPMC405JTAGCLKEN;
13721 
input CPMC405SYNCBYPASS;
13722 
input CPMC405TIMERCLKEN;
13723 
input CPMC405TIMERTICK;
13724 
input CPMDCRCLK;
13725 
input CPMFCMCLK;
13726 
input DBGC405DEBUGHALT;
13727 
input DBGC405EXTBUSHOLDACK;
13728 
input DBGC405UNCONDDEBUGEVENT;
13729 
input [0:7] DSARCVALUE;
13730 
input [0:7] DSCNTLVALUE;
13731 
input DSOCMRWCOMPLETE;
13732 
input EICC405CRITINPUTIRQ;
13733 
input EICC405EXTINPUTIRQ;
13734 
input EMACDCRACK;
13735 
input [0:31] EMACDCRDBUS;
13736 
input EXTDCRACK;
13737 
input [0:31] EXTDCRDBUSIN;
13738 
input [0:3] FCMAPUCR;
13739 
input FCMAPUDCDCREN;
13740 
input FCMAPUDCDFORCEALIGN;
13741 
input FCMAPUDCDFORCEBESTEERING;
13742 
input FCMAPUDCDFPUOP;
13743 
input FCMAPUDCDGPRWRITE;
13744 
input FCMAPUDCDLDSTBYTE;
13745 
input FCMAPUDCDLDSTDW;
13746 
input FCMAPUDCDLDSTHW;
13747 
input FCMAPUDCDLDSTQW;
13748 
input FCMAPUDCDLDSTWD;
13749 
input FCMAPUDCDLOAD;
13750 
input FCMAPUDCDPRIVOP;
13751 
input FCMAPUDCDRAEN;
13752 
input FCMAPUDCDRBEN;
13753 
input FCMAPUDCDSTORE;
13754 
input FCMAPUDCDTRAPBE;
13755 
input FCMAPUDCDTRAPLE;
13756 
input FCMAPUDCDUPDATE;
13757 
input FCMAPUDCDXERCAEN;
13758 
input FCMAPUDCDXEROVEN;
13759 
input FCMAPUDECODEBUSY;
13760 
input FCMAPUDONE;
13761 
input FCMAPUEXCEPTION;
13762 
input FCMAPUEXEBLOCKINGMCO;
13763 
input [0:2] FCMAPUEXECRFIELD;
13764 
input FCMAPUEXENONBLOCKINGMCO;
13765 
input FCMAPUINSTRACK;
13766 
input FCMAPULOADWAIT;
13767 
input [0:31] FCMAPURESULT;
13768 
input FCMAPURESULTVALID;
13769 
input FCMAPUSLEEPNOTREADY;
13770 
input FCMAPUXERCA;
13771 
input FCMAPUXEROV;
13772 
input [0:7] ISARCVALUE;
13773 
input [0:7] ISCNTLVALUE;
13774 
input JTGC405BNDSCANTDO;
13775 
input JTGC405TCK;
13776 
input JTGC405TDI;
13777 
input JTGC405TMS;
13778 
input JTGC405TRSTNEG;
13779 
input MCBCPUCLKEN;
13780 
input MCBJTAGEN;
13781 
input MCBTIMEREN;
13782 
input MCPPCRST;
13783 
input PLBC405DCUADDRACK;
13784 
input PLBC405DCUBUSY;
13785 
input PLBC405DCUERR;
13786 
input PLBC405DCURDDACK;
13787 
input [0:63] PLBC405DCURDDBUS;
13788 
input [1:3] PLBC405DCURDWDADDR;
13789 
input PLBC405DCUSSIZE1;
13790 
input PLBC405DCUWRDACK;
13791 
input PLBC405ICUADDRACK;
13792 
input PLBC405ICUBUSY;
13793 
input PLBC405ICUERR;
13794 
input PLBC405ICURDDACK;
13795 
input [0:63] PLBC405ICURDDBUS;
13796 
input [1:3] PLBC405ICURDWDADDR;
13797 
input PLBC405ICUSSIZE1;
13798 
input PLBCLK;
13799 
input RSTC405RESETCHIP;
13800 
input RSTC405RESETCORE;
13801 
input RSTC405RESETSYS;
13802 
input [0:15] TIEAPUCONTROL;
13803 
input [0:23] TIEAPUUDI1;
13804 
input [0:23] TIEAPUUDI2;
13805 
input [0:23] TIEAPUUDI3;
13806 
input [0:23] TIEAPUUDI4;
13807 
input [0:23] TIEAPUUDI5;
13808 
input [0:23] TIEAPUUDI6;
13809 
input [0:23] TIEAPUUDI7;
13810 
input [0:23] TIEAPUUDI8;
13811 
input TIEC405DETERMINISTICMULT;
13812 
input TIEC405DISOPERANDFWD;
13813 
input TIEC405MMUEN;
13814 
input [0:5] TIEDCRADDR;
13815 
input TIEPVRBIT10;
13816 
input TIEPVRBIT11;
13817 
input TIEPVRBIT28;
13818 
input TIEPVRBIT29;
13819 
input TIEPVRBIT30;
13820 
input TIEPVRBIT31;
13821 
input TIEPVRBIT8;
13822 
input TIEPVRBIT9;
13823 
input TRCC405TRACEDISABLE;
13824 
input TRCC405TRIGGEREVENTIN;
13825 
endmodule
13826 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13827 
module PPC405 (C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DBGWBIAR, C405DCRABUS, C405DCRDBUSOUT, C405DCRREAD, C405DCRWRITE, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUABUS, C405PLBDCUBE, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUPRIORITY, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRDBUS, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUABUS, C405PLBICUCACHEABLE, C405PLBICUPRIORITY, C405PLBICUREQUEST, C405PLBICUSIZE, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, C405XXXMACHINECHECK, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, BRAMISOCMRDDBUS, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DCRC405ACK, DCRC405DBUSIN, DSARCVALUE, DSCNTLVALUE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ, ISARCVALUE, ISCNTLVALUE, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCURDDBUS, PLBC405DCURDWDADDR, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICURDDBUS, PLBC405ICURDWDADDR, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEDSOCMDCRADDR, TIEISOCMDCRADDR, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN);
13828 
parameter PPCUSER = 4'b0000;
13829 
output C405CPMCORESLEEPREQ;
13830 
output C405CPMMSRCE;
13831 
output C405CPMMSREE;
13832 
output C405CPMTIMERIRQ;
13833 
output C405CPMTIMERRESETREQ;
13834 
output C405DBGMSRWE;
13835 
output C405DBGSTOPACK;
13836 
output C405DBGWBCOMPLETE;
13837 
output C405DBGWBFULL;
13838 
output [0:29] C405DBGWBIAR;
13839 
output [0:9] C405DCRABUS;
13840 
output [0:31] C405DCRDBUSOUT;
13841 
output C405DCRREAD;
13842 
output C405DCRWRITE;
13843 
output C405JTGCAPTUREDR;
13844 
output C405JTGEXTEST;
13845 
output C405JTGPGMOUT;
13846 
output C405JTGSHIFTDR;
13847 
output C405JTGTDO;
13848 
output C405JTGTDOEN;
13849 
output C405JTGUPDATEDR;
13850 
output C405PLBDCUABORT;
13851 
output [0:31] C405PLBDCUABUS;
13852 
output [0:7] C405PLBDCUBE;
13853 
output C405PLBDCUCACHEABLE;
13854 
output C405PLBDCUGUARDED;
13855 
output [0:1] C405PLBDCUPRIORITY;
13856 
output C405PLBDCUREQUEST;
13857 
output C405PLBDCURNW;
13858 
output C405PLBDCUSIZE2;
13859 
output C405PLBDCUU0ATTR;
13860 
output [0:63] C405PLBDCUWRDBUS;
13861 
output C405PLBDCUWRITETHRU;
13862 
output C405PLBICUABORT;
13863 
output [0:29] C405PLBICUABUS;
13864 
output C405PLBICUCACHEABLE;
13865 
output [0:1] C405PLBICUPRIORITY;
13866 
output C405PLBICUREQUEST;
13867 
output [2:3] C405PLBICUSIZE;
13868 
output C405PLBICUU0ATTR;
13869 
output C405RSTCHIPRESETREQ;
13870 
output C405RSTCORERESETREQ;
13871 
output C405RSTSYSRESETREQ;
13872 
output C405TRCCYCLE;
13873 
output [0:1] C405TRCEVENEXECUTIONSTATUS;
13874 
output [0:1] C405TRCODDEXECUTIONSTATUS;
13875 
output [0:3] C405TRCTRACESTATUS;
13876 
output C405TRCTRIGGEREVENTOUT;
13877 
output [0:10] C405TRCTRIGGEREVENTTYPE;
13878 
output C405XXXMACHINECHECK;
13879 
output [8:29] DSOCMBRAMABUS;
13880 
output [0:3] DSOCMBRAMBYTEWRITE;
13881 
output DSOCMBRAMEN;
13882 
output [0:31] DSOCMBRAMWRDBUS;
13883 
output DSOCMBUSY;
13884 
output ISOCMBRAMEN;
13885 
output ISOCMBRAMEVENWRITEEN;
13886 
output ISOCMBRAMODDWRITEEN;
13887 
output [8:28] ISOCMBRAMRDABUS;
13888 
output [8:28] ISOCMBRAMWRABUS;
13889 
output [0:31] ISOCMBRAMWRDBUS;
13890 
input BRAMDSOCMCLK;
13891 
input [0:31] BRAMDSOCMRDDBUS;
13892 
input BRAMISOCMCLK;
13893 
input [0:63] BRAMISOCMRDDBUS;
13894 
input CPMC405CLOCK;
13895 
input CPMC405CORECLKINACTIVE;
13896 
input CPMC405CPUCLKEN;
13897 
input CPMC405JTAGCLKEN;
13898 
input CPMC405TIMERCLKEN;
13899 
input CPMC405TIMERTICK;
13900 
input DBGC405DEBUGHALT;
13901 
input DBGC405EXTBUSHOLDACK;
13902 
input DBGC405UNCONDDEBUGEVENT;
13903 
input DCRC405ACK;
13904 
input [0:31] DCRC405DBUSIN;
13905 
input [0:7] DSARCVALUE;
13906 
input [0:7] DSCNTLVALUE;
13907 
input EICC405CRITINPUTIRQ;
13908 
input EICC405EXTINPUTIRQ;
13909 
input [0:7] ISARCVALUE;
13910 
input [0:7] ISCNTLVALUE;
13911 
input JTGC405BNDSCANTDO;
13912 
input JTGC405TCK;
13913 
input JTGC405TDI;
13914 
input JTGC405TMS;
13915 
input JTGC405TRSTNEG;
13916 
input MCBCPUCLKEN;
13917 
input MCBJTAGEN;
13918 
input MCBTIMEREN;
13919 
input MCPPCRST;
13920 
input PLBC405DCUADDRACK;
13921 
input PLBC405DCUBUSY;
13922 
input PLBC405DCUERR;
13923 
input PLBC405DCURDDACK;
13924 
input [0:63] PLBC405DCURDDBUS;
13925 
input [1:3] PLBC405DCURDWDADDR;
13926 
input PLBC405DCUSSIZE1;
13927 
input PLBC405DCUWRDACK;
13928 
input PLBC405ICUADDRACK;
13929 
input PLBC405ICUBUSY;
13930 
input PLBC405ICUERR;
13931 
input PLBC405ICURDDACK;
13932 
input [0:63] PLBC405ICURDDBUS;
13933 
input [1:3] PLBC405ICURDWDADDR;
13934 
input PLBC405ICUSSIZE1;
13935 
input PLBCLK;
13936 
input RSTC405RESETCHIP;
13937 
input RSTC405RESETCORE;
13938 
input RSTC405RESETSYS;
13939 
input TIEC405DETERMINISTICMULT;
13940 
input TIEC405DISOPERANDFWD;
13941 
input TIEC405MMUEN;
13942 
input [0:7] TIEDSOCMDCRADDR;
13943 
input [0:7] TIEISOCMDCRADDR;
13944 
input TRCC405TRACEDISABLE;
13945 
input TRCC405TRIGGEREVENTIN;
13946 
endmodule
13947 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
13948 
module PPC440 (APUFCMDECFPUOP, APUFCMDECLDSTXFERSIZE, APUFCMDECLOAD, APUFCMDECNONAUTON, APUFCMDECSTORE, APUFCMDECUDI, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRUCTION, APUFCMINSTRVALID, APUFCMLOADBYTEADDR, APUFCMLOADDATA, APUFCMLOADDVALID, APUFCMMSRFE0, APUFCMMSRFE1, APUFCMNEXTINSTRREADY, APUFCMOPERANDVALID, APUFCMRADATA, APUFCMRBDATA, APUFCMWRITEBACKOK, C440CPMCORESLEEPREQ, C440CPMDECIRPTREQ, C440CPMFITIRPTREQ, C440CPMMSRCE, C440CPMMSREE, C440CPMTIMERRESETREQ, C440CPMWDIRPTREQ, C440DBGSYSTEMCONTROL, C440JTGTDO, C440JTGTDOEN, C440MACHINECHECK, C440RSTCHIPRESETREQ, C440RSTCORERESETREQ, C440RSTSYSTEMRESETREQ, C440TRCBRANCHSTATUS, C440TRCCYCLE, C440TRCEXECUTIONSTATUS, C440TRCTRACESTATUS, C440TRCTRIGGEREVENTOUT, C440TRCTRIGGEREVENTTYPE, DMA0LLRSTENGINEACK, DMA0LLRXDSTRDYN, DMA0LLTXD, DMA0LLTXEOFN, DMA0LLTXEOPN, DMA0LLTXREM, DMA0LLTXSOFN, DMA0LLTXSOPN, DMA0LLTXSRCRDYN, DMA0RXIRQ, DMA0TXIRQ, DMA1LLRSTENGINEACK, DMA1LLRXDSTRDYN, DMA1LLTXD, DMA1LLTXEOFN, DMA1LLTXEOPN, DMA1LLTXREM, DMA1LLTXSOFN, DMA1LLTXSOPN, DMA1LLTXSRCRDYN, DMA1RXIRQ, DMA1TXIRQ, DMA2LLRSTENGINEACK, DMA2LLRXDSTRDYN, DMA2LLTXD, DMA2LLTXEOFN, DMA2LLTXEOPN, DMA2LLTXREM, DMA2LLTXSOFN, DMA2LLTXSOPN, DMA2LLTXSRCRDYN, DMA2RXIRQ, DMA2TXIRQ, DMA3LLRSTENGINEACK, DMA3LLRXDSTRDYN, DMA3LLTXD, DMA3LLTXEOFN, DMA3LLTXEOPN, DMA3LLTXREM, DMA3LLTXSOFN, DMA3LLTXSOPN, DMA3LLTXSRCRDYN, DMA3RXIRQ, DMA3TXIRQ, MIMCADDRESS, MIMCADDRESSVALID, MIMCBANKCONFLICT, MIMCBYTEENABLE, MIMCREADNOTWRITE, MIMCROWCONFLICT, MIMCWRITEDATA, MIMCWRITEDATAVALID, PPCCPMINTERCONNECTBUSY, PPCDMDCRABUS, PPCDMDCRDBUSOUT, PPCDMDCRREAD, PPCDMDCRUABUS, PPCDMDCRWRITE, PPCDSDCRACK, PPCDSDCRDBUSIN, PPCDSDCRTIMEOUTWAIT, PPCEICINTERCONNECTIRQ, PPCMPLBABORT, PPCMPLBABUS, PPCMPLBBE, PPCMPLBBUSLOCK, PPCMPLBLOCKERR, PPCMPLBPRIORITY, PPCMPLBRDBURST, PPCMPLBREQUEST, PPCMPLBRNW, PPCMPLBSIZE, PPCMPLBTATTRIBUTE, PPCMPLBTYPE, PPCMPLBUABUS, PPCMPLBWRBURST, PPCMPLBWRDBUS, PPCS0PLBADDRACK, PPCS0PLBMBUSY, PPCS0PLBMIRQ, PPCS0PLBMRDERR, PPCS0PLBMWRERR, PPCS0PLBRDBTERM, PPCS0PLBRDCOMP, PPCS0PLBRDDACK, PPCS0PLBRDDBUS, PPCS0PLBRDWDADDR, PPCS0PLBREARBITRATE, PPCS0PLBSSIZE, PPCS0PLBWAIT, PPCS0PLBWRBTERM, PPCS0PLBWRCOMP, PPCS0PLBWRDACK, PPCS1PLBADDRACK, PPCS1PLBMBUSY, PPCS1PLBMIRQ, PPCS1PLBMRDERR, PPCS1PLBMWRERR, PPCS1PLBRDBTERM, PPCS1PLBRDCOMP, PPCS1PLBRDDACK, PPCS1PLBRDDBUS, PPCS1PLBRDWDADDR, PPCS1PLBREARBITRATE, PPCS1PLBSSIZE, PPCS1PLBWAIT, PPCS1PLBWRBTERM, PPCS1PLBWRCOMP, PPCS1PLBWRDACK, CPMC440CLK, CPMC440CLKEN, CPMC440CORECLOCKINACTIVE, CPMC440TIMERCLOCK, CPMDCRCLK, CPMDMA0LLCLK, CPMDMA1LLCLK, CPMDMA2LLCLK, CPMDMA3LLCLK, CPMFCMCLK, CPMINTERCONNECTCLK, CPMINTERCONNECTCLKEN, CPMINTERCONNECTCLKNTO1, CPMMCCLK, CPMPPCMPLBCLK, CPMPPCS0PLBCLK, CPMPPCS1PLBCLK, DBGC440DEBUGHALT, DBGC440SYSTEMSTATUS, DBGC440UNCONDDEBUGEVENT, DCRPPCDMACK, DCRPPCDMDBUSIN, DCRPPCDMTIMEOUTWAIT, DCRPPCDSABUS, DCRPPCDSDBUSOUT, DCRPPCDSREAD, DCRPPCDSWRITE, EICC440CRITIRQ, EICC440EXTIRQ, FCMAPUCONFIRMINSTR, FCMAPUCR, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUFPSCRFEX, FCMAPURESULT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUSTOREDATA, JTGC440TCK, JTGC440TDI, JTGC440TMS, JTGC440TRSTNEG, LLDMA0RSTENGINEREQ, LLDMA0RXD, LLDMA0RXEOFN, LLDMA0RXEOPN, LLDMA0RXREM, LLDMA0RXSOFN, LLDMA0RXSOPN, LLDMA0RXSRCRDYN, LLDMA0TXDSTRDYN, LLDMA1RSTENGINEREQ, LLDMA1RXD, LLDMA1RXEOFN, LLDMA1RXEOPN, LLDMA1RXREM, LLDMA1RXSOFN, LLDMA1RXSOPN, LLDMA1RXSRCRDYN, LLDMA1TXDSTRDYN, LLDMA2RSTENGINEREQ, LLDMA2RXD, LLDMA2RXEOFN, LLDMA2RXEOPN, LLDMA2RXREM, LLDMA2RXSOFN, LLDMA2RXSOPN, LLDMA2RXSRCRDYN, LLDMA2TXDSTRDYN, LLDMA3RSTENGINEREQ, LLDMA3RXD, LLDMA3RXEOFN, LLDMA3RXEOPN, LLDMA3RXREM, LLDMA3RXSOFN, LLDMA3RXSOPN, LLDMA3RXSRCRDYN, LLDMA3TXDSTRDYN, MCMIADDRREADYTOACCEPT, MCMIREADDATA, MCMIREADDATAERR, MCMIREADDATAVALID, PLBPPCMADDRACK, PLBPPCMMBUSY, PLBPPCMMIRQ, PLBPPCMMRDERR, PLBPPCMMWRERR, PLBPPCMRDBTERM, PLBPPCMRDDACK, PLBPPCMRDDBUS, PLBPPCMRDPENDPRI, PLBPPCMRDPENDREQ, PLBPPCMRDWDADDR, PLBPPCMREARBITRATE, PLBPPCMREQPRI, PLBPPCMSSIZE, PLBPPCMTIMEOUT, PLBPPCMWRBTERM, PLBPPCMWRDACK, PLBPPCMWRPENDPRI, PLBPPCMWRPENDREQ, PLBPPCS0ABORT, PLBPPCS0ABUS, PLBPPCS0BE, PLBPPCS0BUSLOCK, PLBPPCS0LOCKERR, PLBPPCS0MASTERID, PLBPPCS0MSIZE, PLBPPCS0PAVALID, PLBPPCS0RDBURST, PLBPPCS0RDPENDPRI, PLBPPCS0RDPENDREQ, PLBPPCS0RDPRIM, PLBPPCS0REQPRI, PLBPPCS0RNW, PLBPPCS0SAVALID, PLBPPCS0SIZE, PLBPPCS0TATTRIBUTE, PLBPPCS0TYPE, PLBPPCS0UABUS, PLBPPCS0WRBURST, PLBPPCS0WRDBUS, PLBPPCS0WRPENDPRI, PLBPPCS0WRPENDREQ, PLBPPCS0WRPRIM, PLBPPCS1ABORT, PLBPPCS1ABUS, PLBPPCS1BE, PLBPPCS1BUSLOCK, PLBPPCS1LOCKERR, PLBPPCS1MASTERID, PLBPPCS1MSIZE, PLBPPCS1PAVALID, PLBPPCS1RDBURST, PLBPPCS1RDPENDPRI, PLBPPCS1RDPENDREQ, PLBPPCS1RDPRIM, PLBPPCS1REQPRI, PLBPPCS1RNW, PLBPPCS1SAVALID, PLBPPCS1SIZE, PLBPPCS1TATTRIBUTE, PLBPPCS1TYPE, PLBPPCS1UABUS, PLBPPCS1WRBURST, PLBPPCS1WRDBUS, PLBPPCS1WRPENDPRI, PLBPPCS1WRPENDREQ, PLBPPCS1WRPRIM, RSTC440RESETCHIP, RSTC440RESETCORE, RSTC440RESETSYSTEM, TIEC440DCURDLDCACHEPLBPRIO, TIEC440DCURDNONCACHEPLBPRIO, TIEC440DCURDTOUCHPLBPRIO, TIEC440DCURDURGENTPLBPRIO, TIEC440DCUWRFLUSHPLBPRIO, TIEC440DCUWRSTOREPLBPRIO, TIEC440DCUWRURGENTPLBPRIO, TIEC440ENDIANRESET, TIEC440ERPNRESET, TIEC440ICURDFETCHPLBPRIO, TIEC440ICURDSPECPLBPRIO, TIEC440ICURDTOUCHPLBPRIO, TIEC440PIR, TIEC440PVR, TIEC440USERRESET, TIEDCRBASEADDR, TRCC440TRACEDISABLE, TRCC440TRIGGEREVENTIN);
13949 
parameter CLOCK_DELAY = "FALSE";
13950 
parameter DCR_AUTOLOCK_ENABLE = "TRUE";
13951 
parameter PPCDM_ASYNCMODE = "FALSE";
13952 
parameter PPCDS_ASYNCMODE = "FALSE";
13953 
parameter PPCS0_WIDTH_128N64 = "TRUE";
13954 
parameter PPCS1_WIDTH_128N64 = "TRUE";
13955 
parameter [0:16] APU_CONTROL = 17'h02000;
13956 
parameter [0:23] APU_UDI0 = 24'h000000;
13957 
parameter [0:23] APU_UDI1 = 24'h000000;
13958 
parameter [0:23] APU_UDI10 = 24'h000000;
13959 
parameter [0:23] APU_UDI11 = 24'h000000;
13960 
parameter [0:23] APU_UDI12 = 24'h000000;
13961 
parameter [0:23] APU_UDI13 = 24'h000000;
13962 
parameter [0:23] APU_UDI14 = 24'h000000;
13963 
parameter [0:23] APU_UDI15 = 24'h000000;
13964 
parameter [0:23] APU_UDI2 = 24'h000000;
13965 
parameter [0:23] APU_UDI3 = 24'h000000;
13966 
parameter [0:23] APU_UDI4 = 24'h000000;
13967 
parameter [0:23] APU_UDI5 = 24'h000000;
13968 
parameter [0:23] APU_UDI6 = 24'h000000;
13969 
parameter [0:23] APU_UDI7 = 24'h000000;
13970 
parameter [0:23] APU_UDI8 = 24'h000000;
13971 
parameter [0:23] APU_UDI9 = 24'h000000;
13972 
parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000;
13973 
parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000;
13974 
parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000;
13975 
parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000;
13976 
parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000;
13977 
parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000;
13978 
parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000;
13979 
parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000;
13980 
parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF;
13981 
parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF;
13982 
parameter [0:31] MI_ARBCONFIG = 32'h00432010;
13983 
parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000;
13984 
parameter [0:31] MI_CONTROL = 32'h0000008F;
13985 
parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000;
13986 
parameter [0:31] PPCM_ARBCONFIG = 32'h00432010;
13987 
parameter [0:31] PPCM_CONTROL = 32'h8000009F;
13988 
parameter [0:31] PPCM_COUNTER = 32'h00000500;
13989 
parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
13990 
parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
13991 
parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
13992 
parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
13993 
parameter [0:31] PPCS0_CONTROL = 32'h8033336C;
13994 
parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
13995 
parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
13996 
parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
13997 
parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
13998 
parameter [0:31] PPCS1_CONTROL = 32'h8033336C;
13999 
parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000;
14000 
parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000;
14001 
parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000;
14002 
parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000;
14003 
parameter [0:7] DMA0_CONTROL = 8'h00;
14004 
parameter [0:7] DMA1_CONTROL = 8'h00;
14005 
parameter [0:7] DMA2_CONTROL = 8'h00;
14006 
parameter [0:7] DMA3_CONTROL = 8'h00;
14007 
parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF;
14008 
parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF;
14009 
parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF;
14010 
parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF;
14011 
parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF;
14012 
parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF;
14013 
parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF;
14014 
parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF;
14015 
output APUFCMDECFPUOP;
14016 
output [0:2] APUFCMDECLDSTXFERSIZE;
14017 
output APUFCMDECLOAD;
14018 
output APUFCMDECNONAUTON;
14019 
output APUFCMDECSTORE;
14020 
output [0:3] APUFCMDECUDI;
14021 
output APUFCMDECUDIVALID;
14022 
output APUFCMENDIAN;
14023 
output APUFCMFLUSH;
14024 
output [0:31] APUFCMINSTRUCTION;
14025 
output APUFCMINSTRVALID;
14026 
output [0:3] APUFCMLOADBYTEADDR;
14027 
output [0:127] APUFCMLOADDATA;
14028 
output APUFCMLOADDVALID;
14029 
output APUFCMMSRFE0;
14030 
output APUFCMMSRFE1;
14031 
output APUFCMNEXTINSTRREADY;
14032 
output APUFCMOPERANDVALID;
14033 
output [0:31] APUFCMRADATA;
14034 
output [0:31] APUFCMRBDATA;
14035 
output APUFCMWRITEBACKOK;
14036 
output C440CPMCORESLEEPREQ;
14037 
output C440CPMDECIRPTREQ;
14038 
output C440CPMFITIRPTREQ;
14039 
output C440CPMMSRCE;
14040 
output C440CPMMSREE;
14041 
output C440CPMTIMERRESETREQ;
14042 
output C440CPMWDIRPTREQ;
14043 
output [0:7] C440DBGSYSTEMCONTROL;
14044 
output C440JTGTDO;
14045 
output C440JTGTDOEN;
14046 
output C440MACHINECHECK;
14047 
output C440RSTCHIPRESETREQ;
14048 
output C440RSTCORERESETREQ;
14049 
output C440RSTSYSTEMRESETREQ;
14050 
output [0:2] C440TRCBRANCHSTATUS;
14051 
output C440TRCCYCLE;
14052 
output [0:4] C440TRCEXECUTIONSTATUS;
14053 
output [0:6] C440TRCTRACESTATUS;
14054 
output C440TRCTRIGGEREVENTOUT;
14055 
output [0:13] C440TRCTRIGGEREVENTTYPE;
14056 
output DMA0LLRSTENGINEACK;
14057 
output DMA0LLRXDSTRDYN;
14058 
output [0:31] DMA0LLTXD;
14059 
output DMA0LLTXEOFN;
14060 
output DMA0LLTXEOPN;
14061 
output [0:3] DMA0LLTXREM;
14062 
output DMA0LLTXSOFN;
14063 
output DMA0LLTXSOPN;
14064 
output DMA0LLTXSRCRDYN;
14065 
output DMA0RXIRQ;
14066 
output DMA0TXIRQ;
14067 
output DMA1LLRSTENGINEACK;
14068 
output DMA1LLRXDSTRDYN;
14069 
output [0:31] DMA1LLTXD;
14070 
output DMA1LLTXEOFN;
14071 
output DMA1LLTXEOPN;
14072 
output [0:3] DMA1LLTXREM;
14073 
output DMA1LLTXSOFN;
14074 
output DMA1LLTXSOPN;
14075 
output DMA1LLTXSRCRDYN;
14076 
output DMA1RXIRQ;
14077 
output DMA1TXIRQ;
14078 
output DMA2LLRSTENGINEACK;
14079 
output DMA2LLRXDSTRDYN;
14080 
output [0:31] DMA2LLTXD;
14081 
output DMA2LLTXEOFN;
14082 
output DMA2LLTXEOPN;
14083 
output [0:3] DMA2LLTXREM;
14084 
output DMA2LLTXSOFN;
14085 
output DMA2LLTXSOPN;
14086 
output DMA2LLTXSRCRDYN;
14087 
output DMA2RXIRQ;
14088 
output DMA2TXIRQ;
14089 
output DMA3LLRSTENGINEACK;
14090 
output DMA3LLRXDSTRDYN;
14091 
output [0:31] DMA3LLTXD;
14092 
output DMA3LLTXEOFN;
14093 
output DMA3LLTXEOPN;
14094 
output [0:3] DMA3LLTXREM;
14095 
output DMA3LLTXSOFN;
14096 
output DMA3LLTXSOPN;
14097 
output DMA3LLTXSRCRDYN;
14098 
output DMA3RXIRQ;
14099 
output DMA3TXIRQ;
14100 
output [0:35] MIMCADDRESS;
14101 
output MIMCADDRESSVALID;
14102 
output MIMCBANKCONFLICT;
14103 
output [0:15] MIMCBYTEENABLE;
14104 
output MIMCREADNOTWRITE;
14105 
output MIMCROWCONFLICT;
14106 
output [0:127] MIMCWRITEDATA;
14107 
output MIMCWRITEDATAVALID;
14108 
output PPCCPMINTERCONNECTBUSY;
14109 
output [0:9] PPCDMDCRABUS;
14110 
output [0:31] PPCDMDCRDBUSOUT;
14111 
output PPCDMDCRREAD;
14112 
output [20:21] PPCDMDCRUABUS;
14113 
output PPCDMDCRWRITE;
14114 
output PPCDSDCRACK;
14115 
output [0:31] PPCDSDCRDBUSIN;
14116 
output PPCDSDCRTIMEOUTWAIT;
14117 
output PPCEICINTERCONNECTIRQ;
14118 
output PPCMPLBABORT;
14119 
output [0:31] PPCMPLBABUS;
14120 
output [0:15] PPCMPLBBE;
14121 
output PPCMPLBBUSLOCK;
14122 
output PPCMPLBLOCKERR;
14123 
output [0:1] PPCMPLBPRIORITY;
14124 
output PPCMPLBRDBURST;
14125 
output PPCMPLBREQUEST;
14126 
output PPCMPLBRNW;
14127 
output [0:3] PPCMPLBSIZE;
14128 
output [0:15] PPCMPLBTATTRIBUTE;
14129 
output [0:2] PPCMPLBTYPE;
14130 
output [28:31] PPCMPLBUABUS;
14131 
output PPCMPLBWRBURST;
14132 
output [0:127] PPCMPLBWRDBUS;
14133 
output PPCS0PLBADDRACK;
14134 
output [0:3] PPCS0PLBMBUSY;
14135 
output [0:3] PPCS0PLBMIRQ;
14136 
output [0:3] PPCS0PLBMRDERR;
14137 
output [0:3] PPCS0PLBMWRERR;
14138 
output PPCS0PLBRDBTERM;
14139 
output PPCS0PLBRDCOMP;
14140 
output PPCS0PLBRDDACK;
14141 
output [0:127] PPCS0PLBRDDBUS;
14142 
output [0:3] PPCS0PLBRDWDADDR;
14143 
output PPCS0PLBREARBITRATE;
14144 
output [0:1] PPCS0PLBSSIZE;
14145 
output PPCS0PLBWAIT;
14146 
output PPCS0PLBWRBTERM;
14147 
output PPCS0PLBWRCOMP;
14148 
output PPCS0PLBWRDACK;
14149 
output PPCS1PLBADDRACK;
14150 
output [0:3] PPCS1PLBMBUSY;
14151 
output [0:3] PPCS1PLBMIRQ;
14152 
output [0:3] PPCS1PLBMRDERR;
14153 
output [0:3] PPCS1PLBMWRERR;
14154 
output PPCS1PLBRDBTERM;
14155 
output PPCS1PLBRDCOMP;
14156 
output PPCS1PLBRDDACK;
14157 
output [0:127] PPCS1PLBRDDBUS;
14158 
output [0:3] PPCS1PLBRDWDADDR;
14159 
output PPCS1PLBREARBITRATE;
14160 
output [0:1] PPCS1PLBSSIZE;
14161 
output PPCS1PLBWAIT;
14162 
output PPCS1PLBWRBTERM;
14163 
output PPCS1PLBWRCOMP;
14164 
output PPCS1PLBWRDACK;
14165 
input CPMC440CLK;
14166 
input CPMC440CLKEN;
14167 
input CPMC440CORECLOCKINACTIVE;
14168 
input CPMC440TIMERCLOCK;
14169 
input CPMDCRCLK;
14170 
input CPMDMA0LLCLK;
14171 
input CPMDMA1LLCLK;
14172 
input CPMDMA2LLCLK;
14173 
input CPMDMA3LLCLK;
14174 
input CPMFCMCLK;
14175 
input CPMINTERCONNECTCLK;
14176 
input CPMINTERCONNECTCLKEN;
14177 
input CPMINTERCONNECTCLKNTO1;
14178 
input CPMMCCLK;
14179 
input CPMPPCMPLBCLK;
14180 
input CPMPPCS0PLBCLK;
14181 
input CPMPPCS1PLBCLK;
14182 
input DBGC440DEBUGHALT;
14183 
input [0:4] DBGC440SYSTEMSTATUS;
14184 
input DBGC440UNCONDDEBUGEVENT;
14185 
input DCRPPCDMACK;
14186 
input [0:31] DCRPPCDMDBUSIN;
14187 
input DCRPPCDMTIMEOUTWAIT;
14188 
input [0:9] DCRPPCDSABUS;
14189 
input [0:31] DCRPPCDSDBUSOUT;
14190 
input DCRPPCDSREAD;
14191 
input DCRPPCDSWRITE;
14192 
input EICC440CRITIRQ;
14193 
input EICC440EXTIRQ;
14194 
input FCMAPUCONFIRMINSTR;
14195 
input [0:3] FCMAPUCR;
14196 
input FCMAPUDONE;
14197 
input FCMAPUEXCEPTION;
14198 
input FCMAPUFPSCRFEX;
14199 
input [0:31] FCMAPURESULT;
14200 
input FCMAPURESULTVALID;
14201 
input FCMAPUSLEEPNOTREADY;
14202 
input [0:127] FCMAPUSTOREDATA;
14203 
input JTGC440TCK;
14204 
input JTGC440TDI;
14205 
input JTGC440TMS;
14206 
input JTGC440TRSTNEG;
14207 
input LLDMA0RSTENGINEREQ;
14208 
input [0:31] LLDMA0RXD;
14209 
input LLDMA0RXEOFN;
14210 
input LLDMA0RXEOPN;
14211 
input [0:3] LLDMA0RXREM;
14212 
input LLDMA0RXSOFN;
14213 
input LLDMA0RXSOPN;
14214 
input LLDMA0RXSRCRDYN;
14215 
input LLDMA0TXDSTRDYN;
14216 
input LLDMA1RSTENGINEREQ;
14217 
input [0:31] LLDMA1RXD;
14218 
input LLDMA1RXEOFN;
14219 
input LLDMA1RXEOPN;
14220 
input [0:3] LLDMA1RXREM;
14221 
input LLDMA1RXSOFN;
14222 
input LLDMA1RXSOPN;
14223 
input LLDMA1RXSRCRDYN;
14224 
input LLDMA1TXDSTRDYN;
14225 
input LLDMA2RSTENGINEREQ;
14226 
input [0:31] LLDMA2RXD;
14227 
input LLDMA2RXEOFN;
14228 
input LLDMA2RXEOPN;
14229 
input [0:3] LLDMA2RXREM;
14230 
input LLDMA2RXSOFN;
14231 
input LLDMA2RXSOPN;
14232 
input LLDMA2RXSRCRDYN;
14233 
input LLDMA2TXDSTRDYN;
14234 
input LLDMA3RSTENGINEREQ;
14235 
input [0:31] LLDMA3RXD;
14236 
input LLDMA3RXEOFN;
14237 
input LLDMA3RXEOPN;
14238 
input [0:3] LLDMA3RXREM;
14239 
input LLDMA3RXSOFN;
14240 
input LLDMA3RXSOPN;
14241 
input LLDMA3RXSRCRDYN;
14242 
input LLDMA3TXDSTRDYN;
14243 
input MCMIADDRREADYTOACCEPT;
14244 
input [0:127] MCMIREADDATA;
14245 
input MCMIREADDATAERR;
14246 
input MCMIREADDATAVALID;
14247 
input PLBPPCMADDRACK;
14248 
input PLBPPCMMBUSY;
14249 
input PLBPPCMMIRQ;
14250 
input PLBPPCMMRDERR;
14251 
input PLBPPCMMWRERR;
14252 
input PLBPPCMRDBTERM;
14253 
input PLBPPCMRDDACK;
14254 
input [0:127] PLBPPCMRDDBUS;
14255 
input [0:1] PLBPPCMRDPENDPRI;
14256 
input PLBPPCMRDPENDREQ;
14257 
input [0:3] PLBPPCMRDWDADDR;
14258 
input PLBPPCMREARBITRATE;
14259 
input [0:1] PLBPPCMREQPRI;
14260 
input [0:1] PLBPPCMSSIZE;
14261 
input PLBPPCMTIMEOUT;
14262 
input PLBPPCMWRBTERM;
14263 
input PLBPPCMWRDACK;
14264 
input [0:1] PLBPPCMWRPENDPRI;
14265 
input PLBPPCMWRPENDREQ;
14266 
input PLBPPCS0ABORT;
14267 
input [0:31] PLBPPCS0ABUS;
14268 
input [0:15] PLBPPCS0BE;
14269 
input PLBPPCS0BUSLOCK;
14270 
input PLBPPCS0LOCKERR;
14271 
input [0:1] PLBPPCS0MASTERID;
14272 
input [0:1] PLBPPCS0MSIZE;
14273 
input PLBPPCS0PAVALID;
14274 
input PLBPPCS0RDBURST;
14275 
input [0:1] PLBPPCS0RDPENDPRI;
14276 
input PLBPPCS0RDPENDREQ;
14277 
input PLBPPCS0RDPRIM;
14278 
input [0:1] PLBPPCS0REQPRI;
14279 
input PLBPPCS0RNW;
14280 
input PLBPPCS0SAVALID;
14281 
input [0:3] PLBPPCS0SIZE;
14282 
input [0:15] PLBPPCS0TATTRIBUTE;
14283 
input [0:2] PLBPPCS0TYPE;
14284 
input [28:31] PLBPPCS0UABUS;
14285 
input PLBPPCS0WRBURST;
14286 
input [0:127] PLBPPCS0WRDBUS;
14287 
input [0:1] PLBPPCS0WRPENDPRI;
14288 
input PLBPPCS0WRPENDREQ;
14289 
input PLBPPCS0WRPRIM;
14290 
input PLBPPCS1ABORT;
14291 
input [0:31] PLBPPCS1ABUS;
14292 
input [0:15] PLBPPCS1BE;
14293 
input PLBPPCS1BUSLOCK;
14294 
input PLBPPCS1LOCKERR;
14295 
input [0:1] PLBPPCS1MASTERID;
14296 
input [0:1] PLBPPCS1MSIZE;
14297 
input PLBPPCS1PAVALID;
14298 
input PLBPPCS1RDBURST;
14299 
input [0:1] PLBPPCS1RDPENDPRI;
14300 
input PLBPPCS1RDPENDREQ;
14301 
input PLBPPCS1RDPRIM;
14302 
input [0:1] PLBPPCS1REQPRI;
14303 
input PLBPPCS1RNW;
14304 
input PLBPPCS1SAVALID;
14305 
input [0:3] PLBPPCS1SIZE;
14306 
input [0:15] PLBPPCS1TATTRIBUTE;
14307 
input [0:2] PLBPPCS1TYPE;
14308 
input [28:31] PLBPPCS1UABUS;
14309 
input PLBPPCS1WRBURST;
14310 
input [0:127] PLBPPCS1WRDBUS;
14311 
input [0:1] PLBPPCS1WRPENDPRI;
14312 
input PLBPPCS1WRPENDREQ;
14313 
input PLBPPCS1WRPRIM;
14314 
input RSTC440RESETCHIP;
14315 
input RSTC440RESETCORE;
14316 
input RSTC440RESETSYSTEM;
14317 
input [0:1] TIEC440DCURDLDCACHEPLBPRIO;
14318 
input [0:1] TIEC440DCURDNONCACHEPLBPRIO;
14319 
input [0:1] TIEC440DCURDTOUCHPLBPRIO;
14320 
input [0:1] TIEC440DCURDURGENTPLBPRIO;
14321 
input [0:1] TIEC440DCUWRFLUSHPLBPRIO;
14322 
input [0:1] TIEC440DCUWRSTOREPLBPRIO;
14323 
input [0:1] TIEC440DCUWRURGENTPLBPRIO;
14324 
input TIEC440ENDIANRESET;
14325 
input [0:3] TIEC440ERPNRESET;
14326 
input [0:1] TIEC440ICURDFETCHPLBPRIO;
14327 
input [0:1] TIEC440ICURDSPECPLBPRIO;
14328 
input [0:1] TIEC440ICURDTOUCHPLBPRIO;
14329 
input [28:31] TIEC440PIR;
14330 
input [28:31] TIEC440PVR;
14331 
input [0:3] TIEC440USERRESET;
14332 
input [0:1] TIEDCRBASEADDR;
14333 
input TRCC440TRACEDISABLE;
14334 
input TRCC440TRIGGEREVENTIN;
14335 
endmodule
14336 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14337 
module PULLDOWN (O);
14338 
output O;
14339 
endmodule
14340 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14341 
module PULLUP (O);
14342 
output O;
14343 
endmodule
14344 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14345 
module RAM128X1D (DPO, SPO, A, D, DPRA, WCLK, WE);
14346 
parameter INIT = 128'h0;
14347 
output DPO;
14348 
output SPO;
14349 
input [6:0] A;
14350 
input D;
14351 
input [6:0] DPRA;
14352 
input WCLK;
14353 
input WE;
14354 
endmodule
14355 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14356 
module RAM128X1S_1 (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
14357 
parameter INIT = 128'h00000000000000000000000000000000;
14358 
output O;
14359 
input A0;
14360 
input A1;
14361 
input A2;
14362 
input A3;
14363 
input A4;
14364 
input A5;
14365 
input A6;
14366 
input D;
14367 
input WCLK;
14368 
input WE;
14369 
endmodule
14370 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14371 
module RAM128X1S (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
14372 
parameter INIT = 128'h00000000000000000000000000000000;
14373 
output O;
14374 
input A0;
14375 
input A1;
14376 
input A2;
14377 
input A3;
14378 
input A4;
14379 
input A5;
14380 
input A6;
14381 
input D;
14382 
input WCLK;
14383 
input WE;
14384 
endmodule
14385 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14386 
module RAM16X1D_1 (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);
14387 
parameter INIT = 16'h0000;
14388 
output DPO;
14389 
output SPO;
14390 
input A0;
14391 
input A1;
14392 
input A2;
14393 
input A3;
14394 
input D;
14395 
input DPRA0;
14396 
input DPRA1;
14397 
input DPRA2;
14398 
input DPRA3;
14399 
input WCLK;
14400 
input WE;
14401 
endmodule
14402 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14403 
module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);
14404 
parameter INIT = 16'h0000;
14405 
output DPO;
14406 
output SPO;
14407 
input A0;
14408 
input A1;
14409 
input A2;
14410 
input A3;
14411 
input D;
14412 
input DPRA0;
14413 
input DPRA1;
14414 
input DPRA2;
14415 
input DPRA3;
14416 
input WCLK;
14417 
input WE;
14418 
endmodule
14419 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14420 
module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE);
14421 
parameter INIT = 16'h0000;
14422 
output O;
14423 
input A0;
14424 
input A1;
14425 
input A2;
14426 
input A3;
14427 
input D;
14428 
input WCLK;
14429 
input WE;
14430 
endmodule
14431 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14432 
module RAM16X1S (O, A0, A1, A2, A3, D, WCLK, WE);
14433 
parameter INIT = 16'h0000;
14434 
output O;
14435 
input A0;
14436 
input A1;
14437 
input A2;
14438 
input A3;
14439 
input D;
14440 
input WCLK;
14441 
input WE;
14442 
endmodule
14443 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14444 
module RAM16X2S (O0, O1, A0, A1, A2, A3, D0, D1, WCLK, WE);
14445 
parameter INIT_00 = 16'h0000;
14446 
parameter INIT_01 = 16'h0000;
14447 
output O0;
14448 
output O1;
14449 
input A0;
14450 
input A1;
14451 
input A2;
14452 
input A3;
14453 
input D0;
14454 
input D1;
14455 
input WCLK;
14456 
input WE;
14457 
endmodule
14458 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14459 
module RAM16X4S (O0, O1, O2, O3, A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE);
14460 
parameter INIT_00 = 16'h0000;
14461 
parameter INIT_01 = 16'h0000;
14462 
parameter INIT_02 = 16'h0000;
14463 
parameter INIT_03 = 16'h0000;
14464 
output O0;
14465 
output O1;
14466 
output O2;
14467 
output O3;
14468 
input A0;
14469 
input A1;
14470 
input A2;
14471 
input A3;
14472 
input D0;
14473 
input D1;
14474 
input D2;
14475 
input D3;
14476 
input WCLK;
14477 
input WE;
14478 
endmodule
14479 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14480 
module RAM16X8S (O, A0, A1, A2, A3, D, WCLK, WE);
14481 
parameter INIT_00 = 16'h0000;
14482 
parameter INIT_01 = 16'h0000;
14483 
parameter INIT_02 = 16'h0000;
14484 
parameter INIT_03 = 16'h0000;
14485 
parameter INIT_04 = 16'h0000;
14486 
parameter INIT_05 = 16'h0000;
14487 
parameter INIT_06 = 16'h0000;
14488 
parameter INIT_07 = 16'h0000;
14489 
output [7:0] O;
14490 
input A0;
14491 
input A1;
14492 
input A2;
14493 
input A3;
14494 
input [7:0] D;
14495 
input WCLK;
14496 
input WE;
14497 
endmodule
14498 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14499 
module RAM256X1S (O, A, D, WCLK, WE);
14500 
parameter INIT = 256'h0;
14501 
output O;
14502 
input [7:0] A;
14503 
input D;
14504 
input WCLK;
14505 
input WE;
14506 
endmodule
14507 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14508 
module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);
14509 
parameter INIT_A = 64'h0000000000000000;
14510 
parameter INIT_B = 64'h0000000000000000;
14511 
parameter INIT_C = 64'h0000000000000000;
14512 
parameter INIT_D = 64'h0000000000000000;
14513 
output [1:0] DOA;
14514 
output [1:0] DOB;
14515 
output [1:0] DOC;
14516 
output [1:0] DOD;
14517 
input [4:0] ADDRA;
14518 
input [4:0] ADDRB;
14519 
input [4:0] ADDRC;
14520 
input [4:0] ADDRD;
14521 
input [1:0] DIA;
14522 
input [1:0] DIB;
14523 
input [1:0] DIC;
14524 
input [1:0] DID;
14525 
input WCLK;
14526 
input WE;
14527 
endmodule
14528 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14529 
module RAM32X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
14530 
parameter INIT = 32'h00000000;
14531 
output DPO;
14532 
output SPO;
14533 
input A0;
14534 
input A1;
14535 
input A2;
14536 
input A3;
14537 
input A4;
14538 
input D;
14539 
input DPRA0;
14540 
input DPRA1;
14541 
input DPRA2;
14542 
input DPRA3;
14543 
input DPRA4;
14544 
input WCLK;
14545 
input WE;
14546 
endmodule
14547 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14548 
module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
14549 
parameter INIT = 32'h00000000;
14550 
output DPO;
14551 
output SPO;
14552 
input A0;
14553 
input A1;
14554 
input A2;
14555 
input A3;
14556 
input A4;
14557 
input D;
14558 
input DPRA0;
14559 
input DPRA1;
14560 
input DPRA2;
14561 
input DPRA3;
14562 
input DPRA4;
14563 
input WCLK;
14564 
input WE;
14565 
endmodule
14566 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14567 
module RAM32X1S_1 (O, A0, A1, A2, A3, A4, D, WCLK, WE);
14568 
parameter INIT = 32'h00000000;
14569 
output O;
14570 
input A0;
14571 
input A1;
14572 
input A2;
14573 
input A3;
14574 
input A4;
14575 
input D;
14576 
input WCLK;
14577 
input WE;
14578 
endmodule
14579 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14580 
module RAM32X1S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
14581 
parameter INIT = 32'h00000000;
14582 
output O;
14583 
input A0;
14584 
input A1;
14585 
input A2;
14586 
input A3;
14587 
input A4;
14588 
input D;
14589 
input WCLK;
14590 
input WE;
14591 
endmodule
14592 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14593 
module RAM32X2S (O0, O1, A0, A1, A2, A3, A4, D0, D1, WCLK, WE);
14594 
parameter INIT_00 = 32'h00000000;
14595 
parameter INIT_01 = 32'h00000000;
14596 
output O0;
14597 
output O1;
14598 
input A0;
14599 
input A1;
14600 
input A2;
14601 
input A3;
14602 
input A4;
14603 
input D0;
14604 
input D1;
14605 
input WCLK;
14606 
input WE;
14607 
endmodule
14608 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14609 
module RAM32X4S (O0, O1, O2, O3, A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE);
14610 
parameter INIT_00 = 32'h00000000;
14611 
parameter INIT_01 = 32'h00000000;
14612 
parameter INIT_02 = 32'h00000000;
14613 
parameter INIT_03 = 32'h00000000;
14614 
output O0;
14615 
output O1;
14616 
output O2;
14617 
output O3;
14618 
input A0;
14619 
input A1;
14620 
input A2;
14621 
input A3;
14622 
input A4;
14623 
input D0;
14624 
input D1;
14625 
input D2;
14626 
input D3;
14627 
input WCLK;
14628 
input WE;
14629 
endmodule
14630 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14631 
module RAM32X8S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
14632 
parameter INIT_00 = 32'h00000000;
14633 
parameter INIT_01 = 32'h00000000;
14634 
parameter INIT_02 = 32'h00000000;
14635 
parameter INIT_03 = 32'h00000000;
14636 
parameter INIT_04 = 32'h00000000;
14637 
parameter INIT_05 = 32'h00000000;
14638 
parameter INIT_06 = 32'h00000000;
14639 
parameter INIT_07 = 32'h00000000;
14640 
output [7:0] O;
14641 
input A0;
14642 
input A1;
14643 
input A2;
14644 
input A3;
14645 
input A4;
14646 
input [7:0] D;
14647 
input WCLK;
14648 
input WE;
14649 
endmodule
14650 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14651 
module RAM64M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);
14652 
parameter INIT_A = 64'h0000000000000000;
14653 
parameter INIT_B = 64'h0000000000000000;
14654 
parameter INIT_C = 64'h0000000000000000;
14655 
parameter INIT_D = 64'h0000000000000000;
14656 
output DOA;
14657 
output DOB;
14658 
output DOC;
14659 
output DOD;
14660 
input [5:0] ADDRA;
14661 
input [5:0] ADDRB;
14662 
input [5:0] ADDRC;
14663 
input [5:0] ADDRD;
14664 
input DIA;
14665 
input DIB;
14666 
input DIC;
14667 
input DID;
14668 
input WCLK;
14669 
input WE;
14670 
endmodule
14671 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14672 
module RAM64X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);
14673 
parameter INIT = 64'h0000000000000000;
14674 
output DPO;
14675 
output SPO;
14676 
input A0;
14677 
input A1;
14678 
input A2;
14679 
input A3;
14680 
input A4;
14681 
input A5;
14682 
input D;
14683 
input DPRA0;
14684 
input DPRA1;
14685 
input DPRA2;
14686 
input DPRA3;
14687 
input DPRA4;
14688 
input DPRA5;
14689 
input WCLK;
14690 
input WE;
14691 
endmodule
14692 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14693 
module RAM64X1D (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);
14694 
parameter INIT = 64'h0000000000000000;
14695 
output DPO;
14696 
output SPO;
14697 
input A0;
14698 
input A1;
14699 
input A2;
14700 
input A3;
14701 
input A4;
14702 
input A5;
14703 
input D;
14704 
input DPRA0;
14705 
input DPRA1;
14706 
input DPRA2;
14707 
input DPRA3;
14708 
input DPRA4;
14709 
input DPRA5;
14710 
input WCLK;
14711 
input WE;
14712 
endmodule
14713 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14714 
module RAM64X1S_1 (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE);
14715 
parameter INIT = 64'h0000000000000000;
14716 
output O;
14717 
input A0;
14718 
input A1;
14719 
input A2;
14720 
input A3;
14721 
input A4;
14722 
input A5;
14723 
input D;
14724 
input WCLK;
14725 
input WE;
14726 
endmodule
14727 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14728 
module RAM64X1S (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE);
14729 
parameter INIT = 64'h0000000000000000;
14730 
output O;
14731 
input A0;
14732 
input A1;
14733 
input A2;
14734 
input A3;
14735 
input A4;
14736 
input A5;
14737 
input D;
14738 
input WCLK;
14739 
input WE;
14740 
endmodule
14741 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14742 
module RAM64X2S (O0, O1, A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE);
14743 
parameter INIT_00 = 64'h0000000000000000;
14744 
parameter INIT_01 = 64'h0000000000000000;
14745 
output O0;
14746 
output O1;
14747 
input A0;
14748 
input A1;
14749 
input A2;
14750 
input A3;
14751 
input A4;
14752 
input A5;
14753 
input D0;
14754 
input D1;
14755 
input WCLK;
14756 
input WE;
14757 
endmodule
14758 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14759 
module RAMB16BWER (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB);
14760 
parameter integer DATA_WIDTH_A = 0;
14761 
parameter integer DATA_WIDTH_B = 0;
14762 
parameter integer DOA_REG = 0;
14763 
parameter integer DOB_REG = 0;
14764 
parameter INIT_A = 36'h0;
14765 
parameter INIT_B = 36'h0;
14766 
parameter RSTTYPE = "SYNC";
14767 
parameter SIM_COLLISION_CHECK = "ALL";
14768 
parameter SRVAL_A = 36'h0;
14769 
parameter SRVAL_B = 36'h0;
14770 
parameter WRITE_MODE_A = "WRITE_FIRST";
14771 
parameter WRITE_MODE_B = "WRITE_FIRST";
14772 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14773 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14774 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14775 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14776 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14777 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14778 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14779 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14780 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14781 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14782 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14783 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14784 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14785 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14786 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14787 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14788 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14789 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14790 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14791 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14792 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14793 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14794 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14795 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14796 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14797 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14798 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14799 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14800 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14801 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14802 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14803 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14804 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14805 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14806 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14807 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14808 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14809 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14810 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14811 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14812 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14813 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14814 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14815 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14816 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14817 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14818 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14819 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14820 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14821 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14822 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14823 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14824 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14825 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14826 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14827 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14828 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14829 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14830 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14831 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14832 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14833 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14834 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14835 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14836 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14837 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14838 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14839 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14840 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14841 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14842 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14843 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
14844 
output [31:0] DOA;
14845 
output [31:0] DOB;
14846 
output [3:0] DOPA;
14847 
output [3:0] DOPB;
14848 
input [13:0] ADDRA;
14849 
input [13:0] ADDRB;
14850 
input CLKA;
14851 
input CLKB;
14852 
input [31:0] DIA;
14853 
input [31:0] DIB;
14854 
input [3:0] DIPA;
14855 
input [3:0] DIPB;
14856 
input ENA;
14857 
input ENB;
14858 
input REGCEA;
14859 
input REGCEB;
14860 
input RSTA;
14861 
input RSTB;
14862 
input [3:0] WEA;
14863 
input [3:0] WEB;
14864 
endmodule
14865 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14866 
module RAMB16BWE_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
14867 
parameter INITP_00 = 256'h0;
14868 
parameter INITP_01 = 256'h0;
14869 
parameter INITP_02 = 256'h0;
14870 
parameter INITP_03 = 256'h0;
14871 
parameter INITP_04 = 256'h0;
14872 
parameter INITP_05 = 256'h0;
14873 
parameter INITP_06 = 256'h0;
14874 
parameter INITP_07 = 256'h0;
14875 
parameter INIT_00 = 256'h0;
14876 
parameter INIT_01 = 256'h0;
14877 
parameter INIT_02 = 256'h0;
14878 
parameter INIT_03 = 256'h0;
14879 
parameter INIT_04 = 256'h0;
14880 
parameter INIT_05 = 256'h0;
14881 
parameter INIT_06 = 256'h0;
14882 
parameter INIT_07 = 256'h0;
14883 
parameter INIT_08 = 256'h0;
14884 
parameter INIT_09 = 256'h0;
14885 
parameter INIT_0A = 256'h0;
14886 
parameter INIT_0B = 256'h0;
14887 
parameter INIT_0C = 256'h0;
14888 
parameter INIT_0D = 256'h0;
14889 
parameter INIT_0E = 256'h0;
14890 
parameter INIT_0F = 256'h0;
14891 
parameter INIT_10 = 256'h0;
14892 
parameter INIT_11 = 256'h0;
14893 
parameter INIT_12 = 256'h0;
14894 
parameter INIT_13 = 256'h0;
14895 
parameter INIT_14 = 256'h0;
14896 
parameter INIT_15 = 256'h0;
14897 
parameter INIT_16 = 256'h0;
14898 
parameter INIT_17 = 256'h0;
14899 
parameter INIT_18 = 256'h0;
14900 
parameter INIT_19 = 256'h0;
14901 
parameter INIT_1A = 256'h0;
14902 
parameter INIT_1B = 256'h0;
14903 
parameter INIT_1C = 256'h0;
14904 
parameter INIT_1D = 256'h0;
14905 
parameter INIT_1E = 256'h0;
14906 
parameter INIT_1F = 256'h0;
14907 
parameter INIT_20 = 256'h0;
14908 
parameter INIT_21 = 256'h0;
14909 
parameter INIT_22 = 256'h0;
14910 
parameter INIT_23 = 256'h0;
14911 
parameter INIT_24 = 256'h0;
14912 
parameter INIT_25 = 256'h0;
14913 
parameter INIT_26 = 256'h0;
14914 
parameter INIT_27 = 256'h0;
14915 
parameter INIT_28 = 256'h0;
14916 
parameter INIT_29 = 256'h0;
14917 
parameter INIT_2A = 256'h0;
14918 
parameter INIT_2B = 256'h0;
14919 
parameter INIT_2C = 256'h0;
14920 
parameter INIT_2D = 256'h0;
14921 
parameter INIT_2E = 256'h0;
14922 
parameter INIT_2F = 256'h0;
14923 
parameter INIT_30 = 256'h0;
14924 
parameter INIT_31 = 256'h0;
14925 
parameter INIT_32 = 256'h0;
14926 
parameter INIT_33 = 256'h0;
14927 
parameter INIT_34 = 256'h0;
14928 
parameter INIT_35 = 256'h0;
14929 
parameter INIT_36 = 256'h0;
14930 
parameter INIT_37 = 256'h0;
14931 
parameter INIT_38 = 256'h0;
14932 
parameter INIT_39 = 256'h0;
14933 
parameter INIT_3A = 256'h0;
14934 
parameter INIT_3B = 256'h0;
14935 
parameter INIT_3C = 256'h0;
14936 
parameter INIT_3D = 256'h0;
14937 
parameter INIT_3E = 256'h0;
14938 
parameter INIT_3F = 256'h0;
14939 
parameter INIT_A = 18'h0;
14940 
parameter INIT_B = 18'h0;
14941 
parameter SIM_COLLISION_CHECK = "ALL";
14942 
parameter SRVAL_A = 18'h0;
14943 
parameter SRVAL_B = 18'h0;
14944 
parameter WRITE_MODE_A = "WRITE_FIRST";
14945 
parameter WRITE_MODE_B = "WRITE_FIRST";
14946 
output [15:0] DOA;
14947 
output [15:0] DOB;
14948 
output [1:0] DOPA;
14949 
output [1:0] DOPB;
14950 
input [9:0] ADDRA;
14951 
input [9:0] ADDRB;
14952 
input CLKA;
14953 
input CLKB;
14954 
input [15:0] DIA;
14955 
input [15:0] DIB;
14956 
input [1:0] DIPA;
14957 
input [1:0] DIPB;
14958 
input ENA;
14959 
input ENB;
14960 
input SSRA;
14961 
input SSRB;
14962 
input [1:0] WEA;
14963 
input [1:0] WEB;
14964 
endmodule
14965 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
14966 
module RAMB16BWE_S18_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
14967 
parameter INITP_00 = 256'h0;
14968 
parameter INITP_01 = 256'h0;
14969 
parameter INITP_02 = 256'h0;
14970 
parameter INITP_03 = 256'h0;
14971 
parameter INITP_04 = 256'h0;
14972 
parameter INITP_05 = 256'h0;
14973 
parameter INITP_06 = 256'h0;
14974 
parameter INITP_07 = 256'h0;
14975 
parameter INIT_00 = 256'h0;
14976 
parameter INIT_01 = 256'h0;
14977 
parameter INIT_02 = 256'h0;
14978 
parameter INIT_03 = 256'h0;
14979 
parameter INIT_04 = 256'h0;
14980 
parameter INIT_05 = 256'h0;
14981 
parameter INIT_06 = 256'h0;
14982 
parameter INIT_07 = 256'h0;
14983 
parameter INIT_08 = 256'h0;
14984 
parameter INIT_09 = 256'h0;
14985 
parameter INIT_0A = 256'h0;
14986 
parameter INIT_0B = 256'h0;
14987 
parameter INIT_0C = 256'h0;
14988 
parameter INIT_0D = 256'h0;
14989 
parameter INIT_0E = 256'h0;
14990 
parameter INIT_0F = 256'h0;
14991 
parameter INIT_10 = 256'h0;
14992 
parameter INIT_11 = 256'h0;
14993 
parameter INIT_12 = 256'h0;
14994 
parameter INIT_13 = 256'h0;
14995 
parameter INIT_14 = 256'h0;
14996 
parameter INIT_15 = 256'h0;
14997 
parameter INIT_16 = 256'h0;
14998 
parameter INIT_17 = 256'h0;
14999 
parameter INIT_18 = 256'h0;
15000 
parameter INIT_19 = 256'h0;
15001 
parameter INIT_1A = 256'h0;
15002 
parameter INIT_1B = 256'h0;
15003 
parameter INIT_1C = 256'h0;
15004 
parameter INIT_1D = 256'h0;
15005 
parameter INIT_1E = 256'h0;
15006 
parameter INIT_1F = 256'h0;
15007 
parameter INIT_20 = 256'h0;
15008 
parameter INIT_21 = 256'h0;
15009 
parameter INIT_22 = 256'h0;
15010 
parameter INIT_23 = 256'h0;
15011 
parameter INIT_24 = 256'h0;
15012 
parameter INIT_25 = 256'h0;
15013 
parameter INIT_26 = 256'h0;
15014 
parameter INIT_27 = 256'h0;
15015 
parameter INIT_28 = 256'h0;
15016 
parameter INIT_29 = 256'h0;
15017 
parameter INIT_2A = 256'h0;
15018 
parameter INIT_2B = 256'h0;
15019 
parameter INIT_2C = 256'h0;
15020 
parameter INIT_2D = 256'h0;
15021 
parameter INIT_2E = 256'h0;
15022 
parameter INIT_2F = 256'h0;
15023 
parameter INIT_30 = 256'h0;
15024 
parameter INIT_31 = 256'h0;
15025 
parameter INIT_32 = 256'h0;
15026 
parameter INIT_33 = 256'h0;
15027 
parameter INIT_34 = 256'h0;
15028 
parameter INIT_35 = 256'h0;
15029 
parameter INIT_36 = 256'h0;
15030 
parameter INIT_37 = 256'h0;
15031 
parameter INIT_38 = 256'h0;
15032 
parameter INIT_39 = 256'h0;
15033 
parameter INIT_3A = 256'h0;
15034 
parameter INIT_3B = 256'h0;
15035 
parameter INIT_3C = 256'h0;
15036 
parameter INIT_3D = 256'h0;
15037 
parameter INIT_3E = 256'h0;
15038 
parameter INIT_3F = 256'h0;
15039 
parameter INIT_A = 18'h0;
15040 
parameter INIT_B = 9'h0;
15041 
parameter SIM_COLLISION_CHECK = "ALL";
15042 
parameter SRVAL_A = 18'h0;
15043 
parameter SRVAL_B = 9'h0;
15044 
parameter WRITE_MODE_A = "WRITE_FIRST";
15045 
parameter WRITE_MODE_B = "WRITE_FIRST";
15046 
output [15:0] DOA;
15047 
output [7:0] DOB;
15048 
output [1:0] DOPA;
15049 
output [0:0] DOPB;
15050 
input [9:0] ADDRA;
15051 
input [10:0] ADDRB;
15052 
input CLKA;
15053 
input CLKB;
15054 
input [15:0] DIA;
15055 
input [7:0] DIB;
15056 
input [1:0] DIPA;
15057 
input [0:0] DIPB;
15058 
input ENA;
15059 
input ENB;
15060 
input SSRA;
15061 
input SSRB;
15062 
input [1:0] WEA;
15063 
input WEB;
15064 
endmodule
15065 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15066 
module RAMB16BWE_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
15067 
parameter INIT = 18'h0;
15068 
parameter INITP_00 = 256'h0;
15069 
parameter INITP_01 = 256'h0;
15070 
parameter INITP_02 = 256'h0;
15071 
parameter INITP_03 = 256'h0;
15072 
parameter INITP_04 = 256'h0;
15073 
parameter INITP_05 = 256'h0;
15074 
parameter INITP_06 = 256'h0;
15075 
parameter INITP_07 = 256'h0;
15076 
parameter INIT_00 = 256'h0;
15077 
parameter INIT_01 = 256'h0;
15078 
parameter INIT_02 = 256'h0;
15079 
parameter INIT_03 = 256'h0;
15080 
parameter INIT_04 = 256'h0;
15081 
parameter INIT_05 = 256'h0;
15082 
parameter INIT_06 = 256'h0;
15083 
parameter INIT_07 = 256'h0;
15084 
parameter INIT_08 = 256'h0;
15085 
parameter INIT_09 = 256'h0;
15086 
parameter INIT_0A = 256'h0;
15087 
parameter INIT_0B = 256'h0;
15088 
parameter INIT_0C = 256'h0;
15089 
parameter INIT_0D = 256'h0;
15090 
parameter INIT_0E = 256'h0;
15091 
parameter INIT_0F = 256'h0;
15092 
parameter INIT_10 = 256'h0;
15093 
parameter INIT_11 = 256'h0;
15094 
parameter INIT_12 = 256'h0;
15095 
parameter INIT_13 = 256'h0;
15096 
parameter INIT_14 = 256'h0;
15097 
parameter INIT_15 = 256'h0;
15098 
parameter INIT_16 = 256'h0;
15099 
parameter INIT_17 = 256'h0;
15100 
parameter INIT_18 = 256'h0;
15101 
parameter INIT_19 = 256'h0;
15102 
parameter INIT_1A = 256'h0;
15103 
parameter INIT_1B = 256'h0;
15104 
parameter INIT_1C = 256'h0;
15105 
parameter INIT_1D = 256'h0;
15106 
parameter INIT_1E = 256'h0;
15107 
parameter INIT_1F = 256'h0;
15108 
parameter INIT_20 = 256'h0;
15109 
parameter INIT_21 = 256'h0;
15110 
parameter INIT_22 = 256'h0;
15111 
parameter INIT_23 = 256'h0;
15112 
parameter INIT_24 = 256'h0;
15113 
parameter INIT_25 = 256'h0;
15114 
parameter INIT_26 = 256'h0;
15115 
parameter INIT_27 = 256'h0;
15116 
parameter INIT_28 = 256'h0;
15117 
parameter INIT_29 = 256'h0;
15118 
parameter INIT_2A = 256'h0;
15119 
parameter INIT_2B = 256'h0;
15120 
parameter INIT_2C = 256'h0;
15121 
parameter INIT_2D = 256'h0;
15122 
parameter INIT_2E = 256'h0;
15123 
parameter INIT_2F = 256'h0;
15124 
parameter INIT_30 = 256'h0;
15125 
parameter INIT_31 = 256'h0;
15126 
parameter INIT_32 = 256'h0;
15127 
parameter INIT_33 = 256'h0;
15128 
parameter INIT_34 = 256'h0;
15129 
parameter INIT_35 = 256'h0;
15130 
parameter INIT_36 = 256'h0;
15131 
parameter INIT_37 = 256'h0;
15132 
parameter INIT_38 = 256'h0;
15133 
parameter INIT_39 = 256'h0;
15134 
parameter INIT_3A = 256'h0;
15135 
parameter INIT_3B = 256'h0;
15136 
parameter INIT_3C = 256'h0;
15137 
parameter INIT_3D = 256'h0;
15138 
parameter INIT_3E = 256'h0;
15139 
parameter INIT_3F = 256'h0;
15140 
parameter SRVAL = 18'h0;
15141 
parameter WRITE_MODE = "WRITE_FIRST";
15142 
output [15:0] DO;
15143 
output [1:0] DOP;
15144 
input [9:0] ADDR;
15145 
input CLK;
15146 
input [15:0] DI;
15147 
input [1:0] DIP;
15148 
input EN;
15149 
input SSR;
15150 
input [1:0] WE;
15151 
endmodule
15152 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15153 
module RAMB16BWE_S36_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15154 
parameter INITP_00 = 256'h0;
15155 
parameter INITP_01 = 256'h0;
15156 
parameter INITP_02 = 256'h0;
15157 
parameter INITP_03 = 256'h0;
15158 
parameter INITP_04 = 256'h0;
15159 
parameter INITP_05 = 256'h0;
15160 
parameter INITP_06 = 256'h0;
15161 
parameter INITP_07 = 256'h0;
15162 
parameter INIT_00 = 256'h0;
15163 
parameter INIT_01 = 256'h0;
15164 
parameter INIT_02 = 256'h0;
15165 
parameter INIT_03 = 256'h0;
15166 
parameter INIT_04 = 256'h0;
15167 
parameter INIT_05 = 256'h0;
15168 
parameter INIT_06 = 256'h0;
15169 
parameter INIT_07 = 256'h0;
15170 
parameter INIT_08 = 256'h0;
15171 
parameter INIT_09 = 256'h0;
15172 
parameter INIT_0A = 256'h0;
15173 
parameter INIT_0B = 256'h0;
15174 
parameter INIT_0C = 256'h0;
15175 
parameter INIT_0D = 256'h0;
15176 
parameter INIT_0E = 256'h0;
15177 
parameter INIT_0F = 256'h0;
15178 
parameter INIT_10 = 256'h0;
15179 
parameter INIT_11 = 256'h0;
15180 
parameter INIT_12 = 256'h0;
15181 
parameter INIT_13 = 256'h0;
15182 
parameter INIT_14 = 256'h0;
15183 
parameter INIT_15 = 256'h0;
15184 
parameter INIT_16 = 256'h0;
15185 
parameter INIT_17 = 256'h0;
15186 
parameter INIT_18 = 256'h0;
15187 
parameter INIT_19 = 256'h0;
15188 
parameter INIT_1A = 256'h0;
15189 
parameter INIT_1B = 256'h0;
15190 
parameter INIT_1C = 256'h0;
15191 
parameter INIT_1D = 256'h0;
15192 
parameter INIT_1E = 256'h0;
15193 
parameter INIT_1F = 256'h0;
15194 
parameter INIT_20 = 256'h0;
15195 
parameter INIT_21 = 256'h0;
15196 
parameter INIT_22 = 256'h0;
15197 
parameter INIT_23 = 256'h0;
15198 
parameter INIT_24 = 256'h0;
15199 
parameter INIT_25 = 256'h0;
15200 
parameter INIT_26 = 256'h0;
15201 
parameter INIT_27 = 256'h0;
15202 
parameter INIT_28 = 256'h0;
15203 
parameter INIT_29 = 256'h0;
15204 
parameter INIT_2A = 256'h0;
15205 
parameter INIT_2B = 256'h0;
15206 
parameter INIT_2C = 256'h0;
15207 
parameter INIT_2D = 256'h0;
15208 
parameter INIT_2E = 256'h0;
15209 
parameter INIT_2F = 256'h0;
15210 
parameter INIT_30 = 256'h0;
15211 
parameter INIT_31 = 256'h0;
15212 
parameter INIT_32 = 256'h0;
15213 
parameter INIT_33 = 256'h0;
15214 
parameter INIT_34 = 256'h0;
15215 
parameter INIT_35 = 256'h0;
15216 
parameter INIT_36 = 256'h0;
15217 
parameter INIT_37 = 256'h0;
15218 
parameter INIT_38 = 256'h0;
15219 
parameter INIT_39 = 256'h0;
15220 
parameter INIT_3A = 256'h0;
15221 
parameter INIT_3B = 256'h0;
15222 
parameter INIT_3C = 256'h0;
15223 
parameter INIT_3D = 256'h0;
15224 
parameter INIT_3E = 256'h0;
15225 
parameter INIT_3F = 256'h0;
15226 
parameter INIT_A = 36'h0;
15227 
parameter INIT_B = 18'h0;
15228 
parameter SIM_COLLISION_CHECK = "ALL";
15229 
parameter SRVAL_A = 36'h0;
15230 
parameter SRVAL_B = 18'h0;
15231 
parameter WRITE_MODE_A = "WRITE_FIRST";
15232 
parameter WRITE_MODE_B = "WRITE_FIRST";
15233 
output [31:0] DOA;
15234 
output [15:0] DOB;
15235 
output [3:0] DOPA;
15236 
output [1:0] DOPB;
15237 
input [8:0] ADDRA;
15238 
input [9:0] ADDRB;
15239 
input CLKA;
15240 
input CLKB;
15241 
input [31:0] DIA;
15242 
input [15:0] DIB;
15243 
input [3:0] DIPA;
15244 
input [1:0] DIPB;
15245 
input ENA;
15246 
input ENB;
15247 
input SSRA;
15248 
input SSRB;
15249 
input [3:0] WEA;
15250 
input [1:0] WEB;
15251 
endmodule
15252 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15253 
module RAMB16BWE_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15254 
parameter INITP_00 = 256'h0;
15255 
parameter INITP_01 = 256'h0;
15256 
parameter INITP_02 = 256'h0;
15257 
parameter INITP_03 = 256'h0;
15258 
parameter INITP_04 = 256'h0;
15259 
parameter INITP_05 = 256'h0;
15260 
parameter INITP_06 = 256'h0;
15261 
parameter INITP_07 = 256'h0;
15262 
parameter INIT_00 = 256'h0;
15263 
parameter INIT_01 = 256'h0;
15264 
parameter INIT_02 = 256'h0;
15265 
parameter INIT_03 = 256'h0;
15266 
parameter INIT_04 = 256'h0;
15267 
parameter INIT_05 = 256'h0;
15268 
parameter INIT_06 = 256'h0;
15269 
parameter INIT_07 = 256'h0;
15270 
parameter INIT_08 = 256'h0;
15271 
parameter INIT_09 = 256'h0;
15272 
parameter INIT_0A = 256'h0;
15273 
parameter INIT_0B = 256'h0;
15274 
parameter INIT_0C = 256'h0;
15275 
parameter INIT_0D = 256'h0;
15276 
parameter INIT_0E = 256'h0;
15277 
parameter INIT_0F = 256'h0;
15278 
parameter INIT_10 = 256'h0;
15279 
parameter INIT_11 = 256'h0;
15280 
parameter INIT_12 = 256'h0;
15281 
parameter INIT_13 = 256'h0;
15282 
parameter INIT_14 = 256'h0;
15283 
parameter INIT_15 = 256'h0;
15284 
parameter INIT_16 = 256'h0;
15285 
parameter INIT_17 = 256'h0;
15286 
parameter INIT_18 = 256'h0;
15287 
parameter INIT_19 = 256'h0;
15288 
parameter INIT_1A = 256'h0;
15289 
parameter INIT_1B = 256'h0;
15290 
parameter INIT_1C = 256'h0;
15291 
parameter INIT_1D = 256'h0;
15292 
parameter INIT_1E = 256'h0;
15293 
parameter INIT_1F = 256'h0;
15294 
parameter INIT_20 = 256'h0;
15295 
parameter INIT_21 = 256'h0;
15296 
parameter INIT_22 = 256'h0;
15297 
parameter INIT_23 = 256'h0;
15298 
parameter INIT_24 = 256'h0;
15299 
parameter INIT_25 = 256'h0;
15300 
parameter INIT_26 = 256'h0;
15301 
parameter INIT_27 = 256'h0;
15302 
parameter INIT_28 = 256'h0;
15303 
parameter INIT_29 = 256'h0;
15304 
parameter INIT_2A = 256'h0;
15305 
parameter INIT_2B = 256'h0;
15306 
parameter INIT_2C = 256'h0;
15307 
parameter INIT_2D = 256'h0;
15308 
parameter INIT_2E = 256'h0;
15309 
parameter INIT_2F = 256'h0;
15310 
parameter INIT_30 = 256'h0;
15311 
parameter INIT_31 = 256'h0;
15312 
parameter INIT_32 = 256'h0;
15313 
parameter INIT_33 = 256'h0;
15314 
parameter INIT_34 = 256'h0;
15315 
parameter INIT_35 = 256'h0;
15316 
parameter INIT_36 = 256'h0;
15317 
parameter INIT_37 = 256'h0;
15318 
parameter INIT_38 = 256'h0;
15319 
parameter INIT_39 = 256'h0;
15320 
parameter INIT_3A = 256'h0;
15321 
parameter INIT_3B = 256'h0;
15322 
parameter INIT_3C = 256'h0;
15323 
parameter INIT_3D = 256'h0;
15324 
parameter INIT_3E = 256'h0;
15325 
parameter INIT_3F = 256'h0;
15326 
parameter INIT_A = 36'h0;
15327 
parameter INIT_B = 36'h0;
15328 
parameter SIM_COLLISION_CHECK = "ALL";
15329 
parameter SRVAL_A = 36'h0;
15330 
parameter SRVAL_B = 36'h0;
15331 
parameter WRITE_MODE_A = "WRITE_FIRST";
15332 
parameter WRITE_MODE_B = "WRITE_FIRST";
15333 
output [31:0] DOA;
15334 
output [31:0] DOB;
15335 
output [3:0] DOPA;
15336 
output [3:0] DOPB;
15337 
input [8:0] ADDRA;
15338 
input [8:0] ADDRB;
15339 
input CLKA;
15340 
input CLKB;
15341 
input [31:0] DIA;
15342 
input [31:0] DIB;
15343 
input [3:0] DIPA;
15344 
input [3:0] DIPB;
15345 
input ENA;
15346 
input ENB;
15347 
input SSRA;
15348 
input SSRB;
15349 
input [3:0] WEA;
15350 
input [3:0] WEB;
15351 
endmodule
15352 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15353 
module RAMB16BWE_S36_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15354 
parameter INITP_00 = 256'h0;
15355 
parameter INITP_01 = 256'h0;
15356 
parameter INITP_02 = 256'h0;
15357 
parameter INITP_03 = 256'h0;
15358 
parameter INITP_04 = 256'h0;
15359 
parameter INITP_05 = 256'h0;
15360 
parameter INITP_06 = 256'h0;
15361 
parameter INITP_07 = 256'h0;
15362 
parameter INIT_00 = 256'h0;
15363 
parameter INIT_01 = 256'h0;
15364 
parameter INIT_02 = 256'h0;
15365 
parameter INIT_03 = 256'h0;
15366 
parameter INIT_04 = 256'h0;
15367 
parameter INIT_05 = 256'h0;
15368 
parameter INIT_06 = 256'h0;
15369 
parameter INIT_07 = 256'h0;
15370 
parameter INIT_08 = 256'h0;
15371 
parameter INIT_09 = 256'h0;
15372 
parameter INIT_0A = 256'h0;
15373 
parameter INIT_0B = 256'h0;
15374 
parameter INIT_0C = 256'h0;
15375 
parameter INIT_0D = 256'h0;
15376 
parameter INIT_0E = 256'h0;
15377 
parameter INIT_0F = 256'h0;
15378 
parameter INIT_10 = 256'h0;
15379 
parameter INIT_11 = 256'h0;
15380 
parameter INIT_12 = 256'h0;
15381 
parameter INIT_13 = 256'h0;
15382 
parameter INIT_14 = 256'h0;
15383 
parameter INIT_15 = 256'h0;
15384 
parameter INIT_16 = 256'h0;
15385 
parameter INIT_17 = 256'h0;
15386 
parameter INIT_18 = 256'h0;
15387 
parameter INIT_19 = 256'h0;
15388 
parameter INIT_1A = 256'h0;
15389 
parameter INIT_1B = 256'h0;
15390 
parameter INIT_1C = 256'h0;
15391 
parameter INIT_1D = 256'h0;
15392 
parameter INIT_1E = 256'h0;
15393 
parameter INIT_1F = 256'h0;
15394 
parameter INIT_20 = 256'h0;
15395 
parameter INIT_21 = 256'h0;
15396 
parameter INIT_22 = 256'h0;
15397 
parameter INIT_23 = 256'h0;
15398 
parameter INIT_24 = 256'h0;
15399 
parameter INIT_25 = 256'h0;
15400 
parameter INIT_26 = 256'h0;
15401 
parameter INIT_27 = 256'h0;
15402 
parameter INIT_28 = 256'h0;
15403 
parameter INIT_29 = 256'h0;
15404 
parameter INIT_2A = 256'h0;
15405 
parameter INIT_2B = 256'h0;
15406 
parameter INIT_2C = 256'h0;
15407 
parameter INIT_2D = 256'h0;
15408 
parameter INIT_2E = 256'h0;
15409 
parameter INIT_2F = 256'h0;
15410 
parameter INIT_30 = 256'h0;
15411 
parameter INIT_31 = 256'h0;
15412 
parameter INIT_32 = 256'h0;
15413 
parameter INIT_33 = 256'h0;
15414 
parameter INIT_34 = 256'h0;
15415 
parameter INIT_35 = 256'h0;
15416 
parameter INIT_36 = 256'h0;
15417 
parameter INIT_37 = 256'h0;
15418 
parameter INIT_38 = 256'h0;
15419 
parameter INIT_39 = 256'h0;
15420 
parameter INIT_3A = 256'h0;
15421 
parameter INIT_3B = 256'h0;
15422 
parameter INIT_3C = 256'h0;
15423 
parameter INIT_3D = 256'h0;
15424 
parameter INIT_3E = 256'h0;
15425 
parameter INIT_3F = 256'h0;
15426 
parameter INIT_A = 36'h0;
15427 
parameter INIT_B = 9'h0;
15428 
parameter SIM_COLLISION_CHECK = "ALL";
15429 
parameter SRVAL_A = 36'h0;
15430 
parameter SRVAL_B = 9'h0;
15431 
parameter WRITE_MODE_A = "WRITE_FIRST";
15432 
parameter WRITE_MODE_B = "WRITE_FIRST";
15433 
output [31:0] DOA;
15434 
output [7:0] DOB;
15435 
output [3:0] DOPA;
15436 
output [0:0] DOPB;
15437 
input [8:0] ADDRA;
15438 
input [10:0] ADDRB;
15439 
input CLKA;
15440 
input CLKB;
15441 
input [31:0] DIA;
15442 
input [7:0] DIB;
15443 
input [3:0] DIPA;
15444 
input [0:0] DIPB;
15445 
input ENA;
15446 
input ENB;
15447 
input SSRA;
15448 
input SSRB;
15449 
input [3:0] WEA;
15450 
input WEB;
15451 
endmodule
15452 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15453 
module RAMB16BWE_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
15454 
parameter INIT = 36'h0;
15455 
parameter INITP_00 = 256'h0;
15456 
parameter INITP_01 = 256'h0;
15457 
parameter INITP_02 = 256'h0;
15458 
parameter INITP_03 = 256'h0;
15459 
parameter INITP_04 = 256'h0;
15460 
parameter INITP_05 = 256'h0;
15461 
parameter INITP_06 = 256'h0;
15462 
parameter INITP_07 = 256'h0;
15463 
parameter INIT_00 = 256'h0;
15464 
parameter INIT_01 = 256'h0;
15465 
parameter INIT_02 = 256'h0;
15466 
parameter INIT_03 = 256'h0;
15467 
parameter INIT_04 = 256'h0;
15468 
parameter INIT_05 = 256'h0;
15469 
parameter INIT_06 = 256'h0;
15470 
parameter INIT_07 = 256'h0;
15471 
parameter INIT_08 = 256'h0;
15472 
parameter INIT_09 = 256'h0;
15473 
parameter INIT_0A = 256'h0;
15474 
parameter INIT_0B = 256'h0;
15475 
parameter INIT_0C = 256'h0;
15476 
parameter INIT_0D = 256'h0;
15477 
parameter INIT_0E = 256'h0;
15478 
parameter INIT_0F = 256'h0;
15479 
parameter INIT_10 = 256'h0;
15480 
parameter INIT_11 = 256'h0;
15481 
parameter INIT_12 = 256'h0;
15482 
parameter INIT_13 = 256'h0;
15483 
parameter INIT_14 = 256'h0;
15484 
parameter INIT_15 = 256'h0;
15485 
parameter INIT_16 = 256'h0;
15486 
parameter INIT_17 = 256'h0;
15487 
parameter INIT_18 = 256'h0;
15488 
parameter INIT_19 = 256'h0;
15489 
parameter INIT_1A = 256'h0;
15490 
parameter INIT_1B = 256'h0;
15491 
parameter INIT_1C = 256'h0;
15492 
parameter INIT_1D = 256'h0;
15493 
parameter INIT_1E = 256'h0;
15494 
parameter INIT_1F = 256'h0;
15495 
parameter INIT_20 = 256'h0;
15496 
parameter INIT_21 = 256'h0;
15497 
parameter INIT_22 = 256'h0;
15498 
parameter INIT_23 = 256'h0;
15499 
parameter INIT_24 = 256'h0;
15500 
parameter INIT_25 = 256'h0;
15501 
parameter INIT_26 = 256'h0;
15502 
parameter INIT_27 = 256'h0;
15503 
parameter INIT_28 = 256'h0;
15504 
parameter INIT_29 = 256'h0;
15505 
parameter INIT_2A = 256'h0;
15506 
parameter INIT_2B = 256'h0;
15507 
parameter INIT_2C = 256'h0;
15508 
parameter INIT_2D = 256'h0;
15509 
parameter INIT_2E = 256'h0;
15510 
parameter INIT_2F = 256'h0;
15511 
parameter INIT_30 = 256'h0;
15512 
parameter INIT_31 = 256'h0;
15513 
parameter INIT_32 = 256'h0;
15514 
parameter INIT_33 = 256'h0;
15515 
parameter INIT_34 = 256'h0;
15516 
parameter INIT_35 = 256'h0;
15517 
parameter INIT_36 = 256'h0;
15518 
parameter INIT_37 = 256'h0;
15519 
parameter INIT_38 = 256'h0;
15520 
parameter INIT_39 = 256'h0;
15521 
parameter INIT_3A = 256'h0;
15522 
parameter INIT_3B = 256'h0;
15523 
parameter INIT_3C = 256'h0;
15524 
parameter INIT_3D = 256'h0;
15525 
parameter INIT_3E = 256'h0;
15526 
parameter INIT_3F = 256'h0;
15527 
parameter SRVAL = 36'h0;
15528 
parameter WRITE_MODE = "WRITE_FIRST";
15529 
output [31:0] DO;
15530 
output [3:0] DOP;
15531 
input [8:0] ADDR;
15532 
input CLK;
15533 
input [31:0] DI;
15534 
input [3:0] DIP;
15535 
input EN;
15536 
input SSR;
15537 
input [3:0] WE;
15538 
endmodule
15539 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15540 
module RAMB16BWE (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15541 
parameter integer DATA_WIDTH_A = 0;
15542 
parameter integer DATA_WIDTH_B = 0;
15543 
parameter INIT_A = 36'h0;
15544 
parameter INIT_B = 36'h0;
15545 
parameter SIM_COLLISION_CHECK = "ALL";
15546 
parameter SRVAL_A = 36'h0;
15547 
parameter SRVAL_B = 36'h0;
15548 
parameter WRITE_MODE_A = "WRITE_FIRST";
15549 
parameter WRITE_MODE_B = "WRITE_FIRST";
15550 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15551 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15552 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15553 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15554 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15555 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15556 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15557 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15558 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15559 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15560 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15561 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15562 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15563 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15564 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15565 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15566 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15567 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15568 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15569 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15570 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15571 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15572 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15573 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15574 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15575 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15576 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15577 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15578 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15579 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15580 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15581 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15582 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15583 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15584 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15585 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15586 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15587 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15588 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15589 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15590 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15591 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15592 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15593 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15594 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15595 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15596 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15597 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15598 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15599 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15600 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15601 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15602 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15603 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15604 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15605 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15606 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15607 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15608 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15609 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15610 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15611 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15612 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15613 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15614 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15615 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15616 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15617 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15618 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15619 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15620 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15621 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15622 
output [31:0] DOA;
15623 
output [31:0] DOB;
15624 
output [3:0] DOPA;
15625 
output [3:0] DOPB;
15626 
input [13:0] ADDRA;
15627 
input [13:0] ADDRB;
15628 
input CLKA;
15629 
input CLKB;
15630 
input [31:0] DIA;
15631 
input [31:0] DIB;
15632 
input [3:0] DIPA;
15633 
input [3:0] DIPB;
15634 
input ENA;
15635 
input ENB;
15636 
input SSRA;
15637 
input SSRB;
15638 
input [3:0] WEA;
15639 
input [3:0] WEB;
15640 
endmodule
15641 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15642 
module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15643 
parameter INIT_A = 18'h0;
15644 
parameter INIT_B = 18'h0;
15645 
parameter SRVAL_A = 18'h0;
15646 
parameter SRVAL_B = 18'h0;
15647 
parameter WRITE_MODE_A = "WRITE_FIRST";
15648 
parameter WRITE_MODE_B = "WRITE_FIRST";
15649 
parameter SIM_COLLISION_CHECK = "ALL";
15650 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15651 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15652 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15653 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15654 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15655 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15656 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15657 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15658 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15659 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15660 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15661 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15662 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15663 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15664 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15665 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15666 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15667 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15668 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15669 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15670 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15671 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15672 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15673 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15674 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15675 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15676 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15677 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15678 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15679 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15680 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15681 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15682 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15683 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15684 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15685 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15686 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15687 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15688 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15689 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15690 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15691 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15692 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15693 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15694 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15695 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15696 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15697 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15698 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15699 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15700 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15701 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15702 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15703 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15704 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15705 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15706 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15707 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15708 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15709 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15710 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15711 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15712 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15713 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15714 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15715 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15716 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15717 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15718 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15719 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15720 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15721 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15722 
output [15:0] DOA;
15723 
output [15:0] DOB;
15724 
output [1:0] DOPA;
15725 
output [1:0] DOPB;
15726 
input [9:0] ADDRA;
15727 
input [9:0] ADDRB;
15728 
input CLKA;
15729 
input CLKB;
15730 
input [15:0] DIA;
15731 
input [15:0] DIB;
15732 
input [1:0] DIPA;
15733 
input [1:0] DIPB;
15734 
input ENA;
15735 
input ENB;
15736 
input SSRA;
15737 
input SSRB;
15738 
input WEA;
15739 
input WEB;
15740 
endmodule
15741 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15742 
module RAMB16_S18_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15743 
parameter INIT_A = 18'h0;
15744 
parameter INIT_B = 36'h0;
15745 
parameter SRVAL_A = 18'h0;
15746 
parameter SRVAL_B = 36'h0;
15747 
parameter WRITE_MODE_A = "WRITE_FIRST";
15748 
parameter WRITE_MODE_B = "WRITE_FIRST";
15749 
parameter SIM_COLLISION_CHECK = "ALL";
15750 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15751 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15752 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15753 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15754 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15755 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15756 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15757 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15758 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15759 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15760 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15761 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15762 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15763 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15764 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15765 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15766 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15767 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15768 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15769 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15770 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15771 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15772 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15773 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15774 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15775 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15776 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15777 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15778 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15779 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15780 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15781 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15782 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15783 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15784 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15785 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15786 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15787 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15788 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15789 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15790 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15791 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15792 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15793 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15794 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15795 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15796 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15797 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15798 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15799 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15800 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15801 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15802 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15803 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15804 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15805 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15806 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15807 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15808 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15809 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15810 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15811 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15812 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15813 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15814 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15815 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15816 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15817 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15818 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15819 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15820 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15821 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15822 
output [15:0] DOA;
15823 
output [31:0] DOB;
15824 
output [1:0] DOPA;
15825 
output [3:0] DOPB;
15826 
input [9:0] ADDRA;
15827 
input [8:0] ADDRB;
15828 
input CLKA;
15829 
input CLKB;
15830 
input [15:0] DIA;
15831 
input [31:0] DIB;
15832 
input [1:0] DIPA;
15833 
input [3:0] DIPB;
15834 
input ENA;
15835 
input ENB;
15836 
input SSRA;
15837 
input SSRB;
15838 
input WEA;
15839 
input WEB;
15840 
endmodule
15841 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15842 
module RAMB16_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
15843 
parameter INIT = 18'h0;
15844 
parameter SRVAL = 18'h0;
15845 
parameter WRITE_MODE = "WRITE_FIRST";
15846 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15847 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15848 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15849 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15850 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15851 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15852 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15853 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15854 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15855 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15856 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15857 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15858 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15859 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15860 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15861 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15862 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15863 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15864 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15865 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15866 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15867 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15868 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15869 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15870 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15871 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15872 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15873 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15874 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15875 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15876 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15877 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15878 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15879 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15880 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15881 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15882 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15883 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15884 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15885 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15886 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15887 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15888 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15889 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15890 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15891 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15892 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15893 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15894 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15895 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15896 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15897 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15898 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15899 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15900 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15901 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15902 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15903 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15904 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15905 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15906 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15907 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15908 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15909 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15910 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15911 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15912 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15913 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15914 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15915 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15916 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15917 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15918 
output [15:0] DO;
15919 
output [1:0] DOP;
15920 
input [9:0] ADDR;
15921 
input CLK;
15922 
input [15:0] DI;
15923 
input [1:0] DIP;
15924 
input EN;
15925 
input SSR;
15926 
input WE;
15927 
endmodule
15928 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
15929 
module RAMB16_S1_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
15930 
parameter INIT_A = 1'h0;
15931 
parameter INIT_B = 18'h0;
15932 
parameter SRVAL_A = 1'h0;
15933 
parameter SRVAL_B = 18'h0;
15934 
parameter WRITE_MODE_A = "WRITE_FIRST";
15935 
parameter WRITE_MODE_B = "WRITE_FIRST";
15936 
parameter SIM_COLLISION_CHECK = "ALL";
15937 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15938 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15939 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15940 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15941 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15942 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15943 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15944 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15945 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15946 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15947 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15948 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15949 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15950 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15951 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15952 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15953 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15954 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15955 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15956 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15957 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15958 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15959 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15960 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15961 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15962 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15963 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15964 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15965 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15966 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15967 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15968 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15969 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15970 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15971 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15972 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15973 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15974 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15975 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15976 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15977 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15978 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15979 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15980 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15981 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15982 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15983 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15984 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15985 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15986 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15987 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15988 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15989 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15990 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15991 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15992 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15993 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15994 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15995 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15996 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15997 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15998 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
15999 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16000 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16001 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16002 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16003 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16004 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16005 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16006 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16007 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16008 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16009 
output [0:0] DOA;
16010 
output [15:0] DOB;
16011 
output [1:0] DOPB;
16012 
input [13:0] ADDRA;
16013 
input [9:0] ADDRB;
16014 
input CLKA;
16015 
input CLKB;
16016 
input [0:0] DIA;
16017 
input [15:0] DIB;
16018 
input [1:0] DIPB;
16019 
input ENA;
16020 
input ENB;
16021 
input SSRA;
16022 
input SSRB;
16023 
input WEA;
16024 
input WEB;
16025 
endmodule
16026 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16027 
module RAMB16_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16028 
parameter INIT_A = 1'h0;
16029 
parameter INIT_B = 1'h0;
16030 
parameter SRVAL_A = 1'h0;
16031 
parameter SRVAL_B = 1'h0;
16032 
parameter WRITE_MODE_A = "WRITE_FIRST";
16033 
parameter WRITE_MODE_B = "WRITE_FIRST";
16034 
parameter SIM_COLLISION_CHECK = "ALL";
16035 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16036 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16037 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16038 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16039 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16040 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16041 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16042 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16043 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16044 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16045 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16046 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16047 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16048 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16049 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16050 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16051 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16052 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16053 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16054 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16055 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16056 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16057 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16058 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16059 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16060 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16061 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16062 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16063 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16064 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16065 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16066 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16067 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16068 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16069 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16070 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16071 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16072 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16073 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16074 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16075 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16076 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16077 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16078 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16079 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16080 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16081 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16082 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16083 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16084 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16085 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16086 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16087 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16088 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16089 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16090 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16091 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16092 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16093 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16094 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16095 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16096 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16097 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16098 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16099 
output [0:0] DOA;
16100 
output [0:0] DOB;
16101 
input [13:0] ADDRA;
16102 
input [13:0] ADDRB;
16103 
input CLKA;
16104 
input CLKB;
16105 
input [0:0] DIA;
16106 
input [0:0] DIB;
16107 
input ENA;
16108 
input ENB;
16109 
input SSRA;
16110 
input SSRB;
16111 
input WEA;
16112 
input WEB;
16113 
endmodule
16114 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16115 
module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16116 
parameter INIT_A = 1'h0;
16117 
parameter INIT_B = 2'h0;
16118 
parameter SRVAL_A = 1'h0;
16119 
parameter SRVAL_B = 2'h0;
16120 
parameter WRITE_MODE_A = "WRITE_FIRST";
16121 
parameter WRITE_MODE_B = "WRITE_FIRST";
16122 
parameter SIM_COLLISION_CHECK = "ALL";
16123 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16124 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16125 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16126 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16127 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16128 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16129 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16130 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16131 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16132 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16133 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16134 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16135 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16136 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16137 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16138 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16139 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16140 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16141 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16142 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16143 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16144 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16145 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16146 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16147 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16148 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16149 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16150 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16151 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16152 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16153 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16154 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16155 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16156 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16157 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16158 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16159 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16160 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16161 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16162 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16163 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16164 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16165 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16166 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16167 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16168 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16169 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16170 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16171 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16172 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16173 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16174 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16175 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16176 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16177 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16178 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16179 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16180 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16181 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16182 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16183 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16184 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16185 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16186 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16187 
output [0:0] DOA;
16188 
output [1:0] DOB;
16189 
input [13:0] ADDRA;
16190 
input [12:0] ADDRB;
16191 
input CLKA;
16192 
input CLKB;
16193 
input [0:0] DIA;
16194 
input [1:0] DIB;
16195 
input ENA;
16196 
input ENB;
16197 
input SSRA;
16198 
input SSRB;
16199 
input WEA;
16200 
input WEB;
16201 
endmodule
16202 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16203 
module RAMB16_S1_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16204 
parameter INIT_A = 1'h0;
16205 
parameter INIT_B = 36'h0;
16206 
parameter SRVAL_A = 1'h0;
16207 
parameter SRVAL_B = 36'h0;
16208 
parameter WRITE_MODE_A = "WRITE_FIRST";
16209 
parameter WRITE_MODE_B = "WRITE_FIRST";
16210 
parameter SIM_COLLISION_CHECK = "ALL";
16211 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16212 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16213 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16214 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16215 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16216 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16217 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16218 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16219 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16220 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16221 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16222 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16223 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16224 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16225 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16226 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16227 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16228 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16229 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16230 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16231 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16232 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16233 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16234 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16235 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16236 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16237 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16238 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16239 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16240 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16241 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16242 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16243 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16244 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16245 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16246 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16247 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16248 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16249 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16250 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16251 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16252 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16253 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16254 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16255 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16256 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16257 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16258 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16259 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16260 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16261 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16262 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16263 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16264 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16265 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16266 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16267 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16268 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16269 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16270 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16271 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16272 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16273 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16274 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16275 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16276 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16277 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16278 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16279 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16280 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16281 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16282 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16283 
output [0:0] DOA;
16284 
output [31:0] DOB;
16285 
output [3:0] DOPB;
16286 
input [13:0] ADDRA;
16287 
input [8:0] ADDRB;
16288 
input CLKA;
16289 
input CLKB;
16290 
input [0:0] DIA;
16291 
input [31:0] DIB;
16292 
input [3:0] DIPB;
16293 
input ENA;
16294 
input ENB;
16295 
input SSRA;
16296 
input SSRB;
16297 
input WEA;
16298 
input WEB;
16299 
endmodule
16300 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16301 
module RAMB16_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16302 
parameter INIT_A = 1'h0;
16303 
parameter INIT_B = 4'h0;
16304 
parameter SRVAL_A = 1'h0;
16305 
parameter SRVAL_B = 4'h0;
16306 
parameter WRITE_MODE_A = "WRITE_FIRST";
16307 
parameter WRITE_MODE_B = "WRITE_FIRST";
16308 
parameter SIM_COLLISION_CHECK = "ALL";
16309 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16310 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16311 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16312 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16313 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16314 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16315 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16316 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16317 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16318 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16319 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16320 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16321 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16322 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16323 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16324 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16325 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16326 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16327 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16328 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16329 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16330 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16331 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16332 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16333 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16334 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16335 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16336 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16337 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16338 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16339 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16340 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16341 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16342 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16343 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16344 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16345 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16346 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16347 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16348 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16349 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16350 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16351 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16352 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16353 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16354 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16355 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16356 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16357 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16358 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16359 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16360 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16361 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16362 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16363 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16364 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16365 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16366 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16367 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16368 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16369 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16370 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16371 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16372 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16373 
output [0:0] DOA;
16374 
output [3:0] DOB;
16375 
input [13:0] ADDRA;
16376 
input [11:0] ADDRB;
16377 
input CLKA;
16378 
input CLKB;
16379 
input [0:0] DIA;
16380 
input [3:0] DIB;
16381 
input ENA;
16382 
input ENB;
16383 
input SSRA;
16384 
input SSRB;
16385 
input WEA;
16386 
input WEB;
16387 
endmodule
16388 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16389 
module RAMB16_S1_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16390 
parameter INIT_A = 1'h0;
16391 
parameter INIT_B = 9'h0;
16392 
parameter SRVAL_A = 1'h0;
16393 
parameter SRVAL_B = 9'h0;
16394 
parameter WRITE_MODE_A = "WRITE_FIRST";
16395 
parameter WRITE_MODE_B = "WRITE_FIRST";
16396 
parameter SIM_COLLISION_CHECK = "ALL";
16397 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16398 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16399 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16400 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16401 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16402 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16403 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16404 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16405 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16406 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16407 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16408 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16409 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16410 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16411 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16412 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16413 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16414 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16415 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16416 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16417 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16418 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16419 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16420 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16421 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16422 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16423 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16424 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16425 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16426 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16427 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16428 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16429 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16430 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16431 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16432 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16433 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16434 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16435 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16436 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16437 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16438 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16439 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16440 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16441 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16442 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16443 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16444 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16445 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16446 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16447 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16448 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16449 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16450 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16451 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16452 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16453 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16454 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16455 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16456 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16457 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16458 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16459 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16460 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16461 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16462 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16463 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16464 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16465 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16466 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16467 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16468 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16469 
output [0:0] DOA;
16470 
output [7:0] DOB;
16471 
output [0:0] DOPB;
16472 
input [13:0] ADDRA;
16473 
input [10:0] ADDRB;
16474 
input CLKA;
16475 
input CLKB;
16476 
input [0:0] DIA;
16477 
input [7:0] DIB;
16478 
input [0:0] DIPB;
16479 
input ENA;
16480 
input ENB;
16481 
input SSRA;
16482 
input SSRB;
16483 
input WEA;
16484 
input WEB;
16485 
endmodule
16486 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16487 
module RAMB16_S1 (DO, ADDR, CLK, DI, EN, SSR, WE);
16488 
parameter INIT = 1'h0;
16489 
parameter SRVAL = 1'h0;
16490 
parameter WRITE_MODE = "WRITE_FIRST";
16491 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16492 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16493 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16494 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16495 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16496 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16497 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16498 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16499 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16500 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16501 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16502 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16503 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16504 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16505 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16506 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16507 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16508 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16509 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16510 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16511 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16512 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16513 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16514 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16515 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16516 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16517 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16518 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16519 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16520 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16521 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16522 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16523 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16524 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16525 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16526 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16527 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16528 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16529 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16530 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16531 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16532 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16533 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16534 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16535 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16536 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16537 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16538 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16539 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16540 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16541 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16542 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16543 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16544 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16545 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16546 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16547 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16548 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16549 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16550 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16551 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16552 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16553 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16554 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16555 
output [0:0] DO;
16556 
input [13:0] ADDR;
16557 
input CLK;
16558 
input [0:0] DI;
16559 
input EN;
16560 
input SSR;
16561 
input WE;
16562 
endmodule
16563 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16564 
module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16565 
parameter INIT_A = 2'h0;
16566 
parameter INIT_B = 18'h0;
16567 
parameter SRVAL_A = 2'h0;
16568 
parameter SRVAL_B = 18'h0;
16569 
parameter WRITE_MODE_A = "WRITE_FIRST";
16570 
parameter WRITE_MODE_B = "WRITE_FIRST";
16571 
parameter SIM_COLLISION_CHECK = "ALL";
16572 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16573 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16574 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16575 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16576 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16577 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16578 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16579 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16580 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16581 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16582 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16583 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16584 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16585 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16586 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16587 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16588 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16589 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16590 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16591 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16592 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16593 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16594 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16595 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16596 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16597 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16598 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16599 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16600 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16601 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16602 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16603 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16604 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16605 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16606 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16607 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16608 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16609 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16610 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16611 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16612 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16613 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16614 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16615 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16616 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16617 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16618 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16619 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16620 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16621 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16622 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16623 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16624 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16625 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16626 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16627 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16628 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16629 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16630 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16631 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16632 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16633 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16634 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16635 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16636 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16637 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16638 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16639 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16640 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16641 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16642 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16643 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16644 
output [1:0] DOA;
16645 
output [15:0] DOB;
16646 
output [1:0] DOPB;
16647 
input [12:0] ADDRA;
16648 
input [9:0] ADDRB;
16649 
input CLKA;
16650 
input CLKB;
16651 
input [1:0] DIA;
16652 
input [15:0] DIB;
16653 
input [1:0] DIPB;
16654 
input ENA;
16655 
input ENB;
16656 
input SSRA;
16657 
input SSRB;
16658 
input WEA;
16659 
input WEB;
16660 
endmodule
16661 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16662 
module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16663 
parameter INIT_A = 2'h0;
16664 
parameter INIT_B = 2'h0;
16665 
parameter SRVAL_A = 2'h0;
16666 
parameter SRVAL_B = 2'h0;
16667 
parameter WRITE_MODE_A = "WRITE_FIRST";
16668 
parameter WRITE_MODE_B = "WRITE_FIRST";
16669 
parameter SIM_COLLISION_CHECK = "ALL";
16670 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16671 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16672 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16673 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16674 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16675 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16676 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16677 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16678 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16679 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16680 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16681 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16682 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16683 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16684 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16685 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16686 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16687 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16688 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16689 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16690 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16691 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16692 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16693 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16694 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16695 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16696 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16697 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16698 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16699 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16700 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16701 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16702 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16703 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16704 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16705 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16706 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16707 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16708 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16709 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16710 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16711 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16712 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16713 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16714 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16715 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16716 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16717 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16718 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16719 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16720 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16721 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16722 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16723 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16724 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16725 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16726 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16727 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16728 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16729 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16730 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16731 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16732 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16733 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16734 
output [1:0] DOA;
16735 
output [1:0] DOB;
16736 
input [12:0] ADDRA;
16737 
input [12:0] ADDRB;
16738 
input CLKA;
16739 
input CLKB;
16740 
input [1:0] DIA;
16741 
input [1:0] DIB;
16742 
input ENA;
16743 
input ENB;
16744 
input SSRA;
16745 
input SSRB;
16746 
input WEA;
16747 
input WEB;
16748 
endmodule
16749 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16750 
module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16751 
parameter INIT_A = 2'h0;
16752 
parameter INIT_B = 36'h0;
16753 
parameter SRVAL_A = 2'h0;
16754 
parameter SRVAL_B = 36'h0;
16755 
parameter WRITE_MODE_A = "WRITE_FIRST";
16756 
parameter WRITE_MODE_B = "WRITE_FIRST";
16757 
parameter SIM_COLLISION_CHECK = "ALL";
16758 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16759 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16760 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16761 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16762 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16763 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16764 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16765 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16766 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16767 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16768 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16769 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16770 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16771 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16772 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16773 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16774 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16775 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16776 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16777 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16778 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16779 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16780 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16781 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16782 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16783 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16784 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16785 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16786 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16787 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16788 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16789 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16790 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16791 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16792 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16793 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16794 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16795 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16796 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16797 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16798 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16799 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16800 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16801 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16802 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16803 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16804 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16805 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16806 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16807 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16808 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16809 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16810 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16811 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16812 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16813 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16814 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16815 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16816 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16817 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16818 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16819 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16820 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16821 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16822 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16823 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16824 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16825 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16826 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16827 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16828 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16829 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16830 
output [1:0] DOA;
16831 
output [31:0] DOB;
16832 
output [3:0] DOPB;
16833 
input [12:0] ADDRA;
16834 
input [8:0] ADDRB;
16835 
input CLKA;
16836 
input CLKB;
16837 
input [1:0] DIA;
16838 
input [31:0] DIB;
16839 
input [3:0] DIPB;
16840 
input ENA;
16841 
input ENB;
16842 
input SSRA;
16843 
input SSRB;
16844 
input WEA;
16845 
input WEB;
16846 
endmodule
16847 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16848 
module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16849 
parameter INIT_A = 2'h0;
16850 
parameter INIT_B = 4'h0;
16851 
parameter SRVAL_A = 2'h0;
16852 
parameter SRVAL_B = 4'h0;
16853 
parameter WRITE_MODE_A = "WRITE_FIRST";
16854 
parameter WRITE_MODE_B = "WRITE_FIRST";
16855 
parameter SIM_COLLISION_CHECK = "ALL";
16856 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16857 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16858 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16859 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16860 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16861 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16862 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16863 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16864 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16865 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16866 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16867 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16868 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16869 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16870 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16871 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16872 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16873 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16874 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16875 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16876 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16877 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16878 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16879 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16880 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16881 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16882 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16883 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16884 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16885 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16886 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16887 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16888 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16889 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16890 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16891 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16892 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16893 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16894 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16895 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16896 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16897 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16898 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16899 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16900 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16901 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16902 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16903 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16904 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16905 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16906 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16907 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16908 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16909 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16910 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16911 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16912 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16913 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16914 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16915 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16916 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16917 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16918 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16919 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16920 
output [1:0] DOA;
16921 
output [3:0] DOB;
16922 
input [12:0] ADDRA;
16923 
input [11:0] ADDRB;
16924 
input CLKA;
16925 
input CLKB;
16926 
input [1:0] DIA;
16927 
input [3:0] DIB;
16928 
input ENA;
16929 
input ENB;
16930 
input SSRA;
16931 
input SSRB;
16932 
input WEA;
16933 
input WEB;
16934 
endmodule
16935 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
16936 
module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
16937 
parameter INIT_A = 2'h0;
16938 
parameter INIT_B = 9'h0;
16939 
parameter SRVAL_A = 2'h0;
16940 
parameter SRVAL_B = 9'h0;
16941 
parameter WRITE_MODE_A = "WRITE_FIRST";
16942 
parameter WRITE_MODE_B = "WRITE_FIRST";
16943 
parameter SIM_COLLISION_CHECK = "ALL";
16944 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16945 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16946 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16947 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16948 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16949 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16950 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16951 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16952 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16953 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16954 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16955 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16956 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16957 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16958 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16959 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16960 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16961 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16962 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16963 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16964 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16965 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16966 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16967 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16968 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16969 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16970 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16971 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16972 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16973 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16974 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16975 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16976 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16977 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16978 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16979 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16980 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16981 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16982 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16983 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16984 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16985 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16986 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16987 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16988 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16989 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16990 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16991 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16992 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16993 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16994 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16995 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16996 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16997 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16998 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16999 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17000 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17001 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17002 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17003 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17004 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17005 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17006 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17007 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17008 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17009 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17010 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17011 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17012 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17013 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17014 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17015 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17016 
output [1:0] DOA;
17017 
output [7:0] DOB;
17018 
output [0:0] DOPB;
17019 
input [12:0] ADDRA;
17020 
input [10:0] ADDRB;
17021 
input CLKA;
17022 
input CLKB;
17023 
input [1:0] DIA;
17024 
input [7:0] DIB;
17025 
input [0:0] DIPB;
17026 
input ENA;
17027 
input ENB;
17028 
input SSRA;
17029 
input SSRB;
17030 
input WEA;
17031 
input WEB;
17032 
endmodule
17033 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17034 
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
17035 
parameter INIT = 2'h0;
17036 
parameter SRVAL = 2'h0;
17037 
parameter WRITE_MODE = "WRITE_FIRST";
17038 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17039 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17040 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17041 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17042 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17043 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17044 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17045 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17046 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17047 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17048 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17049 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17050 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17051 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17052 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17053 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17054 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17055 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17056 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17057 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17058 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17059 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17060 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17061 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17062 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17063 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17064 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17065 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17066 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17067 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17068 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17069 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17070 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17071 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17072 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17073 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17074 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17075 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17076 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17077 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17078 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17079 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17080 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17081 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17082 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17083 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17084 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17085 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17086 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17087 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17088 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17089 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17090 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17091 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17092 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17093 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17094 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17095 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17096 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17097 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17098 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17099 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17100 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17101 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17102 
output [1:0] DO;
17103 
input [12:0] ADDR;
17104 
input CLK;
17105 
input [1:0] DI;
17106 
input EN;
17107 
input SSR;
17108 
input WE;
17109 
endmodule
17110 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17111 
module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17112 
parameter INIT_A = 36'h0;
17113 
parameter INIT_B = 36'h0;
17114 
parameter SRVAL_A = 36'h0;
17115 
parameter SRVAL_B = 36'h0;
17116 
parameter WRITE_MODE_A = "WRITE_FIRST";
17117 
parameter WRITE_MODE_B = "WRITE_FIRST";
17118 
parameter SIM_COLLISION_CHECK = "ALL";
17119 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17120 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17121 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17122 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17123 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17124 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17125 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17126 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17127 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17128 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17129 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17130 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17131 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17132 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17133 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17134 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17135 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17136 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17137 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17138 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17139 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17140 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17141 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17142 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17143 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17144 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17145 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17146 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17147 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17148 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17149 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17150 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17151 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17152 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17153 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17154 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17155 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17156 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17157 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17158 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17159 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17160 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17161 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17162 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17163 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17164 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17165 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17166 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17167 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17168 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17169 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17170 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17171 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17172 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17173 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17174 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17175 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17176 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17177 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17178 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17179 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17180 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17181 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17182 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17183 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17184 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17185 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17186 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17187 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17188 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17189 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17190 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17191 
output [31:0] DOA;
17192 
output [31:0] DOB;
17193 
output [3:0] DOPA;
17194 
output [3:0] DOPB;
17195 
input [8:0] ADDRA;
17196 
input [8:0] ADDRB;
17197 
input CLKA;
17198 
input CLKB;
17199 
input [31:0] DIA;
17200 
input [31:0] DIB;
17201 
input [3:0] DIPA;
17202 
input [3:0] DIPB;
17203 
input ENA;
17204 
input ENB;
17205 
input SSRA;
17206 
input SSRB;
17207 
input WEA;
17208 
input WEB;
17209 
endmodule
17210 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17211 
module RAMB16_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
17212 
parameter INIT = 36'h0;
17213 
parameter SRVAL = 36'h0;
17214 
parameter WRITE_MODE = "WRITE_FIRST";
17215 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17216 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17217 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17218 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17219 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17220 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17221 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17222 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17223 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17224 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17225 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17226 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17227 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17228 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17229 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17230 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17231 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17232 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17233 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17234 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17235 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17236 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17237 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17238 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17239 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17240 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17241 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17242 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17243 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17244 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17245 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17246 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17247 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17248 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17249 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17250 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17251 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17252 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17253 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17254 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17255 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17256 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17257 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17258 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17259 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17260 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17261 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17262 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17263 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17264 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17265 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17266 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17267 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17268 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17269 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17270 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17271 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17272 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17273 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17274 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17275 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17276 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17277 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17278 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17279 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17280 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17281 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17282 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17283 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17284 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17285 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17286 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17287 
output [31:0] DO;
17288 
output [3:0] DOP;
17289 
input [8:0] ADDR;
17290 
input CLK;
17291 
input [31:0] DI;
17292 
input [3:0] DIP;
17293 
input EN;
17294 
input SSR;
17295 
input WE;
17296 
endmodule
17297 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17298 
module RAMB16_S4_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17299 
parameter INIT_A = 4'h0;
17300 
parameter INIT_B = 18'h0;
17301 
parameter SRVAL_A = 4'h0;
17302 
parameter SRVAL_B = 18'h0;
17303 
parameter WRITE_MODE_A = "WRITE_FIRST";
17304 
parameter WRITE_MODE_B = "WRITE_FIRST";
17305 
parameter SIM_COLLISION_CHECK = "ALL";
17306 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17307 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17308 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17309 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17310 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17311 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17312 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17313 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17314 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17315 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17316 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17317 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17318 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17319 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17320 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17321 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17322 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17323 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17324 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17325 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17326 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17327 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17328 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17329 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17330 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17331 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17332 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17333 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17334 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17335 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17336 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17337 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17338 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17339 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17340 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17341 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17342 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17343 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17344 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17345 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17346 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17347 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17348 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17349 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17350 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17351 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17352 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17353 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17354 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17355 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17356 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17357 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17358 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17359 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17360 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17361 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17362 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17363 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17364 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17365 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17366 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17367 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17368 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17369 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17370 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17371 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17372 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17373 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17374 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17375 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17376 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17377 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17378 
output [3:0] DOA;
17379 
output [15:0] DOB;
17380 
output [1:0] DOPB;
17381 
input [11:0] ADDRA;
17382 
input [9:0] ADDRB;
17383 
input CLKA;
17384 
input CLKB;
17385 
input [3:0] DIA;
17386 
input [15:0] DIB;
17387 
input [1:0] DIPB;
17388 
input ENA;
17389 
input ENB;
17390 
input SSRA;
17391 
input SSRB;
17392 
input WEA;
17393 
input WEB;
17394 
endmodule
17395 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17396 
module RAMB16_S4_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17397 
parameter INIT_A = 4'h0;
17398 
parameter INIT_B = 36'h0;
17399 
parameter SRVAL_A = 4'h0;
17400 
parameter SRVAL_B = 36'h0;
17401 
parameter WRITE_MODE_A = "WRITE_FIRST";
17402 
parameter WRITE_MODE_B = "WRITE_FIRST";
17403 
parameter SIM_COLLISION_CHECK = "ALL";
17404 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17405 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17406 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17407 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17408 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17409 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17410 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17411 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17412 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17413 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17414 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17415 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17416 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17417 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17418 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17419 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17420 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17421 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17422 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17423 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17424 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17425 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17426 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17427 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17428 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17429 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17430 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17431 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17432 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17433 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17434 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17435 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17436 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17437 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17438 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17439 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17440 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17441 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17442 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17443 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17444 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17445 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17446 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17447 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17448 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17449 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17450 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17451 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17452 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17453 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17454 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17455 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17456 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17457 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17458 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17459 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17460 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17461 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17462 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17463 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17464 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17465 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17466 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17467 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17468 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17469 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17470 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17471 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17472 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17473 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17474 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17475 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17476 
output [3:0] DOA;
17477 
output [31:0] DOB;
17478 
output [3:0] DOPB;
17479 
input [11:0] ADDRA;
17480 
input [8:0] ADDRB;
17481 
input CLKA;
17482 
input CLKB;
17483 
input [3:0] DIA;
17484 
input [31:0] DIB;
17485 
input [3:0] DIPB;
17486 
input ENA;
17487 
input ENB;
17488 
input SSRA;
17489 
input SSRB;
17490 
input WEA;
17491 
input WEB;
17492 
endmodule
17493 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17494 
module RAMB16_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17495 
parameter INIT_A = 4'h0;
17496 
parameter INIT_B = 4'h0;
17497 
parameter SRVAL_A = 4'h0;
17498 
parameter SRVAL_B = 4'h0;
17499 
parameter WRITE_MODE_A = "WRITE_FIRST";
17500 
parameter WRITE_MODE_B = "WRITE_FIRST";
17501 
parameter SIM_COLLISION_CHECK = "ALL";
17502 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17503 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17504 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17505 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17506 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17507 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17508 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17509 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17510 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17511 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17512 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17513 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17514 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17515 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17516 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17517 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17518 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17519 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17520 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17521 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17522 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17523 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17524 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17525 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17526 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17527 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17528 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17529 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17530 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17531 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17532 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17533 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17534 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17535 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17536 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17537 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17538 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17539 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17540 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17541 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17542 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17543 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17544 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17545 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17546 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17547 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17548 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17549 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17550 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17551 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17552 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17553 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17554 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17555 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17556 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17557 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17558 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17559 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17560 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17561 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17562 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17563 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17564 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17565 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17566 
output [3:0] DOA;
17567 
output [3:0] DOB;
17568 
input [11:0] ADDRA;
17569 
input [11:0] ADDRB;
17570 
input CLKA;
17571 
input CLKB;
17572 
input [3:0] DIA;
17573 
input [3:0] DIB;
17574 
input ENA;
17575 
input ENB;
17576 
input SSRA;
17577 
input SSRB;
17578 
input WEA;
17579 
input WEB;
17580 
endmodule
17581 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17582 
module RAMB16_S4_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17583 
parameter INIT_A = 4'h0;
17584 
parameter INIT_B = 9'h0;
17585 
parameter SRVAL_A = 4'h0;
17586 
parameter SRVAL_B = 9'h0;
17587 
parameter WRITE_MODE_A = "WRITE_FIRST";
17588 
parameter WRITE_MODE_B = "WRITE_FIRST";
17589 
parameter SIM_COLLISION_CHECK = "ALL";
17590 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17591 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17592 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17593 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17594 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17595 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17596 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17597 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17598 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17599 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17600 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17601 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17602 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17603 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17604 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17605 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17606 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17607 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17608 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17609 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17610 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17611 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17612 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17613 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17614 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17615 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17616 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17617 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17618 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17619 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17620 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17621 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17622 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17623 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17624 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17625 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17626 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17627 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17628 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17629 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17630 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17631 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17632 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17633 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17634 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17635 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17636 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17637 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17638 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17639 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17640 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17641 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17642 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17643 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17644 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17645 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17646 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17647 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17648 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17649 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17650 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17651 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17652 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17653 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17654 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17655 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17656 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17657 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17658 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17659 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17660 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17661 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17662 
output [3:0] DOA;
17663 
output [7:0] DOB;
17664 
output [0:0] DOPB;
17665 
input [11:0] ADDRA;
17666 
input [10:0] ADDRB;
17667 
input CLKA;
17668 
input CLKB;
17669 
input [3:0] DIA;
17670 
input [7:0] DIB;
17671 
input [0:0] DIPB;
17672 
input ENA;
17673 
input ENB;
17674 
input SSRA;
17675 
input SSRB;
17676 
input WEA;
17677 
input WEB;
17678 
endmodule
17679 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17680 
module RAMB16_S4 (DO, ADDR, CLK, DI, EN, SSR, WE);
17681 
parameter INIT = 4'h0;
17682 
parameter SRVAL = 4'h0;
17683 
parameter WRITE_MODE = "WRITE_FIRST";
17684 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17685 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17686 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17687 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17688 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17689 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17690 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17691 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17692 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17693 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17694 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17695 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17696 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17697 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17698 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17699 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17700 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17701 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17702 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17703 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17704 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17705 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17706 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17707 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17708 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17709 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17710 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17711 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17712 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17713 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17714 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17715 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17716 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17717 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17718 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17719 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17720 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17721 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17722 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17723 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17724 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17725 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17726 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17727 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17728 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17729 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17730 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17731 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17732 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17733 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17734 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17735 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17736 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17737 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17738 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17739 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17740 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17741 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17742 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17743 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17744 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17745 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17746 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17747 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17748 
output [3:0] DO;
17749 
input [11:0] ADDR;
17750 
input CLK;
17751 
input [3:0] DI;
17752 
input EN;
17753 
input SSR;
17754 
input WE;
17755 
endmodule
17756 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17757 
module RAMB16_S9_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17758 
parameter INIT_A = 9'h0;
17759 
parameter INIT_B = 18'h0;
17760 
parameter SRVAL_A = 9'h0;
17761 
parameter SRVAL_B = 18'h0;
17762 
parameter WRITE_MODE_A = "WRITE_FIRST";
17763 
parameter WRITE_MODE_B = "WRITE_FIRST";
17764 
parameter SIM_COLLISION_CHECK = "ALL";
17765 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17766 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17767 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17768 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17769 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17770 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17771 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17772 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17773 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17774 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17775 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17776 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17777 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17778 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17779 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17780 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17781 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17782 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17783 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17784 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17785 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17786 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17787 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17788 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17789 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17790 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17791 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17792 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17793 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17794 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17795 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17796 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17797 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17798 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17799 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17800 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17801 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17802 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17803 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17804 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17805 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17806 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17807 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17808 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17809 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17810 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17811 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17812 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17813 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17814 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17815 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17816 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17817 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17818 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17819 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17820 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17821 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17822 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17823 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17824 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17825 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17826 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17827 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17828 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17829 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17830 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17831 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17832 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17833 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17834 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17835 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17836 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17837 
output [7:0] DOA;
17838 
output [15:0] DOB;
17839 
output [0:0] DOPA;
17840 
output [1:0] DOPB;
17841 
input [10:0] ADDRA;
17842 
input [9:0] ADDRB;
17843 
input CLKA;
17844 
input CLKB;
17845 
input [7:0] DIA;
17846 
input [15:0] DIB;
17847 
input [0:0] DIPA;
17848 
input [1:0] DIPB;
17849 
input ENA;
17850 
input ENB;
17851 
input SSRA;
17852 
input SSRB;
17853 
input WEA;
17854 
input WEB;
17855 
endmodule
17856 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17857 
module RAMB16_S9_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17858 
parameter INIT_A = 9'h0;
17859 
parameter INIT_B = 36'h0;
17860 
parameter SRVAL_A = 9'h0;
17861 
parameter SRVAL_B = 36'h0;
17862 
parameter WRITE_MODE_A = "WRITE_FIRST";
17863 
parameter WRITE_MODE_B = "WRITE_FIRST";
17864 
parameter SIM_COLLISION_CHECK = "ALL";
17865 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17866 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17867 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17868 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17869 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17870 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17871 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17872 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17873 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17874 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17875 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17876 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17877 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17878 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17879 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17880 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17881 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17882 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17883 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17884 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17885 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17886 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17887 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17888 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17889 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17890 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17891 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17892 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17893 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17894 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17895 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17896 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17897 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17898 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17899 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17900 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17901 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17902 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17903 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17904 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17905 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17906 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17907 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17908 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17909 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17910 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17911 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17912 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17913 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17914 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17915 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17916 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17917 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17918 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17919 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17920 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17921 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17922 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17923 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17924 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17925 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17926 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17927 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17928 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17929 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17930 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17931 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17932 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17933 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17934 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17935 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17936 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17937 
output [7:0] DOA;
17938 
output [31:0] DOB;
17939 
output [0:0] DOPA;
17940 
output [3:0] DOPB;
17941 
input [10:0] ADDRA;
17942 
input [8:0] ADDRB;
17943 
input CLKA;
17944 
input CLKB;
17945 
input [7:0] DIA;
17946 
input [31:0] DIB;
17947 
input [0:0] DIPA;
17948 
input [3:0] DIPB;
17949 
input ENA;
17950 
input ENB;
17951 
input SSRA;
17952 
input SSRB;
17953 
input WEA;
17954 
input WEB;
17955 
endmodule
17956 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
17957 
module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
17958 
parameter INIT_A = 9'h0;
17959 
parameter INIT_B = 9'h0;
17960 
parameter SRVAL_A = 9'h0;
17961 
parameter SRVAL_B = 9'h0;
17962 
parameter WRITE_MODE_A = "WRITE_FIRST";
17963 
parameter WRITE_MODE_B = "WRITE_FIRST";
17964 
parameter SIM_COLLISION_CHECK = "ALL";
17965 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17966 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17967 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17968 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17969 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17970 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17971 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17972 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17973 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17974 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17975 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17976 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17977 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17978 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17979 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17980 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17981 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17982 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17983 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17984 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17985 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17986 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17987 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17988 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17989 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17990 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17991 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17992 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17993 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17994 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17995 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17996 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17997 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17998 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17999 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18000 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18001 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18002 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18003 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18004 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18005 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18006 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18007 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18008 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18009 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18010 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18011 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18012 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18013 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18014 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18015 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18016 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18017 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18018 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18019 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18020 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18021 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18022 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18023 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18024 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18025 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18026 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18027 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18028 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18029 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18030 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18031 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18032 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18033 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18034 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18035 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18036 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18037 
output [7:0] DOA;
18038 
output [7:0] DOB;
18039 
output [0:0] DOPA;
18040 
output [0:0] DOPB;
18041 
input [10:0] ADDRA;
18042 
input [10:0] ADDRB;
18043 
input CLKA;
18044 
input CLKB;
18045 
input [7:0] DIA;
18046 
input [7:0] DIB;
18047 
input [0:0] DIPA;
18048 
input [0:0] DIPB;
18049 
input ENA;
18050 
input ENB;
18051 
input SSRA;
18052 
input SSRB;
18053 
input WEA;
18054 
input WEB;
18055 
endmodule
18056 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18057 
module RAMB16_S9 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
18058 
parameter INIT = 9'h0;
18059 
parameter SRVAL = 9'h0;
18060 
parameter WRITE_MODE = "WRITE_FIRST";
18061 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18062 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18063 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18064 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18065 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18066 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18067 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18068 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18069 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18070 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18071 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18072 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18073 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18074 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18075 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18076 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18077 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18078 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18079 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18080 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18081 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18082 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18083 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18084 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18085 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18086 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18087 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18088 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18089 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18090 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18091 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18092 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18093 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18094 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18095 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18096 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18097 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18098 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18099 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18100 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18101 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18102 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18103 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18104 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18105 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18106 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18107 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18108 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18109 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18110 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18111 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18112 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18113 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18114 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18115 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18116 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18117 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18118 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18119 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18120 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18121 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18122 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18123 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18124 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18125 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18126 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18127 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18128 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18129 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18130 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18131 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18132 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18133 
output [7:0] DO;
18134 
output [0:0] DOP;
18135 
input [10:0] ADDR;
18136 
input CLK;
18137 
input [7:0] DI;
18138 
input [0:0] DIP;
18139 
input EN;
18140 
input SSR;
18141 
input WE;
18142 
endmodule
18143 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18144 
module RAMB16 (CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
18145 
parameter integer DOA_REG = 0;
18146 
parameter integer DOB_REG = 0;
18147 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18148 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18149 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18150 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18151 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18152 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18153 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18154 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18155 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18156 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18157 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18158 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18159 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18160 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18161 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18162 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18163 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18164 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18165 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18166 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18167 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18168 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18169 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18170 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18171 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18172 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18173 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18174 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18175 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18176 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18177 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18178 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18179 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18180 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18181 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18182 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18183 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18184 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18185 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18186 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18187 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18188 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18189 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18190 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18191 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18192 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18193 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18194 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18195 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18196 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18197 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18198 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18199 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18200 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18201 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18202 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18203 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18204 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18205 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18206 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18207 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18208 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18209 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18210 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18211 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18212 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18213 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18214 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18215 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18216 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18217 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18218 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18219 
parameter INIT_A = 36'h0;
18220 
parameter INIT_B = 36'h0;
18221 
parameter INIT_FILE = "NONE";
18222 
parameter INVERT_CLK_DOA_REG = "FALSE";
18223 
parameter INVERT_CLK_DOB_REG = "FALSE";
18224 
parameter RAM_EXTENSION_A = "NONE";
18225 
parameter RAM_EXTENSION_B = "NONE";
18226 
parameter integer READ_WIDTH_A = 0;
18227 
parameter integer READ_WIDTH_B = 0;
18228 
parameter SIM_COLLISION_CHECK = "ALL";
18229 
parameter SRVAL_A = 36'h0;
18230 
parameter SRVAL_B = 36'h0;
18231 
parameter WRITE_MODE_A = "WRITE_FIRST";
18232 
parameter WRITE_MODE_B = "WRITE_FIRST";
18233 
parameter integer WRITE_WIDTH_A = 0;
18234 
parameter integer WRITE_WIDTH_B = 0;
18235 
output CASCADEOUTA;
18236 
output CASCADEOUTB;
18237 
output [31:0] DOA;
18238 
output [31:0] DOB;
18239 
output [3:0] DOPA;
18240 
output [3:0] DOPB;
18241 
input [14:0] ADDRA;
18242 
input [14:0] ADDRB;
18243 
input CASCADEINA;
18244 
input CASCADEINB;
18245 
input CLKA;
18246 
input CLKB;
18247 
input [31:0] DIA;
18248 
input [31:0] DIB;
18249 
input [3:0] DIPA;
18250 
input [3:0] DIPB;
18251 
input ENA;
18252 
input ENB;
18253 
input REGCEA;
18254 
input REGCEB;
18255 
input SSRA;
18256 
input SSRB;
18257 
input [3:0] WEA;
18258 
input [3:0] WEB;
18259 
endmodule
18260 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18261 
module RAMB18SDP (DO, DOP, DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN);
18262 
parameter integer DO_REG = 0;
18263 
parameter INIT = 36'h0;
18264 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18265 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18266 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18267 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18268 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18269 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18270 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18271 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18272 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18273 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18274 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18275 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18276 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18277 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18278 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18279 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18280 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18281 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18282 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18283 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18284 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18285 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18286 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18287 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18288 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18289 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18290 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18291 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18292 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18293 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18294 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18295 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18296 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18297 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18298 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18299 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18300 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18301 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18302 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18303 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18304 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18305 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18306 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18307 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18308 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18309 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18310 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18311 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18312 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18313 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18314 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18315 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18316 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18317 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18318 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18319 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18320 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18321 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18322 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18323 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18324 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18325 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18326 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18327 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18328 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18329 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18330 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18331 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18332 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18333 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18334 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18335 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18336 
parameter INIT_FILE = "NONE";
18337 
parameter SIM_COLLISION_CHECK = "ALL";
18338 
parameter SIM_MODE = "SAFE";
18339 
parameter SRVAL = 36'h0;
18340 
output [31:0] DO;
18341 
output [3:0] DOP;
18342 
input [31:0] DI;
18343 
input [3:0] DIP;
18344 
input [8:0] RDADDR;
18345 
input RDCLK;
18346 
input RDEN;
18347 
input REGCE;
18348 
input SSR;
18349 
input [3:0] WE;
18350 
input [8:0] WRADDR;
18351 
input WRCLK;
18352 
input WREN;
18353 
endmodule
18354 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18355 
module RAMB18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
18356 
parameter integer DOA_REG = 0;
18357 
parameter integer DOB_REG = 0;
18358 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18359 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18360 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18361 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18362 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18363 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18364 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18365 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18366 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18367 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18368 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18369 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18370 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18371 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18372 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18373 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18374 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18375 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18376 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18377 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18378 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18379 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18380 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18381 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18382 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18383 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18384 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18385 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18386 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18387 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18388 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18389 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18390 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18391 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18392 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18393 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18394 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18395 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18396 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18397 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18398 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18399 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18400 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18401 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18402 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18403 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18404 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18405 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18406 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18407 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18408 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18409 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18410 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18411 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18412 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18413 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18414 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18415 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18416 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18417 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18418 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18419 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18420 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18421 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18422 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18423 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18424 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18425 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18426 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18427 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18428 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18429 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18430 
parameter INIT_A = 18'h0;
18431 
parameter INIT_B = 18'h0;
18432 
parameter INIT_FILE = "NONE";
18433 
parameter integer READ_WIDTH_A = 0;
18434 
parameter integer READ_WIDTH_B = 0;
18435 
parameter SIM_COLLISION_CHECK = "ALL";
18436 
parameter SIM_MODE = "SAFE";
18437 
parameter SRVAL_A = 18'h0;
18438 
parameter SRVAL_B = 18'h0;
18439 
parameter WRITE_MODE_A = "WRITE_FIRST";
18440 
parameter WRITE_MODE_B = "WRITE_FIRST";
18441 
parameter integer WRITE_WIDTH_A = 0;
18442 
parameter integer WRITE_WIDTH_B = 0;
18443 
output [15:0] DOA;
18444 
output [15:0] DOB;
18445 
output [1:0] DOPA;
18446 
output [1:0] DOPB;
18447 
input [13:0] ADDRA;
18448 
input [13:0] ADDRB;
18449 
input CLKA;
18450 
input CLKB;
18451 
input [15:0] DIA;
18452 
input [15:0] DIB;
18453 
input [1:0] DIPA;
18454 
input [1:0] DIPB;
18455 
input ENA;
18456 
input ENB;
18457 
input REGCEA;
18458 
input REGCEB;
18459 
input SSRA;
18460 
input SSRB;
18461 
input [1:0] WEA;
18462 
input [1:0] WEB;
18463 
endmodule
18464 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18465 
module RAMB32_S64_ECC (DO, STATUS, DI, RDADDR, RDCLK, RDEN, SSR, WRADDR, WRCLK, WREN);
18466 
parameter integer DO_REG = 0;
18467 
parameter SIM_COLLISION_CHECK = "ALL";
18468 
output [63:0] DO;
18469 
output [1:0] STATUS;
18470 
input [63:0] DI;
18471 
input [8:0] RDADDR;
18472 
input RDCLK;
18473 
input RDEN;
18474 
input SSR;
18475 
input [8:0] WRADDR;
18476 
input WRCLK;
18477 
input WREN;
18478 
endmodule
18479 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18480 
module RAMB36_EXP (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRAL, ADDRAU, ADDRBL, ADDRBU, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKAL, CLKAU, CLKBL, CLKBU, DIA, DIB, DIPA, DIPB, ENAL, ENAU, ENBL, ENBU, REGCEAL, REGCEAU, REGCEBL, REGCEBU, REGCLKAL, REGCLKAU, REGCLKBL, REGCLKBU, SSRAL, SSRAU, SSRBL, SSRBU, WEAL, WEAU, WEBL, WEBU);
18481 
parameter integer DOA_REG = 0;
18482 
parameter integer DOB_REG = 0;
18483 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18484 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18485 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18486 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18487 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18488 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18489 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18490 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18491 
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18492 
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18493 
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18494 
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18495 
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18496 
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18497 
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18498 
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18499 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18500 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18501 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18502 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18503 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18504 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18505 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18506 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18507 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18508 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18509 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18510 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18511 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18512 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18513 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18514 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18515 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18516 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18517 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18518 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18519 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18520 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18521 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18522 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18523 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18524 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18525 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18526 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18527 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18528 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18529 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18530 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18531 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18532 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18533 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18534 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18535 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18536 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18537 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18538 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18539 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18540 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18541 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18542 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18543 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18544 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18545 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18546 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18547 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18548 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18549 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18550 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18551 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18552 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18553 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18554 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18555 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18556 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18557 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18558 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18559 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18560 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18561 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18562 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18563 
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18564 
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18565 
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18566 
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18567 
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18568 
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18569 
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18570 
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18571 
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18572 
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18573 
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18574 
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18575 
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18576 
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18577 
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18578 
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18579 
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18580 
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18581 
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18582 
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18583 
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18584 
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18585 
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18586 
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18587 
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18588 
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18589 
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18590 
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18591 
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18592 
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18593 
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18594 
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18595 
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18596 
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18597 
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18598 
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18599 
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18600 
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18601 
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18602 
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18603 
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18604 
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18605 
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18606 
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18607 
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18608 
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18609 
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18610 
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18611 
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18612 
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18613 
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18614 
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18615 
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18616 
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18617 
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18618 
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18619 
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18620 
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18621 
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18622 
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18623 
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18624 
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18625 
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18626 
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18627 
parameter INIT_A = 36'h0;
18628 
parameter INIT_B = 36'h0;
18629 
parameter INIT_FILE = "NONE";
18630 
parameter RAM_EXTENSION_A = "NONE";
18631 
parameter RAM_EXTENSION_B = "NONE";
18632 
parameter integer READ_WIDTH_A = 0;
18633 
parameter integer READ_WIDTH_B = 0;
18634 
parameter SIM_COLLISION_CHECK = "ALL";
18635 
parameter SIM_MODE = "SAFE";
18636 
parameter SRVAL_A = 36'h0;
18637 
parameter SRVAL_B = 36'h0;
18638 
parameter WRITE_MODE_A = "WRITE_FIRST";
18639 
parameter WRITE_MODE_B = "WRITE_FIRST";
18640 
parameter integer WRITE_WIDTH_A = 0;
18641 
parameter integer WRITE_WIDTH_B = 0;
18642 
output CASCADEOUTLATA;
18643 
output CASCADEOUTLATB;
18644 
output CASCADEOUTREGA;
18645 
output CASCADEOUTREGB;
18646 
output [31:0] DOA;
18647 
output [31:0] DOB;
18648 
output [3:0] DOPA;
18649 
output [3:0] DOPB;
18650 
input [15:0] ADDRAL;
18651 
input [14:0] ADDRAU;
18652 
input [15:0] ADDRBL;
18653 
input [14:0] ADDRBU;
18654 
input CASCADEINLATA;
18655 
input CASCADEINLATB;
18656 
input CASCADEINREGA;
18657 
input CASCADEINREGB;
18658 
input CLKAL;
18659 
input CLKAU;
18660 
input CLKBL;
18661 
input CLKBU;
18662 
input [31:0] DIA;
18663 
input [31:0] DIB;
18664 
input [3:0] DIPA;
18665 
input [3:0] DIPB;
18666 
input ENAL;
18667 
input ENAU;
18668 
input ENBL;
18669 
input ENBU;
18670 
input REGCEAL;
18671 
input REGCEAU;
18672 
input REGCEBL;
18673 
input REGCEBU;
18674 
input REGCLKAL;
18675 
input REGCLKAU;
18676 
input REGCLKBL;
18677 
input REGCLKBU;
18678 
input SSRAL;
18679 
input SSRAU;
18680 
input SSRBL;
18681 
input SSRBU;
18682 
input [3:0] WEAL;
18683 
input [3:0] WEAU;
18684 
input [7:0] WEBL;
18685 
input [7:0] WEBU;
18686 
endmodule
18687 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18688 
module RAMB36SDP_EXP (DBITERR, DO, DOP, ECCPARITY, SBITERR, DI, DIP, RDADDRL, RDADDRU, RDCLKL, RDCLKU, RDENL, RDENU, RDRCLKL, RDRCLKU, REGCEL, REGCEU, SSRL, SSRU, WEL, WEU, WRADDRL, WRADDRU, WRCLKL, WRCLKU, WRENL, WRENU);
18689 
parameter integer DO_REG = 0;
18690 
parameter EN_ECC_READ = "FALSE";
18691 
parameter EN_ECC_SCRUB = "FALSE";
18692 
parameter EN_ECC_WRITE = "FALSE";
18693 
parameter INIT = 72'h0;
18694 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18695 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18696 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18697 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18698 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18699 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18700 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18701 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18702 
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18703 
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18704 
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18705 
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18706 
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18707 
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18708 
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18709 
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18710 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18711 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18712 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18713 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18714 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18715 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18716 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18717 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18718 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18719 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18720 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18721 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18722 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18723 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18724 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18725 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18726 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18727 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18728 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18729 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18730 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18731 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18732 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18733 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18734 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18735 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18736 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18737 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18738 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18739 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18740 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18741 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18742 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18743 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18744 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18745 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18746 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18747 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18748 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18749 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18750 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18751 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18752 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18753 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18754 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18755 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18756 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18757 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18758 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18759 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18760 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18761 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18762 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18763 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18764 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18765 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18766 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18767 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18768 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18769 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18770 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18771 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18772 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18773 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18774 
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18775 
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18776 
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18777 
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18778 
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18779 
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18780 
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18781 
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18782 
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18783 
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18784 
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18785 
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18786 
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18787 
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18788 
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18789 
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18790 
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18791 
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18792 
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18793 
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18794 
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18795 
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18796 
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18797 
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18798 
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18799 
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18800 
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18801 
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18802 
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18803 
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18804 
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18805 
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18806 
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18807 
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18808 
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18809 
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18810 
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18811 
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18812 
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18813 
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18814 
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18815 
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18816 
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18817 
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18818 
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18819 
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18820 
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18821 
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18822 
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18823 
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18824 
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18825 
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18826 
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18827 
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18828 
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18829 
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18830 
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18831 
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18832 
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18833 
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18834 
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18835 
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18836 
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18837 
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18838 
parameter INIT_FILE = "NONE";
18839 
parameter SIM_COLLISION_CHECK = "ALL";
18840 
parameter SIM_MODE = "SAFE";
18841 
parameter SRVAL = 72'h0;
18842 
output DBITERR;
18843 
output [63:0] DO;
18844 
output [7:0] DOP;
18845 
output [7:0] ECCPARITY;
18846 
output SBITERR;
18847 
input [63:0] DI;
18848 
input [7:0] DIP;
18849 
input [15:0] RDADDRL;
18850 
input [14:0] RDADDRU;
18851 
input RDCLKL;
18852 
input RDCLKU;
18853 
input RDENL;
18854 
input RDENU;
18855 
input RDRCLKL;
18856 
input RDRCLKU;
18857 
input REGCEL;
18858 
input REGCEU;
18859 
input SSRL;
18860 
input SSRU;
18861 
input [7:0] WEL;
18862 
input [7:0] WEU;
18863 
input [15:0] WRADDRL;
18864 
input [14:0] WRADDRU;
18865 
input WRCLKL;
18866 
input WRCLKU;
18867 
input WRENL;
18868 
input WRENU;
18869 
endmodule
18870 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
18871 
module RAMB36SDP (DBITERR, DO, DOP, ECCPARITY, SBITERR, DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN);
18872 
parameter integer DO_REG = 0;
18873 
parameter EN_ECC_READ = "FALSE";
18874 
parameter EN_ECC_SCRUB = "FALSE";
18875 
parameter EN_ECC_WRITE = "FALSE";
18876 
parameter INIT = 72'h0;
18877 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18878 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18879 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18880 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18881 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18882 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18883 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18884 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18885 
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18886 
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18887 
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18888 
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18889 
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18890 
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18891 
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18892 
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18893 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18894 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18895 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18896 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18897 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18898 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18899 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18900 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18901 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18902 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18903 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18904 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18905 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18906 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18907 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18908 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18909 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18910 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18911 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18912 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18913 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18914 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18915 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18916 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18917 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18918 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18919 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18920 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18921 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18922 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18923 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18924 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18925 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18926 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18927 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18928 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18929 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18930 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18931 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18932 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18933 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18934 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18935 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18936 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18937 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18938 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18939 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18940 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18941 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18942 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18943 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18944 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18945 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18946 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18947 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18948 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18949 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18950 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18951 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18952 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18953 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18954 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18955 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18956 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18957 
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18958 
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18959 
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18960 
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18961 
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18962 
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18963 
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18964 
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18965 
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18966 
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18967 
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18968 
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18969 
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18970 
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18971 
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18972 
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18973 
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18974 
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18975 
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18976 
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18977 
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18978 
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18979 
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18980 
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18981 
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18982 
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18983 
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18984 
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18985 
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18986 
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18987 
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18988 
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18989 
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18990 
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18991 
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18992 
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18993 
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18994 
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18995 
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18996 
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18997 
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18998 
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18999 
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19000 
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19001 
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19002 
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19003 
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19004 
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19005 
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19006 
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19007 
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19008 
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19009 
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19010 
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19011 
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19012 
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19013 
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19014 
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19015 
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19016 
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19017 
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19018 
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19019 
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19020 
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19021 
parameter INIT_FILE = "NONE";
19022 
parameter SIM_COLLISION_CHECK = "ALL";
19023 
parameter SIM_MODE = "SAFE";
19024 
parameter SRVAL = 72'h0;
19025 
output DBITERR;
19026 
output [63:0] DO;
19027 
output [7:0] DOP;
19028 
output [7:0] ECCPARITY;
19029 
output SBITERR;
19030 
input [63:0] DI;
19031 
input [7:0] DIP;
19032 
input [8:0] RDADDR;
19033 
input RDCLK;
19034 
input RDEN;
19035 
input REGCE;
19036 
input SSR;
19037 
input [7:0] WE;
19038 
input [8:0] WRADDR;
19039 
input WRCLK;
19040 
input WREN;
19041 
endmodule
19042 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19043 
module RAMB36 (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
19044 
parameter integer DOA_REG = 0;
19045 
parameter integer DOB_REG = 0;
19046 
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19047 
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19048 
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19049 
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19050 
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19051 
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19052 
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19053 
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19054 
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19055 
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19056 
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19057 
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19058 
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19059 
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19060 
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19061 
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19062 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19063 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19064 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19065 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19066 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19067 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19068 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19069 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19070 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19071 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19072 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19073 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19074 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19075 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19076 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19077 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19078 
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19079 
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19080 
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19081 
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19082 
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19083 
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19084 
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19085 
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19086 
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19087 
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19088 
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19089 
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19090 
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19091 
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19092 
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19093 
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19094 
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19095 
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19096 
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19097 
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19098 
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19099 
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19100 
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19101 
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19102 
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19103 
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19104 
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19105 
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19106 
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19107 
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19108 
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19109 
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19110 
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19111 
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19112 
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19113 
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19114 
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19115 
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19116 
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19117 
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19118 
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19119 
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19120 
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19121 
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19122 
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19123 
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19124 
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19125 
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19126 
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19127 
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19128 
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19129 
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19130 
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19131 
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19132 
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19133 
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19134 
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19135 
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19136 
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19137 
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19138 
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19139 
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19140 
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19141 
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19142 
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19143 
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19144 
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19145 
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19146 
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19147 
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19148 
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19149 
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19150 
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19151 
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19152 
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19153 
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19154 
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19155 
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19156 
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19157 
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19158 
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19159 
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19160 
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19161 
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19162 
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19163 
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19164 
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19165 
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19166 
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19167 
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19168 
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19169 
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19170 
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19171 
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19172 
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19173 
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19174 
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19175 
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19176 
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19177 
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19178 
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19179 
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19180 
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19181 
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19182 
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19183 
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19184 
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19185 
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19186 
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19187 
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19188 
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19189 
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19190 
parameter INIT_A = 36'h0;
19191 
parameter INIT_B = 36'h0;
19192 
parameter INIT_FILE = "NONE";
19193 
parameter RAM_EXTENSION_A = "NONE";
19194 
parameter RAM_EXTENSION_B = "NONE";
19195 
parameter integer READ_WIDTH_A = 0;
19196 
parameter integer READ_WIDTH_B = 0;
19197 
parameter SIM_COLLISION_CHECK = "ALL";
19198 
parameter SIM_MODE = "SAFE";
19199 
parameter SRVAL_A = 36'h0;
19200 
parameter SRVAL_B = 36'h0;
19201 
parameter WRITE_MODE_A = "WRITE_FIRST";
19202 
parameter WRITE_MODE_B = "WRITE_FIRST";
19203 
parameter integer WRITE_WIDTH_A = 0;
19204 
parameter integer WRITE_WIDTH_B = 0;
19205 
output CASCADEOUTLATA;
19206 
output CASCADEOUTLATB;
19207 
output CASCADEOUTREGA;
19208 
output CASCADEOUTREGB;
19209 
output [31:0] DOA;
19210 
output [31:0] DOB;
19211 
output [3:0] DOPA;
19212 
output [3:0] DOPB;
19213 
input [15:0] ADDRA;
19214 
input [15:0] ADDRB;
19215 
input CASCADEINLATA;
19216 
input CASCADEINLATB;
19217 
input CASCADEINREGA;
19218 
input CASCADEINREGB;
19219 
input CLKA;
19220 
input CLKB;
19221 
input [31:0] DIA;
19222 
input [31:0] DIB;
19223 
input [3:0] DIPA;
19224 
input [3:0] DIPB;
19225 
input ENA;
19226 
input ENB;
19227 
input REGCEA;
19228 
input REGCEB;
19229 
input SSRA;
19230 
input SSRB;
19231 
input [3:0] WEA;
19232 
input [3:0] WEB;
19233 
endmodule
19234 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19235 
module RAMB4_S16_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19236 
parameter SIM_COLLISION_CHECK = "ALL";
19237 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19238 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19239 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19240 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19241 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19242 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19243 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19244 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19245 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19246 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19247 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19248 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19249 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19250 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19251 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19252 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19253 
output [15:0] DOA;
19254 
output [15:0] DOB;
19255 
input [7:0] ADDRA;
19256 
input [7:0] ADDRB;
19257 
input CLKA;
19258 
input CLKB;
19259 
input [15:0] DIA;
19260 
input [15:0] DIB;
19261 
input ENA;
19262 
input ENB;
19263 
input RSTA;
19264 
input RSTB;
19265 
input WEA;
19266 
input WEB;
19267 
endmodule
19268 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19269 
module RAMB4_S16 (DO, ADDR, CLK, DI, EN, RST, WE);
19270 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19271 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19272 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19273 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19274 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19275 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19276 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19277 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19278 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19279 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19280 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19281 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19282 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19283 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19284 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19285 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19286 
output [15:0] DO;
19287 
input [7:0] ADDR;
19288 
input CLK;
19289 
input [15:0] DI;
19290 
input EN;
19291 
input RST;
19292 
input WE;
19293 
endmodule
19294 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19295 
module RAMB4_S1_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19296 
parameter SIM_COLLISION_CHECK = "ALL";
19297 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19298 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19299 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19300 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19301 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19302 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19303 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19304 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19305 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19306 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19307 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19308 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19309 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19310 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19311 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19312 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19313 
output [0:0] DOA;
19314 
output [15:0] DOB;
19315 
input [11:0] ADDRA;
19316 
input [7:0] ADDRB;
19317 
input CLKA;
19318 
input CLKB;
19319 
input [0:0] DIA;
19320 
input [15:0] DIB;
19321 
input ENA;
19322 
input ENB;
19323 
input RSTA;
19324 
input RSTB;
19325 
input WEA;
19326 
input WEB;
19327 
endmodule
19328 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19329 
module RAMB4_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19330 
parameter SIM_COLLISION_CHECK = "ALL";
19331 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19332 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19333 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19334 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19335 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19336 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19337 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19338 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19339 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19340 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19341 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19342 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19343 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19344 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19345 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19346 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19347 
output [0:0] DOA;
19348 
output [0:0] DOB;
19349 
input [11:0] ADDRA;
19350 
input [11:0] ADDRB;
19351 
input CLKA;
19352 
input CLKB;
19353 
input [0:0] DIA;
19354 
input [0:0] DIB;
19355 
input ENA;
19356 
input ENB;
19357 
input RSTA;
19358 
input RSTB;
19359 
input WEA;
19360 
input WEB;
19361 
endmodule
19362 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19363 
module RAMB4_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19364 
parameter SIM_COLLISION_CHECK = "ALL";
19365 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19366 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19367 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19368 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19369 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19370 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19371 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19372 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19373 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19374 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19375 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19376 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19377 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19378 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19379 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19380 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19381 
output [0:0] DOA;
19382 
output [1:0] DOB;
19383 
input [11:0] ADDRA;
19384 
input [10:0] ADDRB;
19385 
input CLKA;
19386 
input CLKB;
19387 
input [0:0] DIA;
19388 
input [1:0] DIB;
19389 
input ENA;
19390 
input ENB;
19391 
input RSTA;
19392 
input RSTB;
19393 
input WEA;
19394 
input WEB;
19395 
endmodule
19396 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19397 
module RAMB4_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19398 
parameter SIM_COLLISION_CHECK = "ALL";
19399 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19400 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19401 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19402 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19403 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19404 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19405 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19406 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19407 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19408 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19409 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19410 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19411 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19412 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19413 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19414 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19415 
output [0:0] DOA;
19416 
output [3:0] DOB;
19417 
input [11:0] ADDRA;
19418 
input [9:0] ADDRB;
19419 
input CLKA;
19420 
input CLKB;
19421 
input [0:0] DIA;
19422 
input [3:0] DIB;
19423 
input ENA;
19424 
input ENB;
19425 
input RSTA;
19426 
input RSTB;
19427 
input WEA;
19428 
input WEB;
19429 
endmodule
19430 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19431 
module RAMB4_S1_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19432 
parameter SIM_COLLISION_CHECK = "ALL";
19433 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19434 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19435 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19436 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19437 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19438 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19439 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19440 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19441 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19442 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19443 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19444 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19445 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19446 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19447 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19448 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19449 
output [0:0] DOA;
19450 
output [7:0] DOB;
19451 
input [11:0] ADDRA;
19452 
input [8:0] ADDRB;
19453 
input CLKA;
19454 
input CLKB;
19455 
input [0:0] DIA;
19456 
input [7:0] DIB;
19457 
input ENA;
19458 
input ENB;
19459 
input RSTA;
19460 
input RSTB;
19461 
input WEA;
19462 
input WEB;
19463 
endmodule
19464 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19465 
module RAMB4_S1 (DO, ADDR, CLK, DI, EN, RST, WE);
19466 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19467 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19468 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19469 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19470 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19471 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19472 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19473 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19474 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19475 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19476 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19477 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19478 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19479 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19480 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19481 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19482 
output [0:0] DO;
19483 
input [11:0] ADDR;
19484 
input CLK;
19485 
input [0:0] DI;
19486 
input EN;
19487 
input RST;
19488 
input WE;
19489 
endmodule
19490 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19491 
module RAMB4_S2_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19492 
parameter SIM_COLLISION_CHECK = "ALL";
19493 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19494 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19495 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19496 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19497 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19498 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19499 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19500 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19501 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19502 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19503 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19504 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19505 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19506 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19507 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19508 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19509 
output [1:0] DOA;
19510 
output [15:0] DOB;
19511 
input [10:0] ADDRA;
19512 
input [7:0] ADDRB;
19513 
input CLKA;
19514 
input CLKB;
19515 
input [1:0] DIA;
19516 
input [15:0] DIB;
19517 
input ENA;
19518 
input ENB;
19519 
input RSTA;
19520 
input RSTB;
19521 
input WEA;
19522 
input WEB;
19523 
endmodule
19524 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19525 
module RAMB4_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19526 
parameter SIM_COLLISION_CHECK = "ALL";
19527 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19528 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19529 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19530 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19531 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19532 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19533 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19534 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19535 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19536 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19537 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19538 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19539 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19540 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19541 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19542 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19543 
output [1:0] DOA;
19544 
output [1:0] DOB;
19545 
input [10:0] ADDRA;
19546 
input [10:0] ADDRB;
19547 
input CLKA;
19548 
input CLKB;
19549 
input [1:0] DIA;
19550 
input [1:0] DIB;
19551 
input ENA;
19552 
input ENB;
19553 
input RSTA;
19554 
input RSTB;
19555 
input WEA;
19556 
input WEB;
19557 
endmodule
19558 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19559 
module RAMB4_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19560 
parameter SIM_COLLISION_CHECK = "ALL";
19561 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19562 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19563 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19564 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19565 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19566 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19567 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19568 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19569 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19570 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19571 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19572 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19573 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19574 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19575 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19576 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19577 
output [1:0] DOA;
19578 
output [3:0] DOB;
19579 
input [10:0] ADDRA;
19580 
input [9:0] ADDRB;
19581 
input CLKA;
19582 
input CLKB;
19583 
input [1:0] DIA;
19584 
input [3:0] DIB;
19585 
input ENA;
19586 
input ENB;
19587 
input RSTA;
19588 
input RSTB;
19589 
input WEA;
19590 
input WEB;
19591 
endmodule
19592 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19593 
module RAMB4_S2_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19594 
parameter SIM_COLLISION_CHECK = "ALL";
19595 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19596 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19597 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19598 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19599 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19600 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19601 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19602 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19603 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19604 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19605 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19606 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19607 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19608 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19609 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19610 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19611 
output [1:0] DOA;
19612 
output [7:0] DOB;
19613 
input [10:0] ADDRA;
19614 
input [8:0] ADDRB;
19615 
input CLKA;
19616 
input CLKB;
19617 
input [1:0] DIA;
19618 
input [7:0] DIB;
19619 
input ENA;
19620 
input ENB;
19621 
input RSTA;
19622 
input RSTB;
19623 
input WEA;
19624 
input WEB;
19625 
endmodule
19626 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19627 
module RAMB4_S2 (DO, ADDR, CLK, DI, EN, RST, WE);
19628 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19629 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19630 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19631 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19632 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19633 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19634 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19635 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19636 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19637 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19638 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19639 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19640 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19641 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19642 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19643 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19644 
output [1:0] DO;
19645 
input [10:0] ADDR;
19646 
input CLK;
19647 
input [1:0] DI;
19648 
input EN;
19649 
input RST;
19650 
input WE;
19651 
endmodule
19652 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19653 
module RAMB4_S4_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19654 
parameter SIM_COLLISION_CHECK = "ALL";
19655 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19656 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19657 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19658 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19659 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19660 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19661 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19662 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19663 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19664 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19665 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19666 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19667 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19668 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19669 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19670 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19671 
output [3:0] DOA;
19672 
output [15:0] DOB;
19673 
input [9:0] ADDRA;
19674 
input [7:0] ADDRB;
19675 
input CLKA;
19676 
input CLKB;
19677 
input [3:0] DIA;
19678 
input [15:0] DIB;
19679 
input ENA;
19680 
input ENB;
19681 
input RSTA;
19682 
input RSTB;
19683 
input WEA;
19684 
input WEB;
19685 
endmodule
19686 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19687 
module RAMB4_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19688 
parameter SIM_COLLISION_CHECK = "ALL";
19689 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19690 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19691 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19692 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19693 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19694 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19695 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19696 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19697 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19698 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19699 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19700 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19701 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19702 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19703 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19704 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19705 
output [3:0] DOA;
19706 
output [3:0] DOB;
19707 
input [9:0] ADDRA;
19708 
input [9:0] ADDRB;
19709 
input CLKA;
19710 
input CLKB;
19711 
input [3:0] DIA;
19712 
input [3:0] DIB;
19713 
input ENA;
19714 
input ENB;
19715 
input RSTA;
19716 
input RSTB;
19717 
input WEA;
19718 
input WEB;
19719 
endmodule
19720 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19721 
module RAMB4_S4_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19722 
parameter SIM_COLLISION_CHECK = "ALL";
19723 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19724 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19725 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19726 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19727 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19728 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19729 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19730 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19731 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19732 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19733 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19734 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19735 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19736 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19737 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19738 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19739 
output [3:0] DOA;
19740 
output [7:0] DOB;
19741 
input [9:0] ADDRA;
19742 
input [8:0] ADDRB;
19743 
input CLKA;
19744 
input CLKB;
19745 
input [3:0] DIA;
19746 
input [7:0] DIB;
19747 
input ENA;
19748 
input ENB;
19749 
input RSTA;
19750 
input RSTB;
19751 
input WEA;
19752 
input WEB;
19753 
endmodule
19754 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19755 
module RAMB4_S4 (DO, ADDR, CLK, DI, EN, RST, WE);
19756 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19757 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19758 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19759 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19760 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19761 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19762 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19763 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19764 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19765 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19766 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19767 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19768 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19769 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19770 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19771 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19772 
output [3:0] DO;
19773 
input [9:0] ADDR;
19774 
input CLK;
19775 
input [3:0] DI;
19776 
input EN;
19777 
input RST;
19778 
input WE;
19779 
endmodule
19780 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19781 
module RAMB4_S8_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19782 
parameter SIM_COLLISION_CHECK = "ALL";
19783 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19784 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19785 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19786 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19787 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19788 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19789 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19790 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19791 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19792 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19793 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19794 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19795 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19796 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19797 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19798 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19799 
output [7:0] DOA;
19800 
output [15:0] DOB;
19801 
input [8:0] ADDRA;
19802 
input [7:0] ADDRB;
19803 
input CLKA;
19804 
input CLKB;
19805 
input [7:0] DIA;
19806 
input [15:0] DIB;
19807 
input ENA;
19808 
input ENB;
19809 
input RSTA;
19810 
input RSTB;
19811 
input WEA;
19812 
input WEB;
19813 
endmodule
19814 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19815 
module RAMB4_S8_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
19816 
parameter SIM_COLLISION_CHECK = "ALL";
19817 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19818 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19819 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19820 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19821 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19822 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19823 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19824 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19825 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19826 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19827 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19828 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19829 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19830 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19831 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19832 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19833 
output [7:0] DOA;
19834 
output [7:0] DOB;
19835 
input [8:0] ADDRA;
19836 
input [8:0] ADDRB;
19837 
input CLKA;
19838 
input CLKB;
19839 
input [7:0] DIA;
19840 
input [7:0] DIB;
19841 
input ENA;
19842 
input ENB;
19843 
input RSTA;
19844 
input RSTB;
19845 
input WEA;
19846 
input WEB;
19847 
endmodule
19848 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19849 
module RAMB4_S8 (DO, ADDR, CLK, DI, EN, RST, WE);
19850 
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19851 
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19852 
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19853 
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19854 
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19855 
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19856 
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19857 
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19858 
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19859 
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19860 
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19861 
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19862 
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19863 
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19864 
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19865 
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19866 
output [7:0] DO;
19867 
input [8:0] ADDR;
19868 
input CLK;
19869 
input [7:0] DI;
19870 
input EN;
19871 
input RST;
19872 
input WE;
19873 
endmodule
19874 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19875 
module ROM128X1 (O, A0, A1, A2, A3, A4, A5, A6);
19876 
parameter INIT = 128'h00000000000000000000000000000000;
19877 
output O;
19878 
input A0;
19879 
input A1;
19880 
input A2;
19881 
input A3;
19882 
input A4;
19883 
input A5;
19884 
input A6;
19885 
endmodule
19886 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19887 
module ROM16X1 (O, A0, A1, A2, A3);
19888 
parameter INIT = 16'h0000;
19889 
output O;
19890 
input A0;
19891 
input A1;
19892 
input A2;
19893 
input A3;
19894 
endmodule
19895 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19896 
module ROM256X1 (O, A0, A1, A2, A3, A4, A5, A6, A7);
19897 
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19898 
output O;
19899 
input A0;
19900 
input A1;
19901 
input A2;
19902 
input A3;
19903 
input A4;
19904 
input A5;
19905 
input A6;
19906 
input A7;
19907 
endmodule
19908 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19909 
module ROM32X1 (O, A0, A1, A2, A3, A4);
19910 
parameter INIT = 32'h00000000;
19911 
output O;
19912 
input A0;
19913 
input A1;
19914 
input A2;
19915 
input A3;
19916 
input A4;
19917 
endmodule
19918 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19919 
module ROM64X1 (O, A0, A1, A2, A3, A4, A5);
19920 
parameter INIT = 64'h0000000000000000;
19921 
output O;
19922 
input A0;
19923 
input A1;
19924 
input A2;
19925 
input A3;
19926 
input A4;
19927 
input A5;
19928 
endmodule
19929 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19930 
module SIM_CONFIG_S3A (CSOB, DONE, CCLK, D, DCMLOCK, CSIB, INITB, M, PROGB, RDWRB);
19931 
parameter DEVICE_ID = 32'h0;
19932 
output CSOB;
19933 
inout DONE;
19934 
inout [7:0] D;
19935 
inout INITB;
19936 
input CCLK;
19937 
input DCMLOCK;
19938 
input CSIB;
19939 
input [2:0] M;
19940 
input PROGB;
19941 
input RDWRB;
19942 
endmodule
19943 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19944 
module SIM_CONFIG_V5 (BUSY, CSOB, DONE, CCLK, CSB, D, DCMLOCK, INITB, M, PROGB, RDWRB);
19945 
parameter DEVICE_ID = 32'h0;
19946 
output BUSY;
19947 
output CSOB;
19948 
inout DONE;
19949 
inout [31:0] D;
19950 
inout INITB;
19951 
input CCLK;
19952 
input CSB;
19953 
input DCMLOCK;
19954 
input [2:0] M;
19955 
input PROGB;
19956 
input RDWRB;
19957 
endmodule
19958 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19959 
module SPI_ACCESS (MISO, CLK, CSB, MOSI);
19960 
parameter SIM_DELAY_TYPE = "SCALED";
19961 
parameter SIM_DEVICE = "3S1400AN";
19962 
parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
19963 
parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
19964 
parameter SIM_MEM_FILE = "NONE";
19965 
output MISO;
19966 
input CLK;
19967 
input CSB;
19968 
input MOSI;
19969 
endmodule
19970 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19971 
module SRL16_1 (Q, A0, A1, A2, A3, CLK, D);
19972 
parameter INIT = 16'h0000;
19973 
output Q;
19974 
input A0;
19975 
input A1;
19976 
input A2;
19977 
input A3;
19978 
input CLK;
19979 
input D;
19980 
endmodule
19981 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19982 
module SRL16E_1 (Q, A0, A1, A2, A3, CE, CLK, D);
19983 
parameter INIT = 16'h0000;
19984 
output Q;
19985 
input A0;
19986 
input A1;
19987 
input A2;
19988 
input A3;
19989 
input CE;
19990 
input CLK;
19991 
input D;
19992 
endmodule
19993 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
19994 
module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
19995 
parameter INIT = 16'h0000;
19996 
output Q;
19997 
input A0;
19998 
input A1;
19999 
input A2;
20000 
input A3;
20001 
input CE;
20002 
input CLK;
20003 
input D;
20004 
endmodule
20005 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20006 
module SRL16 (Q, A0, A1, A2, A3, CLK, D);
20007 
parameter INIT = 16'h0000;
20008 
output Q;
20009 
input A0;
20010 
input A1;
20011 
input A2;
20012 
input A3;
20013 
input CLK;
20014 
input D;
20015 
endmodule
20016 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20017 
module SRLC16_1 (Q, Q15, A0, A1, A2, A3, CLK, D);
20018 
parameter INIT = 16'h0000;
20019 
output Q;
20020 
output Q15;
20021 
input A0;
20022 
input A1;
20023 
input A2;
20024 
input A3;
20025 
input CLK;
20026 
input D;
20027 
endmodule
20028 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20029 
module SRLC16E_1 (Q, Q15, A0, A1, A2, A3, CE, CLK, D);
20030 
parameter INIT = 16'h0000;
20031 
output Q;
20032 
output Q15;
20033 
input A0;
20034 
input A1;
20035 
input A2;
20036 
input A3;
20037 
input CE;
20038 
input CLK;
20039 
input D;
20040 
endmodule
20041 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20042 
module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D);
20043 
parameter INIT = 16'h0000;
20044 
output Q;
20045 
output Q15;
20046 
input A0;
20047 
input A1;
20048 
input A2;
20049 
input A3;
20050 
input CE;
20051 
input CLK;
20052 
input D;
20053 
endmodule
20054 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20055 
module SRLC16 (Q, Q15, A0, A1, A2, A3, CLK, D);
20056 
parameter INIT = 16'h0000;
20057 
output Q;
20058 
output Q15;
20059 
input A0;
20060 
input A1;
20061 
input A2;
20062 
input A3;
20063 
input CLK;
20064 
input D;
20065 
endmodule
20066 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20067 
module SRLC32E (Q, Q31, A, CE, CLK, D);
20068 
parameter INIT = 32'h00000000;
20069 
output Q;
20070 
output Q31;
20071 
input [4:0] A;
20072 
input CE;
20073 
input CLK;
20074 
input D;
20075 
endmodule
20076 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20077 
module STARTUP_FPGACORE (CLK, GSR);
20078 
input CLK;
20079 
input GSR;
20080 
endmodule
20081 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20082 
module STARTUP_SPARTAN2 (CLK, GSR, GTS);
20083 
input CLK;
20084 
input GSR;
20085 
input GTS;
20086 
endmodule
20087 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20088 
module STARTUP_SPARTAN3A (CLK, GSR, GTS);
20089 
input CLK;
20090 
input GSR;
20091 
input GTS;
20092 
endmodule
20093 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20094 
module STARTUP_SPARTAN3E (CLK, GSR, GTS, MBT);
20095 
input CLK;
20096 
input GSR;
20097 
input GTS;
20098 
input MBT;
20099 
endmodule
20100 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20101 
module STARTUP_SPARTAN3 (CLK, GSR, GTS);
20102 
input CLK;
20103 
input GSR;
20104 
input GTS;
20105 
endmodule
20106 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20107 
module STARTUP_VIRTEX2 (CLK, GSR, GTS);
20108 
input CLK;
20109 
input GSR;
20110 
input GTS;
20111 
endmodule
20112 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20113 
module STARTUP_VIRTEX4 (EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
20114 
output EOS;
20115 
input CLK;
20116 
input GSR;
20117 
input GTS;
20118 
input USRCCLKO;
20119 
input USRCCLKTS;
20120 
input USRDONEO;
20121 
input USRDONETS;
20122 
endmodule
20123 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20124 
module STARTUP_VIRTEX5 (CFGCLK, CFGMCLK, DINSPI, EOS, TCKSPI, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
20125 
output CFGCLK;
20126 
output CFGMCLK;
20127 
output DINSPI;
20128 
output EOS;
20129 
output TCKSPI;
20130 
input CLK;
20131 
input GSR;
20132 
input GTS;
20133 
input USRCCLKO;
20134 
input USRCCLKTS;
20135 
input USRDONEO;
20136 
input USRDONETS;
20137 
endmodule
20138 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20139 
module STARTUP_VIRTEX (CLK, GSR, GTS);
20140 
input CLK;
20141 
input GSR;
20142 
input GTS;
20143 
endmodule
20144 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20145 
module SYSMON (ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, CONVST, CONVSTCLK, DADDR, DCLK, DEN, DI, DWE, RESET, VAUXN, VAUXP, VN, VP);
20146 
parameter INIT_40 = 16'h0;
20147 
parameter INIT_41 = 16'h0;
20148 
parameter INIT_42 = 16'h0800;
20149 
parameter INIT_43 = 16'h0;
20150 
parameter INIT_44 = 16'h0;
20151 
parameter INIT_45 = 16'h0;
20152 
parameter INIT_46 = 16'h0;
20153 
parameter INIT_47 = 16'h0;
20154 
parameter INIT_48 = 16'h0;
20155 
parameter INIT_49 = 16'h0;
20156 
parameter INIT_4A = 16'h0;
20157 
parameter INIT_4B = 16'h0;
20158 
parameter INIT_4C = 16'h0;
20159 
parameter INIT_4D = 16'h0;
20160 
parameter INIT_4E = 16'h0;
20161 
parameter INIT_4F = 16'h0;
20162 
parameter INIT_50 = 16'h0;
20163 
parameter INIT_51 = 16'h0;
20164 
parameter INIT_52 = 16'h0;
20165 
parameter INIT_53 = 16'h0;
20166 
parameter INIT_54 = 16'h0;
20167 
parameter INIT_55 = 16'h0;
20168 
parameter INIT_56 = 16'h0;
20169 
parameter INIT_57 = 16'h0;
20170 
parameter SIM_MONITOR_FILE = "design.txt";
20171 
output [2:0] ALM;
20172 
output BUSY;
20173 
output [4:0] CHANNEL;
20174 
output [15:0] DO;
20175 
output DRDY;
20176 
output EOC;
20177 
output EOS;
20178 
output JTAGBUSY;
20179 
output JTAGLOCKED;
20180 
output JTAGMODIFIED;
20181 
output OT;
20182 
input CONVST;
20183 
input CONVSTCLK;
20184 
input [6:0] DADDR;
20185 
input DCLK;
20186 
input DEN;
20187 
input [15:0] DI;
20188 
input DWE;
20189 
input RESET;
20190 
input [15:0] VAUXN;
20191 
input [15:0] VAUXP;
20192 
input VN;
20193 
input VP;
20194 
endmodule
20195 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20196 
module TBLOCK ();
20197 
endmodule
20198 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20199 
module TEMAC (DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXD, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATS, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXD, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC0PHYTXGMIIMIICLKOUT, EMAC0SPEEDIS10100, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXD, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATS, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXD, EMAC1PHYTXEN, EMAC1PHYTXER, EMAC1PHYTXGMIIMIICLKOUT, EMAC1SPEEDIS10100, EMACDCRACK, EMACDCRDBUS, HOSTMIIMRDY, HOSTRDDATA, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXD, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXD, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXIFGDELAY, CLIENTEMAC1TXUNDERRUN, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTADDR, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTOPCODE, HOSTREQ, HOSTWRDATA, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0PHYAD, PHYEMAC0RXBUFERR, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCLKCORCNT, PHYEMAC0RXCOMMADET, PHYEMAC0RXD, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXLOSSOFSYNC, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC0TXGMIIMIICLKIN, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1PHYAD, PHYEMAC1RXBUFERR, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCLKCORCNT, PHYEMAC1RXCOMMADET, PHYEMAC1RXD, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXLOSSOFSYNC, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, PHYEMAC1TXGMIIMIICLKIN, RESET);
20200 
parameter EMAC0_1000BASEX_ENABLE = "FALSE";
20201 
parameter EMAC0_ADDRFILTER_ENABLE = "FALSE";
20202 
parameter EMAC0_BYTEPHY = "FALSE";
20203 
parameter EMAC0_CONFIGVEC_79 = "FALSE";
20204 
parameter EMAC0_GTLOOPBACK = "FALSE";
20205 
parameter EMAC0_HOST_ENABLE = "FALSE";
20206 
parameter EMAC0_LTCHECK_DISABLE = "FALSE";
20207 
parameter EMAC0_MDIO_ENABLE = "FALSE";
20208 
parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE";
20209 
parameter EMAC0_PHYISOLATE = "FALSE";
20210 
parameter EMAC0_PHYLOOPBACKMSB = "FALSE";
20211 
parameter EMAC0_PHYPOWERDOWN = "FALSE";
20212 
parameter EMAC0_PHYRESET = "FALSE";
20213 
parameter EMAC0_RGMII_ENABLE = "FALSE";
20214 
parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE";
20215 
parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE";
20216 
parameter EMAC0_RXHALFDUPLEX = "FALSE";
20217 
parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE";
20218 
parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE";
20219 
parameter EMAC0_RXRESET = "FALSE";
20220 
parameter EMAC0_RXVLAN_ENABLE = "FALSE";
20221 
parameter EMAC0_RX_ENABLE = "FALSE";
20222 
parameter EMAC0_SGMII_ENABLE = "FALSE";
20223 
parameter EMAC0_SPEED_LSB = "FALSE";
20224 
parameter EMAC0_SPEED_MSB = "FALSE";
20225 
parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE";
20226 
parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE";
20227 
parameter EMAC0_TXHALFDUPLEX = "FALSE";
20228 
parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE";
20229 
parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE";
20230 
parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE";
20231 
parameter EMAC0_TXRESET = "FALSE";
20232 
parameter EMAC0_TXVLAN_ENABLE = "FALSE";
20233 
parameter EMAC0_TX_ENABLE = "FALSE";
20234 
parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE";
20235 
parameter EMAC0_USECLKEN = "FALSE";
20236 
parameter EMAC1_1000BASEX_ENABLE = "FALSE";
20237 
parameter EMAC1_ADDRFILTER_ENABLE = "FALSE";
20238 
parameter EMAC1_BYTEPHY = "FALSE";
20239 
parameter EMAC1_CONFIGVEC_79 = "FALSE";
20240 
parameter EMAC1_GTLOOPBACK = "FALSE";
20241 
parameter EMAC1_HOST_ENABLE = "FALSE";
20242 
parameter EMAC1_LTCHECK_DISABLE = "FALSE";
20243 
parameter EMAC1_MDIO_ENABLE = "FALSE";
20244 
parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE";
20245 
parameter EMAC1_PHYISOLATE = "FALSE";
20246 
parameter EMAC1_PHYLOOPBACKMSB = "FALSE";
20247 
parameter EMAC1_PHYPOWERDOWN = "FALSE";
20248 
parameter EMAC1_PHYRESET = "FALSE";
20249 
parameter EMAC1_RGMII_ENABLE = "FALSE";
20250 
parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE";
20251 
parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE";
20252 
parameter EMAC1_RXHALFDUPLEX = "FALSE";
20253 
parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE";
20254 
parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE";
20255 
parameter EMAC1_RXRESET = "FALSE";
20256 
parameter EMAC1_RXVLAN_ENABLE = "FALSE";
20257 
parameter EMAC1_RX_ENABLE = "FALSE";
20258 
parameter EMAC1_SGMII_ENABLE = "FALSE";
20259 
parameter EMAC1_SPEED_LSB = "FALSE";
20260 
parameter EMAC1_SPEED_MSB = "FALSE";
20261 
parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE";
20262 
parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE";
20263 
parameter EMAC1_TXHALFDUPLEX = "FALSE";
20264 
parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE";
20265 
parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE";
20266 
parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE";
20267 
parameter EMAC1_TXRESET = "FALSE";
20268 
parameter EMAC1_TXVLAN_ENABLE = "FALSE";
20269 
parameter EMAC1_TX_ENABLE = "FALSE";
20270 
parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE";
20271 
parameter EMAC1_USECLKEN = "FALSE";
20272 
parameter [0:7] EMAC0_DCRBASEADDR = 8'h00;
20273 
parameter [0:7] EMAC1_DCRBASEADDR = 8'h00;
20274 
parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000;
20275 
parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000;
20276 
parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000;
20277 
parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000;
20278 
parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000;
20279 
parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000;
20280 
output DCRHOSTDONEIR;
20281 
output EMAC0CLIENTANINTERRUPT;
20282 
output EMAC0CLIENTRXBADFRAME;
20283 
output EMAC0CLIENTRXCLIENTCLKOUT;
20284 
output [15:0] EMAC0CLIENTRXD;
20285 
output EMAC0CLIENTRXDVLD;
20286 
output EMAC0CLIENTRXDVLDMSW;
20287 
output EMAC0CLIENTRXFRAMEDROP;
20288 
output EMAC0CLIENTRXGOODFRAME;
20289 
output [6:0] EMAC0CLIENTRXSTATS;
20290 
output EMAC0CLIENTRXSTATSBYTEVLD;
20291 
output EMAC0CLIENTRXSTATSVLD;
20292 
output EMAC0CLIENTTXACK;
20293 
output EMAC0CLIENTTXCLIENTCLKOUT;
20294 
output EMAC0CLIENTTXCOLLISION;
20295 
output EMAC0CLIENTTXRETRANSMIT;
20296 
output EMAC0CLIENTTXSTATS;
20297 
output EMAC0CLIENTTXSTATSBYTEVLD;
20298 
output EMAC0CLIENTTXSTATSVLD;
20299 
output EMAC0PHYENCOMMAALIGN;
20300 
output EMAC0PHYLOOPBACKMSB;
20301 
output EMAC0PHYMCLKOUT;
20302 
output EMAC0PHYMDOUT;
20303 
output EMAC0PHYMDTRI;
20304 
output EMAC0PHYMGTRXRESET;
20305 
output EMAC0PHYMGTTXRESET;
20306 
output EMAC0PHYPOWERDOWN;
20307 
output EMAC0PHYSYNCACQSTATUS;
20308 
output EMAC0PHYTXCHARDISPMODE;
20309 
output EMAC0PHYTXCHARDISPVAL;
20310 
output EMAC0PHYTXCHARISK;
20311 
output EMAC0PHYTXCLK;
20312 
output [7:0] EMAC0PHYTXD;
20313 
output EMAC0PHYTXEN;
20314 
output EMAC0PHYTXER;
20315 
output EMAC0PHYTXGMIIMIICLKOUT;
20316 
output EMAC0SPEEDIS10100;
20317 
output EMAC1CLIENTANINTERRUPT;
20318 
output EMAC1CLIENTRXBADFRAME;
20319 
output EMAC1CLIENTRXCLIENTCLKOUT;
20320 
output [15:0] EMAC1CLIENTRXD;
20321 
output EMAC1CLIENTRXDVLD;
20322 
output EMAC1CLIENTRXDVLDMSW;
20323 
output EMAC1CLIENTRXFRAMEDROP;
20324 
output EMAC1CLIENTRXGOODFRAME;
20325 
output [6:0] EMAC1CLIENTRXSTATS;
20326 
output EMAC1CLIENTRXSTATSBYTEVLD;
20327 
output EMAC1CLIENTRXSTATSVLD;
20328 
output EMAC1CLIENTTXACK;
20329 
output EMAC1CLIENTTXCLIENTCLKOUT;
20330 
output EMAC1CLIENTTXCOLLISION;
20331 
output EMAC1CLIENTTXRETRANSMIT;
20332 
output EMAC1CLIENTTXSTATS;
20333 
output EMAC1CLIENTTXSTATSBYTEVLD;
20334 
output EMAC1CLIENTTXSTATSVLD;
20335 
output EMAC1PHYENCOMMAALIGN;
20336 
output EMAC1PHYLOOPBACKMSB;
20337 
output EMAC1PHYMCLKOUT;
20338 
output EMAC1PHYMDOUT;
20339 
output EMAC1PHYMDTRI;
20340 
output EMAC1PHYMGTRXRESET;
20341 
output EMAC1PHYMGTTXRESET;
20342 
output EMAC1PHYPOWERDOWN;
20343 
output EMAC1PHYSYNCACQSTATUS;
20344 
output EMAC1PHYTXCHARDISPMODE;
20345 
output EMAC1PHYTXCHARDISPVAL;
20346 
output EMAC1PHYTXCHARISK;
20347 
output EMAC1PHYTXCLK;
20348 
output [7:0] EMAC1PHYTXD;
20349 
output EMAC1PHYTXEN;
20350 
output EMAC1PHYTXER;
20351 
output EMAC1PHYTXGMIIMIICLKOUT;
20352 
output EMAC1SPEEDIS10100;
20353 
output EMACDCRACK;
20354 
output [0:31] EMACDCRDBUS;
20355 
output HOSTMIIMRDY;
20356 
output [31:0] HOSTRDDATA;
20357 
input CLIENTEMAC0DCMLOCKED;
20358 
input CLIENTEMAC0PAUSEREQ;
20359 
input [15:0] CLIENTEMAC0PAUSEVAL;
20360 
input CLIENTEMAC0RXCLIENTCLKIN;
20361 
input CLIENTEMAC0TXCLIENTCLKIN;
20362 
input [15:0] CLIENTEMAC0TXD;
20363 
input CLIENTEMAC0TXDVLD;
20364 
input CLIENTEMAC0TXDVLDMSW;
20365 
input CLIENTEMAC0TXFIRSTBYTE;
20366 
input [7:0] CLIENTEMAC0TXIFGDELAY;
20367 
input CLIENTEMAC0TXUNDERRUN;
20368 
input CLIENTEMAC1DCMLOCKED;
20369 
input CLIENTEMAC1PAUSEREQ;
20370 
input [15:0] CLIENTEMAC1PAUSEVAL;
20371 
input CLIENTEMAC1RXCLIENTCLKIN;
20372 
input CLIENTEMAC1TXCLIENTCLKIN;
20373 
input [15:0] CLIENTEMAC1TXD;
20374 
input CLIENTEMAC1TXDVLD;
20375 
input CLIENTEMAC1TXDVLDMSW;
20376 
input CLIENTEMAC1TXFIRSTBYTE;
20377 
input [7:0] CLIENTEMAC1TXIFGDELAY;
20378 
input CLIENTEMAC1TXUNDERRUN;
20379 
input [0:9] DCREMACABUS;
20380 
input DCREMACCLK;
20381 
input [0:31] DCREMACDBUS;
20382 
input DCREMACENABLE;
20383 
input DCREMACREAD;
20384 
input DCREMACWRITE;
20385 
input [9:0] HOSTADDR;
20386 
input HOSTCLK;
20387 
input HOSTEMAC1SEL;
20388 
input HOSTMIIMSEL;
20389 
input [1:0] HOSTOPCODE;
20390 
input HOSTREQ;
20391 
input [31:0] HOSTWRDATA;
20392 
input PHYEMAC0COL;
20393 
input PHYEMAC0CRS;
20394 
input PHYEMAC0GTXCLK;
20395 
input PHYEMAC0MCLKIN;
20396 
input PHYEMAC0MDIN;
20397 
input PHYEMAC0MIITXCLK;
20398 
input [4:0] PHYEMAC0PHYAD;
20399 
input PHYEMAC0RXBUFERR;
20400 
input [1:0] PHYEMAC0RXBUFSTATUS;
20401 
input PHYEMAC0RXCHARISCOMMA;
20402 
input PHYEMAC0RXCHARISK;
20403 
input PHYEMAC0RXCHECKINGCRC;
20404 
input PHYEMAC0RXCLK;
20405 
input [2:0] PHYEMAC0RXCLKCORCNT;
20406 
input PHYEMAC0RXCOMMADET;
20407 
input [7:0] PHYEMAC0RXD;
20408 
input PHYEMAC0RXDISPERR;
20409 
input PHYEMAC0RXDV;
20410 
input PHYEMAC0RXER;
20411 
input [1:0] PHYEMAC0RXLOSSOFSYNC;
20412 
input PHYEMAC0RXNOTINTABLE;
20413 
input PHYEMAC0RXRUNDISP;
20414 
input PHYEMAC0SIGNALDET;
20415 
input PHYEMAC0TXBUFERR;
20416 
input PHYEMAC0TXGMIIMIICLKIN;
20417 
input PHYEMAC1COL;
20418 
input PHYEMAC1CRS;
20419 
input PHYEMAC1GTXCLK;
20420 
input PHYEMAC1MCLKIN;
20421 
input PHYEMAC1MDIN;
20422 
input PHYEMAC1MIITXCLK;
20423 
input [4:0] PHYEMAC1PHYAD;
20424 
input PHYEMAC1RXBUFERR;
20425 
input [1:0] PHYEMAC1RXBUFSTATUS;
20426 
input PHYEMAC1RXCHARISCOMMA;
20427 
input PHYEMAC1RXCHARISK;
20428 
input PHYEMAC1RXCHECKINGCRC;
20429 
input PHYEMAC1RXCLK;
20430 
input [2:0] PHYEMAC1RXCLKCORCNT;
20431 
input PHYEMAC1RXCOMMADET;
20432 
input [7:0] PHYEMAC1RXD;
20433 
input PHYEMAC1RXDISPERR;
20434 
input PHYEMAC1RXDV;
20435 
input PHYEMAC1RXER;
20436 
input [1:0] PHYEMAC1RXLOSSOFSYNC;
20437 
input PHYEMAC1RXNOTINTABLE;
20438 
input PHYEMAC1RXRUNDISP;
20439 
input PHYEMAC1SIGNALDET;
20440 
input PHYEMAC1TXBUFERR;
20441 
input PHYEMAC1TXGMIIMIICLKIN;
20442 
input RESET;
20443 
endmodule
20444 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20445 
module TIMEGRP ();
20446 
endmodule
20447 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20448 
module TIMESPEC ();
20449 
endmodule
20450 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20451 
module USR_ACCESS_VIRTEX4 (DATA, DATAVALID);
20452 
output [31:0] DATA;
20453 
output DATAVALID;
20454 
endmodule
20455 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20456 
module USR_ACCESS_VIRTEX5 (CFGCLK, DATA, DATAVALID);
20457 
output CFGCLK;
20458 
output [31:0] DATA;
20459 
output DATAVALID;
20460 
endmodule
20461 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20462 
module VCC (P);
20463 
output P;
20464 
endmodule
20465 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20466 
module WIREAND (I);
20467 
input I;
20468 
endmodule
20469 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20470 
module XNOR2 (O, I0, I1);
20471 
output O;
20472 
input I0;
20473 
input I1;
20474 
endmodule
20475 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20476 
module XNOR3 (O, I0, I1, I2);
20477 
output O;
20478 
input I0;
20479 
input I1;
20480 
input I2;
20481 
endmodule
20482 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20483 
module XNOR4 (O, I0, I1, I2, I3);
20484 
output O;
20485 
input I0;
20486 
input I1;
20487 
input I2;
20488 
input I3;
20489 
endmodule
20490 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20491 
module XNOR5 (O, I0, I1, I2, I3, I4);
20492 
output O;
20493 
input I0;
20494 
input I1;
20495 
input I2;
20496 
input I3;
20497 
input I4;
20498 
endmodule
20499 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20500 
module XOR2 (O, I0, I1);
20501 
output O;
20502 
input I0;
20503 
input I1;
20504 
endmodule
20505 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20506 
module XOR3 (O, I0, I1, I2);
20507 
output O;
20508 
input I0;
20509 
input I1;
20510 
input I2;
20511 
endmodule
20512 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20513 
module XOR4 (O, I0, I1, I2, I3);
20514 
output O;
20515 
input I0;
20516 
input I1;
20517 
input I2;
20518 
input I3;
20519 
endmodule
20520 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20521 
module XOR5 (O, I0, I1, I2, I3, I4);
20522 
output O;
20523 
input I0;
20524 
input I1;
20525 
input I2;
20526 
input I3;
20527 
input I4;
20528 
endmodule
20529 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20530 
module XORCY_D (LO, O, CI, LI);
20531 
output LO;
20532 
output O;
20533 
input CI;
20534 
input LI;
20535 
endmodule
20536 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20537 
module XORCY_L (LO, CI, LI);
20538 
output LO;
20539 
input CI;
20540 
input LI;
20541 
endmodule
20542 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
20543 
module XORCY (O, CI, LI);
20544 
output O;
20545 
input CI;
20546 
input LI;
20547 
endmodule

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