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jt_eaton |
--$ XILINX$RCSfile: xcf04s_vo20.bsd,v $
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-- XILINX Revision: 1.5
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-------------------------------------------------------------------------------
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-- Copyright (c) 2006 Xilinx, Inc.
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-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: v1.0 (PROM BSDL template version)
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-- \ \ Application: Generate_Prom_Bsdl_Files.pl, 1.00
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-- / / Filename: xcf04s_vo20.bsd
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-- /___/ /\ Generated: Wed Oct 11 19:34:18 2006
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-- \ \ / \ State: State: PRELIMINARY
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-- \___\/\___\
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--
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-- Device: XCF04S
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-- Package(s): VO20, VOG20
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-- Purpose: IEEE 1149.1 BSDL file
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-- Reference: None
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-- Revisions:
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--
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------------------------------------------------------------------------------
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-- Technical Support:
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--
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-- Find the latest version of this BSDL file, find technical support answers,
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-- or find contact information at: http://www.support.xilinx.com
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--
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------------------------------------------------------------------------------
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-- Special Instructions:
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--
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-- This BSDL file reflects the pre-configuration behavior. To reflect
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-- the post-configuration JTAG behavior (if any), edit this file as
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-- described below:
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-- 1. Rename file and entity if necessary to avoid name collisions.
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-- 2. Modify USERCODE value in USERCODE_REGISTER declaration.
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------------------------------------------------------------------------------
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-- BSDL Silicon Validation Information
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-- None.
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------------------------------------------------------------------------------
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entity XCF04S_VO20 is
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generic (PHYSICAL_PIN_MAP : string := "VO20");
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port (
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CE: in bit;
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CEO: out bit;
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CF: out bit;
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CLK: in bit;
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D0: out bit;
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OE_RESET: inout bit;
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TCK: in bit;
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TDI: in bit;
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TDO: out bit;
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TMS: in bit;
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GND: linkage bit;
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VCCINT: linkage bit;
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VCCJ: linkage bit;
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VCCO: linkage bit;
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DNC: linkage bit_vector(1 to 6)
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); --end port list
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use STD_1149_1_2001.all;
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attribute COMPONENT_CONFORMANCE of XCF04S_VO20 : entity is
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"STD_1149_1_2001";
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attribute PIN_MAP of XCF04S_VO20 : entity is
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PHYSICAL_PIN_MAP;
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constant VO20: PIN_MAP_STRING:=
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"CE: 10," &
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"CEO: 13," &
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"CF: 7," &
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"CLK: 3," &
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"D0: 1," &
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"OE_RESET: 8," &
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"TCK: 6," &
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"TDI: 4," &
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"TDO: 17," &
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"TMS: 5," &
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"GND: 11," &
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"VCCINT: 18," &
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"VCCJ: 20," &
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"VCCO: 19," &
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"DNC: (2, 9, 12, 14, 15, 16)";
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attribute TAP_SCAN_IN of TDI : signal is true;
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attribute TAP_SCAN_MODE of TMS : signal is true;
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attribute TAP_SCAN_OUT of TDO : signal is true;
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attribute TAP_SCAN_CLOCK of TCK : signal is (15.00e+06, BOTH);
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attribute INSTRUCTION_LENGTH of XCF04S_VO20 : entity is
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8;
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attribute INSTRUCTION_OPCODE of XCF04S_VO20 : entity is
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-- IEEE 1149.1 standard instructions
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"BYPASS (11111111)," &
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"SAMPLE (00000001)," &
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"PRELOAD (00000001)," &
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"EXTEST (00000000)," &
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"IDCODE (11111110)," &
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"USERCODE (11111101)," &
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"HIGHZ (11111100)," &
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"CLAMP (11111010)," &
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-- Xilinx special function instructions
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"CONFIG (11101110)," &
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-- Xilinx ISP instructions
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"ISPEN (11101000)," &
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"ISPENC (11101001)," &
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"NORMRST (11110000)," &
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"FPGM (11101010)," &
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"FERASE (11101100)," &
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"FADDR (11101011)," &
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"FDATA0 (11101101)," &
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"FVFY0 (11101111)," &
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"FDATA3 (11110011)," &
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"FVFY1 (11111000)," &
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"FVFY3 (11100010)," &
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"FVFY6 (11100110)," &
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"FBLANK0 (11100101)," &
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"FBLANK3 (11100001)," &
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"FBLANK6 (11100100)," &
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"SERASE (00001010)," &
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"ISC_READ_INFO (11110001)," &
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"ISCTESTSTATUS (11100011)," &
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"priv3 (11100111)," &
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"priv4 (11110110)," &
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"priv5 (11100000)," &
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"priv6 (11110111)," &
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"priv7 (11110010)," &
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"ISCCLRSTATUS (11110100)," &
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"priv9 (11110101)";
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attribute INSTRUCTION_CAPTURE of XCF04S_VO20: entity is
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"XXXXX001";
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-- IR[7:6]= Erase/Program Result (10=success; 01=fail; 00/11=N/A)
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-- IR[5] = Erase/Program Status (1=ready; 0=busy)
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-- IR[4] = ISP mode (1=in-system programming mode; 0=normal download mode)
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-- IR[3] = JTAG read-protection (1=secured; 0=unsecured)
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-- IR[2] = 0 value
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-- IR[1:0]= 01 as defined by IEEE STD 1149.1
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attribute INSTRUCTION_PRIVATE of XCF04S_VO20: entity is
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"priv3," &
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"priv4," &
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"priv5," &
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"priv6," &
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"priv7," &
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"priv9";
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attribute IDCODE_REGISTER of XCF04S_VO20: entity is
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"XXXX" & -- version
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"0101000001000110" & -- part number
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"00001001001" & -- manufacturer's id
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"1"; -- required by IEEE STD 1149.1
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attribute USERCODE_REGISTER of XCF04S_VO20: entity is
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"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
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attribute REGISTER_ACCESS of XCF04S_VO20 : entity is
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-- IEEE 1149.1 standard data registers
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"BOUNDARY (EXTEST, SAMPLE, PRELOAD),"&
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"DEVICE_ID (IDCODE, USERCODE),"&
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"BYPASS (BYPASS, HIGHZ, CLAMP, CONFIG)," &
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-- Xilinx ISP data registers
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"ISC_DEFAULT[1] (NORMRST, FPGM),"&
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"ISPENABLE[6] (ISPEN, ISPENC)," &
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"ADDRESS[16] (FADDR, FERASE, SERASE),"&
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"DATA0[4096] (FVFY0, FDATA0),"&
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"DATA1[4194304] (FVFY1, FBLANK0),"&
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"DATA3[3] (FVFY3, FDATA3, FBLANK3),"&
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"USERCODEV[32] (FVFY6, FBLANK6),"&
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"ISC_INFO[8] (ISC_READ_INFO),"&
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"XSC_STATUS[8] (ISCTESTSTATUS, ISCCLRSTATUS)";
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attribute BOUNDARY_LENGTH of XCF04S_VO20 : entity is
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25;
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attribute BOUNDARY_REGISTER of XCF04S_VO20 : entity is
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-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
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" 0 (BC_1, CLK, input, X )," &
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" 1 (BC_1, *, internal, 0 )," &
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" 2 (BC_1, *, internal, X )," &
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" 3 (BC_1, *, controlr, 0 )," &
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" 4 (BC_1, D0, output3, X, 3, 0, Z)," &
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" 5 (BC_1, *, internal, 0 )," &
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" 6 (BC_1, *, internal, X )," &
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" 7 (BC_1, *, internal, 0 )," &
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" 8 (BC_1, *, internal, X )," &
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" 9 (BC_1, *, internal, 0 )," &
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" 10 (BC_1, *, internal, X )," &
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" 11 (BC_1, *, controlr, 0 )," &
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" 12 (BC_1, CEO, output3, X, 11, 0, Z)," &
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" 13 (BC_1, *, internal, 0 )," &
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" 14 (BC_1, *, internal, X )," &
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" 15 (BC_1, CE, input, X )," &
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" 16 (BC_1, *, internal, 0 )," &
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" 17 (BC_1, *, internal, X )," &
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" 18 (BC_1, *, controlr, 0 )," &
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" 19 (BC_1, OE_RESET, output3, X, 18, 0, Z)," &
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" 20 (BC_1, OE_RESET, input, X )," &
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" 21 (BC_1, *, controlr, 0 )," &
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" 22 (BC_1, CF, output3, X, 21, 0, Z)," &
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" 23 (BC_1, *, internal, 0 )," &
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" 24 (BC_1, *, internal, X )";
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attribute DESIGN_WARNING of XCF04S_VO20 : entity is
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"The FERASE and FPGM instructions require " &
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"a falling-edge of TCK AFTER the Run-Test/Idle TAP state is entered " &
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"in order to start the operation corresponding to the instruction. " &
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"The FVFY0, FVFY1, and FBLANK0 instructions activate a non-standard, " &
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"output-only data register that does not pass TDI through to TDO. Thus, " &
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"data beyond the specififed length of the corresponding data register " &
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"is undefined. " &
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"When the FVFY0, FVFY1, and FBLANK0 instructions are in use, " &
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"all components between TDO of this device and the tester must select " &
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"the BYPASS register to avoid acting on the undefined data values. " &
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"Do not drive CF low when CF is connected to the PROGRAM/PROG_B pin of " &
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"a Virtex, Virtex-E, Virtex-4, Spartan-II, Spartan-IIE FPGA and when " &
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"the FPGA is in the same boundary-scan chain as this XCF04S. " &
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"A Low applied to the PROGRAM/PROG_B pin of these FPGAs resets the TAP " &
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"in these FPGAs.";
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end XCF04S_VO20;
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