| 1 |
131 |
jt_eaton |
eval 'exec `which perl` -S $0 ${1+"$@"}'
|
| 2 |
|
|
if 0;
|
| 3 |
|
|
|
| 4 |
|
|
#/**********************************************************************/
|
| 5 |
|
|
#/* */
|
| 6 |
|
|
#/* ------- */
|
| 7 |
|
|
#/* / SOC \ */
|
| 8 |
|
|
#/* / GEN \ */
|
| 9 |
|
|
#/* / TOOL \ */
|
| 10 |
|
|
#/* ============== */
|
| 11 |
|
|
#/* | | */
|
| 12 |
|
|
#/* |____________| */
|
| 13 |
|
|
#/* */
|
| 14 |
|
|
#/* */
|
| 15 |
|
|
#/* */
|
| 16 |
|
|
#/* Author(s): */
|
| 17 |
|
|
#/* - John Eaton, jt_eaton@opencores.org */
|
| 18 |
|
|
#/* */
|
| 19 |
|
|
#/**********************************************************************/
|
| 20 |
|
|
#/* */
|
| 21 |
|
|
#/* Copyright (C) <2010-2013> */
|
| 22 |
|
|
#/* */
|
| 23 |
|
|
#/* This source file may be used and distributed without */
|
| 24 |
|
|
#/* restriction provided that this copyright statement is not */
|
| 25 |
|
|
#/* removed from the file and that any derivative work contains */
|
| 26 |
|
|
#/* the original copyright notice and the associated disclaimer. */
|
| 27 |
|
|
#/* */
|
| 28 |
|
|
#/* This source file is free software; you can redistribute it */
|
| 29 |
|
|
#/* and/or modify it under the terms of the GNU Lesser General */
|
| 30 |
|
|
#/* Public License as published by the Free Software Foundation; */
|
| 31 |
|
|
#/* either version 2.1 of the License, or (at your option) any */
|
| 32 |
|
|
#/* later version. */
|
| 33 |
|
|
#/* */
|
| 34 |
|
|
#/* This source is distributed in the hope that it will be */
|
| 35 |
|
|
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
|
| 36 |
|
|
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
|
| 37 |
|
|
#/* PURPOSE. See the GNU Lesser General Public License for more */
|
| 38 |
|
|
#/* details. */
|
| 39 |
|
|
#/* */
|
| 40 |
|
|
#/* You should have received a copy of the GNU Lesser General */
|
| 41 |
|
|
#/* Public License along with this source; if not, download it */
|
| 42 |
|
|
#/* from http://www.opencores.org/lgpl.shtml */
|
| 43 |
|
|
#/* */
|
| 44 |
|
|
#/**********************************************************************/
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
|
|
############################################################################
|
| 48 |
|
|
# General PERL config
|
| 49 |
|
|
############################################################################
|
| 50 |
|
|
use Getopt::Long;
|
| 51 |
|
|
use English;
|
| 52 |
|
|
use File::Basename;
|
| 53 |
|
|
use Cwd;
|
| 54 |
|
|
use XML::LibXML;
|
| 55 |
|
|
use lib './tools';
|
| 56 |
|
|
use sys::lib;
|
| 57 |
|
|
use yp::lib;
|
| 58 |
133 |
jt_eaton |
use Parallel::ForkManager;
|
| 59 |
131 |
jt_eaton |
|
| 60 |
|
|
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
|
| 61 |
|
|
|
| 62 |
|
|
|
| 63 |
|
|
############################################################################
|
| 64 |
|
|
### Process the options
|
| 65 |
|
|
############################################################################
|
| 66 |
|
|
Getopt::Long::config("require_order", "prefix=-");
|
| 67 |
|
|
GetOptions("h","help",
|
| 68 |
|
|
) || die "(use '$program_name -h' for help)";
|
| 69 |
|
|
|
| 70 |
|
|
|
| 71 |
|
|
|
| 72 |
|
|
|
| 73 |
|
|
##############################################################################
|
| 74 |
|
|
## Help option
|
| 75 |
|
|
##############################################################################
|
| 76 |
|
|
if ( $opt_h or $opt_help )
|
| 77 |
133 |
jt_eaton |
{ print "\n build_elab_master";
|
| 78 |
131 |
jt_eaton |
print "\n";
|
| 79 |
|
|
exit 1;
|
| 80 |
|
|
}
|
| 81 |
|
|
|
| 82 |
|
|
|
| 83 |
|
|
my $parser = XML::LibXML->new();
|
| 84 |
|
|
|
| 85 |
|
|
|
| 86 |
|
|
|
| 87 |
|
|
|
| 88 |
|
|
#/**********************************************************************/
|
| 89 |
|
|
#/* Process each library by finding any ip-xact file in any component */
|
| 90 |
|
|
#/* */
|
| 91 |
|
|
#/* Each ip-xact file is parsed and it's filename and the names of any*/
|
| 92 |
|
|
#/* modules that it uses are saved. */
|
| 93 |
|
|
#/* */
|
| 94 |
|
|
#/* */
|
| 95 |
|
|
#/**********************************************************************/
|
| 96 |
|
|
|
| 97 |
133 |
jt_eaton |
my @elab_cmds = ();
|
| 98 |
|
|
my @des_cmds = ();
|
| 99 |
|
|
my @gen_cmds = ();
|
| 100 |
|
|
|
| 101 |
|
|
my $number_of_cpus = yp::lib::get_number_of_cpus();
|
| 102 |
|
|
|
| 103 |
131 |
jt_eaton |
my $home = cwd();
|
| 104 |
|
|
|
| 105 |
|
|
my $prefix = yp::lib::get_workspace();
|
| 106 |
|
|
$prefix = "/${prefix}";
|
| 107 |
|
|
|
| 108 |
|
|
my @vendors = yp::lib::find_vendors();
|
| 109 |
|
|
|
| 110 |
|
|
foreach my $vendor (@vendors)
|
| 111 |
|
|
{
|
| 112 |
|
|
|
| 113 |
|
|
my $vendor_status = yp::lib::get_vendor_status($vendor);
|
| 114 |
|
|
if($vendor_status eq "active")
|
| 115 |
|
|
{
|
| 116 |
|
|
my @libraries = yp::lib::find_libraries($vendor);
|
| 117 |
|
|
foreach my $library (@libraries)
|
| 118 |
|
|
{
|
| 119 |
|
|
|
| 120 |
|
|
my $library_status = yp::lib::get_library_status($vendor,$library);
|
| 121 |
|
|
if($library_status eq "active")
|
| 122 |
|
|
{
|
| 123 |
133 |
jt_eaton |
# print "$vendor $library \n ";
|
| 124 |
131 |
jt_eaton |
run_vendor_library ( $vendor , $library)
|
| 125 |
|
|
}
|
| 126 |
|
|
}
|
| 127 |
|
|
}
|
| 128 |
|
|
}
|
| 129 |
|
|
|
| 130 |
|
|
|
| 131 |
|
|
|
| 132 |
|
|
|
| 133 |
|
|
sub run_vendor_library
|
| 134 |
|
|
{
|
| 135 |
|
|
my @params = @_;
|
| 136 |
|
|
my $library = pop(@params);
|
| 137 |
|
|
my $vendor = pop(@params);
|
| 138 |
|
|
|
| 139 |
|
|
|
| 140 |
|
|
my @components = yp::lib::find_components($vendor,$library);
|
| 141 |
|
|
|
| 142 |
|
|
foreach my $component (@components)
|
| 143 |
|
|
{
|
| 144 |
|
|
my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
|
| 145 |
|
|
if($socgen_filename)
|
| 146 |
|
|
{
|
| 147 |
|
|
my $socgen_file = $parser->parse_file($socgen_filename);
|
| 148 |
|
|
|
| 149 |
133 |
jt_eaton |
#print "ELAB_XXXXX build_master $vendor $library \n";
|
| 150 |
|
|
|
| 151 |
131 |
jt_eaton |
#/*********************************************************************************************/
|
| 152 |
133 |
jt_eaton |
#/ elaborate each testbench */
|
| 153 |
131 |
jt_eaton |
#/ */
|
| 154 |
|
|
#/*********************************************************************************************/
|
| 155 |
|
|
|
| 156 |
133 |
jt_eaton |
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
| 157 |
|
|
{
|
| 158 |
|
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
| 159 |
|
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
| 160 |
|
|
my $testbench_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
|
| 161 |
|
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
| 162 |
|
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
| 163 |
|
|
|
| 164 |
|
|
|
| 165 |
|
|
if(defined $testbench_configuration )
|
| 166 |
|
|
{
|
| 167 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration configuration -env sim -tool testbenches -unit testbench \n";
|
| 168 |
|
|
}
|
| 169 |
|
|
else
|
| 170 |
|
|
{
|
| 171 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool testbenches -unit testbench \n";
|
| 172 |
|
|
}
|
| 173 |
|
|
|
| 174 |
|
|
push @elab_cmds, $cmd;
|
| 175 |
|
|
|
| 176 |
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
| 177 |
|
|
push @gen_cmds, $cmd;
|
| 178 |
|
|
|
| 179 |
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
| 180 |
|
|
push @des_cmds, $cmd;
|
| 181 |
|
|
|
| 182 |
|
|
if ($testbench_instance)
|
| 183 |
|
|
{
|
| 184 |
|
|
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";
|
| 185 |
|
|
|
| 186 |
|
|
push @gen_cmds, $cmd;
|
| 187 |
|
|
}
|
| 188 |
|
|
}
|
| 189 |
|
|
|
| 190 |
|
|
|
| 191 |
|
|
|
| 192 |
|
|
|
| 193 |
|
|
|
| 194 |
|
|
|
| 195 |
|
|
#/*********************************************************************************************/
|
| 196 |
|
|
#/ elaborate for each test */
|
| 197 |
|
|
#/ */
|
| 198 |
|
|
#/*********************************************************************************************/
|
| 199 |
|
|
|
| 200 |
131 |
jt_eaton |
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
|
| 201 |
|
|
{
|
| 202 |
|
|
my $test_name = $i_name ->findnodes('./text()')->to_literal ;
|
| 203 |
|
|
my $test_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
| 204 |
|
|
|
| 205 |
|
|
# print "XXXX $vendor $library $component $test_variant $test_name \n ";
|
| 206 |
|
|
|
| 207 |
|
|
|
| 208 |
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
| 209 |
|
|
{
|
| 210 |
|
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
| 211 |
133 |
jt_eaton |
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
| 212 |
|
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
| 213 |
|
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
| 214 |
131 |
jt_eaton |
|
| 215 |
|
|
|
| 216 |
|
|
if($test_variant eq $testbench_variant )
|
| 217 |
|
|
{
|
| 218 |
|
|
# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
|
| 219 |
|
|
|
| 220 |
133 |
jt_eaton |
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
| 221 |
131 |
jt_eaton |
|
| 222 |
133 |
jt_eaton |
|
| 223 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
|
| 224 |
|
|
# print "$cmd";
|
| 225 |
|
|
# if (system($cmd)) {}
|
| 226 |
|
|
push @elab_cmds, $cmd;
|
| 227 |
|
|
|
| 228 |
|
|
|
| 229 |
|
|
|
| 230 |
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
| 231 |
|
|
# print "$cmd";
|
| 232 |
|
|
# if (system($cmd)) {}
|
| 233 |
|
|
push @gen_cmds, $cmd;
|
| 234 |
|
|
|
| 235 |
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
| 236 |
|
|
# print "$cmd";
|
| 237 |
|
|
# if (system($cmd)) {}
|
| 238 |
|
|
push @des_cmds, $cmd;
|
| 239 |
|
|
|
| 240 |
|
|
|
| 241 |
|
|
|
| 242 |
|
|
|
| 243 |
131 |
jt_eaton |
if ($testbench_instance)
|
| 244 |
|
|
{
|
| 245 |
|
|
|
| 246 |
133 |
jt_eaton |
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
|
| 247 |
131 |
jt_eaton |
|
| 248 |
133 |
jt_eaton |
push @gen_cmds, $cmd;
|
| 249 |
131 |
jt_eaton |
}
|
| 250 |
133 |
jt_eaton |
}
|
| 251 |
131 |
jt_eaton |
|
| 252 |
133 |
jt_eaton |
}
|
| 253 |
|
|
}
|
| 254 |
131 |
jt_eaton |
|
| 255 |
133 |
jt_eaton |
|
| 256 |
|
|
|
| 257 |
|
|
|
| 258 |
|
|
#/*********************************************************************************************/
|
| 259 |
|
|
#/ elaborate each fpga */
|
| 260 |
|
|
#/ */
|
| 261 |
|
|
#/*********************************************************************************************/
|
| 262 |
|
|
|
| 263 |
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
|
| 264 |
|
|
{
|
| 265 |
|
|
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
|
| 266 |
|
|
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
| 267 |
|
|
my $fpga_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
|
| 268 |
|
|
|
| 269 |
|
|
if(defined $fpga_configuration )
|
| 270 |
|
|
{
|
| 271 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -configuration $fpga_configuration -env syn -tool fpgas -unit fpga \n";
|
| 272 |
|
|
}
|
| 273 |
|
|
else
|
| 274 |
|
|
{
|
| 275 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool fpgas -unit fpga \n";
|
| 276 |
|
|
}
|
| 277 |
|
|
|
| 278 |
|
|
# push @elab_cmds, $cmd;
|
| 279 |
|
|
|
| 280 |
|
|
|
| 281 |
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
|
| 282 |
|
|
# push @gen_cmds, $cmd;
|
| 283 |
|
|
|
| 284 |
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
|
| 285 |
|
|
# push @des_cmds, $cmd;
|
| 286 |
131 |
jt_eaton |
}
|
| 287 |
|
|
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
133 |
jt_eaton |
#/*********************************************************************************************/
|
| 292 |
|
|
#/ elaborate for each chip */
|
| 293 |
|
|
#/ */
|
| 294 |
|
|
#/*********************************************************************************************/
|
| 295 |
131 |
jt_eaton |
|
| 296 |
133 |
jt_eaton |
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))
|
| 297 |
|
|
{
|
| 298 |
|
|
my $chip_name = $i_name ->findnodes('./text()')->to_literal ;
|
| 299 |
|
|
my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
| 300 |
131 |
jt_eaton |
|
| 301 |
133 |
jt_eaton |
# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";
|
| 302 |
131 |
jt_eaton |
|
| 303 |
|
|
|
| 304 |
133 |
jt_eaton |
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
|
| 305 |
|
|
{
|
| 306 |
|
|
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
|
| 307 |
|
|
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
if($chip_variant eq $fpga_variant )
|
| 311 |
|
|
{
|
| 312 |
|
|
# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";
|
| 313 |
|
|
|
| 314 |
|
|
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";
|
| 318 |
|
|
# print "$cmd";
|
| 319 |
|
|
|
| 320 |
|
|
push @elab_cmds, $cmd;
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
|
| 325 |
|
|
# print "$cmd";
|
| 326 |
|
|
|
| 327 |
|
|
push @gen_cmds, $cmd;
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| 328 |
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| 329 |
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$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
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| 330 |
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# print "$cmd";
|
| 331 |
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| 332 |
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push @des_cmds, $cmd;
|
| 333 |
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| 334 |
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| 335 |
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| 336 |
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| 337 |
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| 338 |
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}
|
| 339 |
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|
| 340 |
131 |
jt_eaton |
}
|
| 341 |
133 |
jt_eaton |
}
|
| 342 |
131 |
jt_eaton |
|
| 343 |
133 |
jt_eaton |
|
| 344 |
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| 345 |
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| 346 |
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|
| 347 |
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| 348 |
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| 349 |
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| 350 |
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|
| 351 |
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| 352 |
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| 353 |
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| 354 |
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| 355 |
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| 356 |
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|
| 357 |
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|
| 358 |
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|
| 359 |
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|
| 360 |
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|
| 361 |
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| 362 |
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| 363 |
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|
| 364 |
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| 365 |
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|
| 366 |
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|
| 367 |
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|
| 368 |
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|
| 369 |
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|
| 370 |
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|
| 371 |
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|
|
| 372 |
|
|
|
| 373 |
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|
|
| 374 |
131 |
jt_eaton |
}
|
| 375 |
|
|
|
| 376 |
133 |
jt_eaton |
|
| 377 |
131 |
jt_eaton |
}
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
133 |
jt_eaton |
@elab_cmds = sys::lib::trim_sort(@elab_cmds);
|
| 382 |
|
|
@des_cmds = sys::lib::trim_sort(@des_cmds);
|
| 383 |
|
|
@gen_cmds = sys::lib::trim_sort(@gen_cmds);
|
| 384 |
131 |
jt_eaton |
|
| 385 |
133 |
jt_eaton |
|
| 386 |
|
|
|
| 387 |
|
|
#my $manager = new Parallel::ForkManager( $number_of_cpus );
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
foreach $cmd (@elab_cmds)
|
| 392 |
|
|
{
|
| 393 |
|
|
# $manager->start and next;
|
| 394 |
|
|
if (system($cmd)) {}
|
| 395 |
|
|
# $manager->finish;
|
| 396 |
|
|
}
|
| 397 |
|
|
|
| 398 |
|
|
#$manager->wait_all_children;
|
| 399 |
|
|
|
| 400 |
|
|
|
| 401 |
|
|
foreach $cmd (@des_cmds)
|
| 402 |
|
|
{
|
| 403 |
|
|
if (system($cmd)) {}
|
| 404 |
|
|
}
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
foreach $cmd (@gen_cmds)
|
| 408 |
|
|
{
|
| 409 |
|
|
# $manager->start and next;
|
| 410 |
|
|
if (system($cmd)) {}
|
| 411 |
|
|
# $manager->finish;
|
| 412 |
|
|
}
|
| 413 |
|
|
|
| 414 |
|
|
#$manager->wait_all_children;
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
return(0);
|
| 422 |
|
|
|
| 423 |
|
|
}
|
| 424 |
|
|
|
