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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;
 
#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010-2013>                */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
use Cwd;
use XML::LibXML;
use lib './tools';
use sys::lib;
use yp::lib;
use BerkeleyDB;
use Parallel::ForkManager;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h","help",
) || die "(use '$program_name -h' for help)";
 
 
 
 
##############################################################################
## Help option
##############################################################################
if ( $opt_h or $opt_help  )
  { print "\n build_elab_master";
    print "\n";
    exit 1;
  }
 
 
my $parser = XML::LibXML->new();
 
 
 
 
#/**********************************************************************/
#/*  Process each library by finding any ip-xact file in any component */
#/*                                                                    */
#/*  Each ip-xact file is parsed and it's filename and the names of any*/
#/*  modules that it uses are saved.                                   */
#/*                                                                    */
#/*                                                                    */
#/**********************************************************************/
 
my @elab_cmds = ();
my @des_cmds = ();
my @gen_cmds = ();
my @top_levels =();
my @children =();
 
 
print "Build_elab_master \n";
 
my $number_of_cpus   = yp::lib::get_number_of_cpus();
 
my $home = cwd();
 
my $prefix   = yp::lib::get_workspace();
   $prefix   = "/${prefix}";
 
my @vendors = yp::lib::find_vendors();
 
foreach my $vendor (@vendors)
 {
 
 my $vendor_status    =  yp::lib::get_vendor_status($vendor);
 if($vendor_status eq "active")
   {
   my @libraries = yp::lib::find_libraries($vendor);
   foreach my $library (@libraries)
     {
 
     my $library_status   =  yp::lib::get_library_status($vendor,$library);
     if($library_status eq "active")
         {
 
 
 
 
 
 
my @components   = yp::lib::find_components($vendor,$library);
 
foreach my $component (@components)
   {
   my $socgen_filename     = yp::lib::find_componentConfiguration($vendor,$library,$component);
   if($socgen_filename)
   {
   my $socgen_file     = $parser->parse_file($socgen_filename);
 
 
 
   #/*********************************************************************************************/
   #/   elaborate  each testbench                                                                */
   #/                                                                                            */
   #/*********************************************************************************************/
 
   foreach  my   $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
      {
 
      my $testbench_variant            = $j_name ->findnodes('./text()')->to_literal ;
      my $testbench_version            = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
      my $testbench_config             = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
      my $testbench_instance           = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
      my $testbench_bus_name           = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
 
 
if(defined $testbench_config   && length $testbench_config > 0)
{
$cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version} -configuration ${testbench_config}  \n";
}
else
{
$cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version}   \n";
}
 
 
       push @elab_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_root   -vendor ${vendor}  -library ${library}  -component ${component} -version ${testbench_version}  \n  ";
       push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design   -vendor ${vendor}  -library ${library}  -component ${component} -version ${testbench_version} \n    ";
       push @des_cmds, $cmd;
 
    if  ($testbench_instance)
         {
$cmd ="./tools/verilog/trace_bus -prefix  ${prefix}  -vendor ${vendor}  -library ${library}  -component ${component} -version ${testbench_version}  -path $testbench_instance  -bus_name $testbench_bus_name  ";
 
       push @gen_cmds, $cmd;
         }
      }
 
 
 
 
 
 
   #/*********************************************************************************************/
   #/   elaborate for each test                                                                  */
   #/                                                                                            */
   #/*********************************************************************************************/
 
   foreach  my   $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
      {
      my $test_name            = $i_name ->findnodes('./text()')->to_literal ;
      my $test_variant          = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
 
#      print "XXXX $vendor $library $component  $test_variant   $test_name  \n ";
 
 
   foreach  my   $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
      {
      my $testbench_variant            = $j_name ->findnodes('./text()')->to_literal ;
      my $testbench_version            = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
      my $testbench_instance           = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
      my $testbench_bus_name           = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
 
 
      if($test_variant eq $testbench_variant )
       {
#       print "YYYY $prefix  $vendor $library $component   $testbench_version  $test_name   \n ";
 
#print "ELAB_XXXXX  test_variant  $vendor $library \n";
 
push @top_levels,  "${vendor}::${library}::${component}::${testbench_version}::${test_name}";
 
$cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version}  -env sim -tool icarus -unit test -name  $test_name  \n";
 
       push @elab_cmds, $cmd;
 
 
 
$cmd ="./tools/verilog/gen_root   -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version}  -name  $test_name  \n";
 
       push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design   -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version}  -name  $test_name  \n";
 
       push @des_cmds, $cmd;
 
 
 
 
    if  ($testbench_instance)
         {
 
$cmd ="./tools/verilog/trace_bus -prefix  ${prefix}  -vendor ${vendor}  -library ${library}  -component ${component} -version ${testbench_version}  -path $testbench_instance  -bus_name $testbench_bus_name  -test_name  $test_name ";
 
       push @gen_cmds, $cmd;
         }
       }
 
      }
      }
 
 
 
 
 
 
 
 
   #/*********************************************************************************************/
   #/   elaborate for each chip                                                                  */
   #/                                                                                            */
   #/*********************************************************************************************/
 
   foreach  my   $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))
      {
      my $chip_name            = $i_name ->findnodes('./text()')->to_literal ;
      my $chip_variant          = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
 
#      print "XXXX $vendor $library $component  $chip_variant   $chip_name  \n ";
 
 
   foreach  my   $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
      {
      my $fpga_variant            = $j_name ->findnodes('./text()')->to_literal ;
      my $fpga_version                 = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
 
 
      if($chip_variant eq $fpga_variant )
       {
#       print "YYYY $prefix  $vendor $library $component   $fpga_version  $chip_name   \n ";
 
#print "ELAB_XXXXX  test_variant  $vendor $library \n";
 
push @top_levels,  "${vendor}::${library}::${component}::${fpga_version}::${chip_name}";
$cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${fpga_version}  -env syn -tool ise -unit chip -name $chip_name  \n";
 
        push @elab_cmds, $cmd;
 
 
 
$cmd ="./tools/verilog/gen_root   -vendor ${vendor} -library ${library} -component   ${component}  -version ${fpga_version}  -name  $chip_name  \n";
 
       push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design   -vendor ${vendor} -library ${library} -component   ${component}  -version ${fpga_version}  -name  $chip_name  \n";
 
       push @des_cmds, $cmd;
       }
 
      }
      }
 
 
 
 
 
 
 
 
   #/*********************************************************************************************/
   #/   elaborate for each rtlcheck                                                              */
   #/                                                                                            */
   #/*********************************************************************************************/
 
   foreach  my   $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:rtl_check/socgen:lint/socgen:name"))
      {
      my $lint_name            = $i_name ->findnodes('./text()')->to_literal ;
      my $lint_variant          = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
 
   foreach  my   $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
      {
      my $testbench_variant            = $j_name ->findnodes('./text()')->to_literal ;
      my $testbench_version                 = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
 
      if($lint_variant eq $testbench_variant )
       {
       $cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${testbench_version}  -env sim -tool rtl_check -unit lint -name $lint_name  \n";
        push @elab_cmds, $cmd;
       }
 
      }
      }
 
 
  #/**********************************************************************************************/
   #/   elaborate for each top module                                                            */
   #/                                                                                            */
   #/*********************************************************************************************/
 
   foreach  my   $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
      {
      my $version_name          = $i_name ->findnodes('./text()')->to_literal ;
      my $configuration         = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
$cmd ="./tools/verilog/elab_verilog  -vendor ${vendor} -library ${library} -component   ${component}  -version ${version_name} -configuration ${configuration}\n";
        push @elab_cmds, $cmd;
      }
 
 
}
 
 
 
}
 
 
 
 
         }
     }
   }
 }
 
 
 
 
 
@elab_cmds      = sys::lib::trim_sort(@elab_cmds);
 
print "Start elab_cmds \n";
 
foreach $cmd (@elab_cmds)
 {
 
# $manager->start and next;
#print "$cmd";
  if (system($cmd)) {}
# $manager->finish;
 }
 
 
print "End elab_cmds \n";
 
 
 
 
 
 
 
 
 
 
 
 
@top_levels     = sys::lib::trim_sort(@top_levels);
 
 
foreach $level (@top_levels)
 {
 
 ( $ven,$lib,$cmp,$ver,$nam) = split( /\::/ , $level);
 
 my $elab_db_filename = yp::lib::get_elab_db_filename($ven,$lib,$cmp,$ver,"default");
 
 my $elab_db  = new BerkeleyDB::Hash( -Filename => "$elab_db_filename", -Flags => DB_CREATE ) or die "Cannot open $elab_db_filename: $!";
 
 my $key;
 my $value;
 
 $cursor = $elab_db ->db_cursor() ;
 while ($cursor->c_get($key, $value, DB_NEXT) == 0)
   {
 
#   print "$key \n";
my $VLNV;
my $vlnv;
 
 
   ( ${VLNV},${vlnv}) = split( /___root./ , $key);
   if($VLNV eq "component")
     {
     if($vlnv)
       {
       push @children,$value;
 
       }
     }
}
}
 
@children     = sys::lib::trim_sort(@children);
 
foreach my $child (@children)
 {
 my $ven;
 my $lib;
 my $cmp;
 my $ver;
 ( ${ven},${lib},${cmp},${ver}) = split( /:/ , $child);
 
 
 
 my $child_filename     = yp::lib::find_componentConfiguration($ven,$lib,$cmp);
 if($child_filename)
    {
    my $socgen_file     = $parser->parse_file($child_filename);
    foreach  my   $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
      {
      my $version_name          = $i_name ->findnodes('./text()')->to_literal ;
      my $configuration         = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
      $cmd ="./tools/verilog/elab_verilog  -vendor ${ven} -library ${lib} -component   ${cmp}  -version ${version_name} -configuration ${configuration}\n";
 
      if (system($cmd)) {}
      }
    }
 }
 
 
 
 
 
 
 
 
@des_cmds       = sys::lib::trim_sort(@des_cmds);
@gen_cmds       = sys::lib::trim_sort(@gen_cmds);
 
 
#print "Execute cmds \n";
 
my $manager = new Parallel::ForkManager( $number_of_cpus );
 
 
 
 
#$manager->wait_all_children;
 
 
 
 
 
 
 
foreach $cmd (@des_cmds)
 {
      if (system($cmd)) {}
 }
 
print "End des_cmds \n";
 
foreach $cmd (@gen_cmds)
 {
# $manager->start and next;
  if (system($cmd)) {}
# $manager->finish;
 }
 
#$manager->wait_all_children;
 
print "End All \n";
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	eval 'exec `which perl` -S $0 ${1+"$@"}'
2			`if 0;`
3
4			`#/**********************************************************************/`
5			`#/* */`
6			`#/* ------- */`
7			`#/* / SOC \ */`
8			`#/* / GEN \ */`
9			`#/* / TOOL \ */`
10			`#/* ============== */`
11			`#/* \| \| */`
12			`#/* \|____________\| */`
13			`#/* */`
14			`#/* */`
15			`#/* */`
16			`#/* Author(s): */`
17			`#/* - John Eaton, jt_eaton@opencores.org */`
18			`#/* */`
19			`#/**********************************************************************/`
20			`#/* */`
21			`#/* Copyright (C) <2010-2013> */`
22			`#/* */`
23			`#/* This source file may be used and distributed without */`
24			`#/* restriction provided that this copyright statement is not */`
25			`#/* removed from the file and that any derivative work contains */`
26			`#/* the original copyright notice and the associated disclaimer. */`
27			`#/* */`
28			`#/* This source file is free software; you can redistribute it */`
29			`#/* and/or modify it under the terms of the GNU Lesser General */`
30			`#/* Public License as published by the Free Software Foundation; */`
31			`#/* either version 2.1 of the License, or (at your option) any */`
32			`#/* later version. */`
33			`#/* */`
34			`#/* This source is distributed in the hope that it will be */`
35			`#/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
36			`#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
37			`#/* PURPOSE. See the GNU Lesser General Public License for more */`
38			`#/* details. */`
39			`#/* */`
40			`#/* You should have received a copy of the GNU Lesser General */`
41			`#/* Public License along with this source; if not, download it */`
42			`#/* from http://www.opencores.org/lgpl.shtml */`
43			`#/* */`
44			`#/**********************************************************************/`
45
46
47			`############################################################################`
48			`# General PERL config`
49			`############################################################################`
50			`use Getopt::Long;`
51			`use English;`
52			`use File::Basename;`
53			`use Cwd;`
54			`use XML::LibXML;`
55			`use lib './tools';`
56			`use sys::lib;`
57			`use yp::lib;`
58	134	jt_eaton	`use BerkeleyDB;`
59	133	jt_eaton	`use Parallel::ForkManager;`
60	131	jt_eaton
61			`$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.`
62
63
64			`############################################################################`
65			`### Process the options`
66			`############################################################################`
67			`Getopt::Long::config("require_order", "prefix=-");`
68			`GetOptions("h","help",`
69			`) \|\| die "(use '$program_name -h' for help)";`
70
71
72
73
74			`##############################################################################`
75			`## Help option`
76			`##############################################################################`
77			`if ( $opt_h or $opt_help )`
78	133	jt_eaton	`{ print "\n build_elab_master";`
79	131	jt_eaton	`print "\n";`
80			`exit 1;`
81			`}`
82
83
84			`my $parser = XML::LibXML->new();`
85
86
87
88
89			`#/**********************************************************************/`
90			`#/* Process each library by finding any ip-xact file in any component */`
91			`#/* */`
92			`#/* Each ip-xact file is parsed and it's filename and the names of any*/`
93			`#/* modules that it uses are saved. */`
94			`#/* */`
95			`#/* */`
96			`#/**********************************************************************/`
97
98	133	jt_eaton	`my @elab_cmds = ();`
99			`my @des_cmds = ();`
100			`my @gen_cmds = ();`
101	134	jt_eaton	`my @top_levels =();`
102			`my @children =();`
103	133	jt_eaton
104	134	jt_eaton
105			`print "Build_elab_master \n";`
106
107	133	jt_eaton	`my $number_of_cpus = yp::lib::get_number_of_cpus();`
108
109	131	jt_eaton	`my $home = cwd();`
110
111			`my $prefix = yp::lib::get_workspace();`
112			`$prefix = "/${prefix}";`
113
114			`my @vendors = yp::lib::find_vendors();`
115
116			`foreach my $vendor (@vendors)`
117			`{`
118
119			`my $vendor_status = yp::lib::get_vendor_status($vendor);`
120			`if($vendor_status eq "active")`
121			`{`
122			`my @libraries = yp::lib::find_libraries($vendor);`
123			`foreach my $library (@libraries)`
124			`{`
125
126			`my $library_status = yp::lib::get_library_status($vendor,$library);`
127			`if($library_status eq "active")`
128			`{`
129
130
131
132
133
134	134	jt_eaton
135	131	jt_eaton	`my @components = yp::lib::find_components($vendor,$library);`
136
137			`foreach my $component (@components)`
138			`{`
139			`my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);`
140			`if($socgen_filename)`
141			`{`
142			`my $socgen_file = $parser->parse_file($socgen_filename);`
143
144	133	jt_eaton
145	134	jt_eaton
146	131	jt_eaton	`#/*********************************************************************************************/`
147	133	jt_eaton	`#/ elaborate each testbench */`
148	131	jt_eaton	`#/ */`
149			`#/*********************************************************************************************/`
150
151	133	jt_eaton	`foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))`
152			`{`
153	134	jt_eaton
154	133	jt_eaton	`my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;`
155			`my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;`
156	134	jt_eaton	`my $testbench_config = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;`
157	133	jt_eaton	`my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;`
158			`my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;`
159
160
161	134	jt_eaton	`if(defined $testbench_config && length $testbench_config > 0)`
162	133	jt_eaton	`{`
163	134	jt_eaton	`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration ${testbench_config} \n";`
164	133	jt_eaton	`}`
165			`else`
166			`{`
167	134	jt_eaton	`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n";`
168	133	jt_eaton	`}`
169
170	134	jt_eaton
171	133	jt_eaton	`push @elab_cmds, $cmd;`
172
173			`$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";`
174			`push @gen_cmds, $cmd;`
175
176			`$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";`
177			`push @des_cmds, $cmd;`
178
179			`if ($testbench_instance)`
180			`{`
181			`$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";`
182
183			`push @gen_cmds, $cmd;`
184			`}`
185			`}`
186
187
188
189
190
191
192			`#/*********************************************************************************************/`
193			`#/ elaborate for each test */`
194			`#/ */`
195			`#/*********************************************************************************************/`
196
197	131	jt_eaton	`foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))`
198			`{`
199			`my $test_name = $i_name ->findnodes('./text()')->to_literal ;`
200			`my $test_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;`
201
202			`# print "XXXX $vendor $library $component $test_variant $test_name \n ";`
203
204
205			`foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))`
206			`{`
207			`my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;`
208	133	jt_eaton	`my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;`
209			`my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;`
210			`my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;`
211	131	jt_eaton
212
213			`if($test_variant eq $testbench_variant )`
214			`{`
215			`# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";`
216
217	133	jt_eaton	`#print "ELAB_XXXXX test_variant $vendor $library \n";`
218	131	jt_eaton
219	134	jt_eaton	`push @top_levels, "${vendor}::${library}::${component}::${testbench_version}::${test_name}";`
220	133	jt_eaton
221	134	jt_eaton	`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";`
222
223	133	jt_eaton	`push @elab_cmds, $cmd;`
224
225
226
227			`$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";`
228	134	jt_eaton
229	133	jt_eaton	`push @gen_cmds, $cmd;`
230
231			`$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";`
232	134	jt_eaton
233	133	jt_eaton	`push @des_cmds, $cmd;`
234
235
236
237
238	131	jt_eaton	`if ($testbench_instance)`
239			`{`
240
241	133	jt_eaton	`$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";`
242	131	jt_eaton
243	133	jt_eaton	`push @gen_cmds, $cmd;`
244	131	jt_eaton	`}`
245	133	jt_eaton	`}`
246	131	jt_eaton
247	133	jt_eaton	`}`
248			`}`
249	131	jt_eaton
250	133	jt_eaton
251
252
253
254
255
256
257			`#/*********************************************************************************************/`
258			`#/ elaborate for each chip */`
259			`#/ */`
260			`#/*********************************************************************************************/`
261	131	jt_eaton
262	133	jt_eaton	`foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))`
263			`{`
264			`my $chip_name = $i_name ->findnodes('./text()')->to_literal ;`
265			`my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;`
266	131	jt_eaton
267	133	jt_eaton	`# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";`
268	131	jt_eaton
269
270	133	jt_eaton	`foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))`
271			`{`
272			`my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;`
273			`my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;`
274
275
276			`if($chip_variant eq $fpga_variant )`
277			`{`
278			`# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";`
279
280			`#print "ELAB_XXXXX test_variant $vendor $library \n";`
281
282	134	jt_eaton	`push @top_levels, "${vendor}::${library}::${component}::${fpga_version}::${chip_name}";`
283	133	jt_eaton	`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";`
284
285			`push @elab_cmds, $cmd;`
286
287
288
289			`$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";`
290
291			`push @gen_cmds, $cmd;`
292
293			`$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";`
294
295			`push @des_cmds, $cmd;`
296	134	jt_eaton	`}`
297	133	jt_eaton
298	134	jt_eaton	`}`
299			`}`
300	133	jt_eaton
301
302
303
304	134	jt_eaton
305
306
307
308			`#/*********************************************************************************************/`
309			`#/ elaborate for each rtlcheck */`
310			`#/ */`
311			`#/*********************************************************************************************/`
312
313			`foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:rtl_check/socgen:lint/socgen:name"))`
314			`{`
315			`my $lint_name = $i_name ->findnodes('./text()')->to_literal ;`
316			`my $lint_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;`
317
318			`foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))`
319			`{`
320			`my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;`
321			`my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;`
322
323			`if($lint_variant eq $testbench_variant )`
324			`{`
325			`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool rtl_check -unit lint -name $lint_name \n";`
326			`push @elab_cmds, $cmd;`
327	133	jt_eaton	`}`
328
329	131	jt_eaton	`}`
330	133	jt_eaton	`}`
331	131	jt_eaton
332	133	jt_eaton
333	134	jt_eaton	`#/**********************************************************************************************/`
334			`#/ elaborate for each top module */`
335			`#/ */`
336			`#/*********************************************************************************************/`
337	133	jt_eaton
338	134	jt_eaton	`foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))`
339			`{`
340			`my $version_name = $i_name ->findnodes('./text()')->to_literal ;`
341			`my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;`
342			`$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${version_name} -configuration ${configuration}\n";`
343			`push @elab_cmds, $cmd;`
344			`}`
345	133	jt_eaton
346
347	134	jt_eaton	`}`
348	133	jt_eaton
349
350
351	134	jt_eaton	`}`
352	133	jt_eaton
353
354
355
356	134	jt_eaton	`}`
357			`}`
358			`}`
359			`}`
360	133	jt_eaton
361
362
363
364
365	134	jt_eaton	`@elab_cmds = sys::lib::trim_sort(@elab_cmds);`
366	133	jt_eaton
367	134	jt_eaton	`print "Start elab_cmds \n";`
368	133	jt_eaton
369	134	jt_eaton	`foreach $cmd (@elab_cmds)`
370			`{`
371	133	jt_eaton
372	134	jt_eaton	`# $manager->start and next;`
373			`#print "$cmd";`
374			`if (system($cmd)) {}`
375			`# $manager->finish;`
376			`}`
377	133	jt_eaton
378
379	134	jt_eaton	`print "End elab_cmds \n";`
380	133	jt_eaton
381
382
383
384
385
386
387
388
389
390	131	jt_eaton
391	133	jt_eaton
392	134	jt_eaton	`@top_levels = sys::lib::trim_sort(@top_levels);`
393
394
395			`foreach $level (@top_levels)`
396			`{`
397
398			`( $ven,$lib,$cmp,$ver,$nam) = split( /\::/ , $level);`
399
400			`my $elab_db_filename = yp::lib::get_elab_db_filename($ven,$lib,$cmp,$ver,"default");`
401
402			`my $elab_db = new BerkeleyDB::Hash( -Filename => "$elab_db_filename", -Flags => DB_CREATE ) or die "Cannot open $elab_db_filename: $!";`
403
404			`my $key;`
405			`my $value;`
406
407			`$cursor = $elab_db ->db_cursor() ;`
408			`while ($cursor->c_get($key, $value, DB_NEXT) == 0)`
409			`{`
410
411			`# print "$key \n";`
412			`my $VLNV;`
413			`my $vlnv;`
414
415
416			`( ${VLNV},${vlnv}) = split( /___root./ , $key);`
417			`if($VLNV eq "component")`
418			`{`
419			`if($vlnv)`
420			`{`
421			`push @children,$value;`
422
423			`}`
424			`}`
425	131	jt_eaton	`}`
426	134	jt_eaton	`}`
427	131	jt_eaton
428	134	jt_eaton	`@children = sys::lib::trim_sort(@children);`
429	131	jt_eaton
430	134	jt_eaton	`foreach my $child (@children)`
431			`{`
432			`my $ven;`
433			`my $lib;`
434			`my $cmp;`
435			`my $ver;`
436			`( ${ven},${lib},${cmp},${ver}) = split( /:/ , $child);`
437	131	jt_eaton
438	134	jt_eaton
439
440			`my $child_filename = yp::lib::find_componentConfiguration($ven,$lib,$cmp);`
441			`if($child_filename)`
442			`{`
443			`my $socgen_file = $parser->parse_file($child_filename);`
444			`foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))`
445			`{`
446			`my $version_name = $i_name ->findnodes('./text()')->to_literal ;`
447			`my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;`
448			`$cmd ="./tools/verilog/elab_verilog -vendor ${ven} -library ${lib} -component ${cmp} -version ${version_name} -configuration ${configuration}\n";`
449
450			`if (system($cmd)) {}`
451			`}`
452			`}`
453			`}`
454
455
456
457
458
459
460
461
462	133	jt_eaton	`@des_cmds = sys::lib::trim_sort(@des_cmds);`
463			`@gen_cmds = sys::lib::trim_sort(@gen_cmds);`
464	131	jt_eaton
465	133	jt_eaton
466	134	jt_eaton	`#print "Execute cmds \n";`
467	133	jt_eaton
468	134	jt_eaton	`my $manager = new Parallel::ForkManager( $number_of_cpus );`
469	133	jt_eaton
470
471
472
473			`#$manager->wait_all_children;`
474
475
476	134	jt_eaton
477
478
479
480
481	133	jt_eaton	`foreach $cmd (@des_cmds)`
482			`{`
483			`if (system($cmd)) {}`
484			`}`
485
486	134	jt_eaton	`print "End des_cmds \n";`
487	133	jt_eaton
488			`foreach $cmd (@gen_cmds)`
489			`{`
490			`# $manager->start and next;`
491	134	jt_eaton	`if (system($cmd)) {}`
492	133	jt_eaton	`# $manager->finish;`
493			`}`
494
495			`#$manager->wait_all_children;`
496
497	134	jt_eaton	`print "End All \n";`
498	133	jt_eaton
499
500

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