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[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Blame information for rev 119

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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;
#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010-2012>                */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/
 
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
use Cwd;
use XML::LibXML;
use lib './tools';
use sys::lib;
use yp::lib;
 
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h","help",
           "view=s" => \$view,
           "prefix=s" => \$prefix,
           "vendor=s" => \$vendor,
           "project=s" => \$project,
           "component=s" => \$component,
           "version=s" => \$version,
           "dest_dir=s" => \$dest_dir
) || die "(use '$program_name -h' for help)";
 
 
##############################################################################
## Help option
##############################################################################
if ( $opt_h  or ($opt_help) )
   {
   print "\n gen_verilogLib -view {sim|syn} -prefix /work  -vendor vendor_name -project  project_name  -component component_name -version version_name -dest_dir dest_dir";
   print "\n";
   exit 1;
   }
 
 
##############################################################################
##
##############################################################################
 
 
 
$home = cwd();
my $variant;
 
 if($version)       {$variant   = "${component}_${version}";}
 else               {$variant   = "${component}";}
 
my $lib_comp_sep    = yp::lib::find_lib_comp_sep($vendor,$project);
my $comp_xml_sep    = yp::lib::find_ipxact_component_path("spirit:component",$vendor,$project,$component,$version);
 
#############################################################################
##
##
#############################################################################
 
print "\n  Building $view  Verilog Lib RTL for  $prefix $project  $component $verison  $variant  $dest_dir  \n" ;
 
my $path  = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}";
mkdir $path,0755             unless( -e $path );
 
my $path  = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}";
mkdir $path,0755             unless( -e $path );
 
my $parser = XML::LibXML->new();
my $spirit_component_file    = $parser->parse_file(yp::lib::find_ipxact("spirit:component",$vendor,$project,$component,$version));
 
 
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:component/spirit:model/spirit:views/spirit:view/spirit:name[./text() = '$view']"))
    {
    my($view_fileset)  = $comp_view->findnodes('../spirit:fileSetRef/spirit:localName/text()')->to_literal ;
 
    #/**********************************************************************/
    #/*                                                                    */
    #/* build a `define file for module names                              */
    #/*                                                                    */
    #/*                                                                    */
    #/*                                                                    */
    #/*                                                                    */
    #/**********************************************************************/
 
    my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist";
    open DEFLIST,">$outfile" or die "unable to open $outfile";
    print  DEFLIST " \n";
    foreach  my   $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:logicalName"))
       {
       my($def_logic)     = $i_name ->findnodes('./text()')->to_literal ;
       my($def_type)      = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
       if($def_logic )    {print  DEFLIST   sprintf( "\`define %s   _%s\n",   uc($def_logic) ,  $def_logic    );}
       }
 
 
    #/**********************************************************************/
    #/*                                                                    */
    #/* build a fileset in the following order                             */
    #/*                                                                    */
    #/* deflist for module names                                           */
    #/* all include files                                                  */
    #/* verilogSource files                                                */
    #/*                                                                    */
    #/*                                                                    */
    #/**********************************************************************/
 
    my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist";
    open FILELIST,">$outfile" or die "unable to open $outfile";
 
    print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist\n";
 
    foreach  my   $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
       {
       my($file_name)      = $i_name ->findnodes('./text()')->to_literal ;
       my($file_type)      = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
       my($view_file)      = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
       if(($file_type eq "verilogInclude")&& (($view_file eq $view_fileset)))
         { print FILELIST  "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};
       }
 
    foreach  my   $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
       {
       my($file_name)      = $i_name ->findnodes('./text()')->to_literal ;
       my($file_type)      = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
       my($view_file)      = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
       if(($file_type eq "verilogSource")&& (($view_file eq $view_fileset)))
         { print FILELIST  "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};
       }
 
 
 
      #/**********************************************************************/
      #/*                                                                    */
      #/* Every leaf cell is processed through a the verilog preprocessor    */
      #/* to customize the module names,remove all verilog tic(`) statements */
      #/* and to create seperate versions for simulation and synthesys       */
      #/*                                                                    */
      #/*                                                                    */
      #/**********************************************************************/
 
 
        my $file_out  = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}/${variant}.v";
 
        if( -e $file_out )
        {
        $cmd ="rm  $file_out \n";
        if (system($cmd)) {}
        };
 
        $cmd ="vppreproc --noline --noblank  -DVARIANT=${variant}  -I${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/../verilog  -f  ${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist    >>  $file_out \n";
 
        if (system($cmd)) {}
 
 
 
 
 
 
 
  }
 
 
1
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Blame information for rev 119

Line No.	Rev	Author	Line
1	119	jt_eaton	eval 'exec `which perl` -S $0 ${1+"$@"}'
2			`if 0;`
3			`#/**********************************************************************/`
4			`#/* */`
5			`#/* ------- */`
6			`#/* / SOC \ */`
7			`#/* / GEN \ */`
8			`#/* / TOOL \ */`
9			`#/* ============== */`
10			`#/* \| \| */`
11			`#/* \|____________\| */`
12			`#/* */`
13			`#/* */`
14			`#/* */`
15			`#/* Author(s): */`
16			`#/* - John Eaton, jt_eaton@opencores.org */`
17			`#/* */`
18			`#/**********************************************************************/`
19			`#/* */`
20			`#/* Copyright (C) <2010-2012> */`
21			`#/* */`
22			`#/* This source file may be used and distributed without */`
23			`#/* restriction provided that this copyright statement is not */`
24			`#/* removed from the file and that any derivative work contains */`
25			`#/* the original copyright notice and the associated disclaimer. */`
26			`#/* */`
27			`#/* This source file is free software; you can redistribute it */`
28			`#/* and/or modify it under the terms of the GNU Lesser General */`
29			`#/* Public License as published by the Free Software Foundation; */`
30			`#/* either version 2.1 of the License, or (at your option) any */`
31			`#/* later version. */`
32			`#/* */`
33			`#/* This source is distributed in the hope that it will be */`
34			`#/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
35			`#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
36			`#/* PURPOSE. See the GNU Lesser General Public License for more */`
37			`#/* details. */`
38			`#/* */`
39			`#/* You should have received a copy of the GNU Lesser General */`
40			`#/* Public License along with this source; if not, download it */`
41			`#/* from http://www.opencores.org/lgpl.shtml */`
42			`#/* */`
43			`#/**********************************************************************/`
44
45
46
47			`############################################################################`
48			`# General PERL config`
49			`############################################################################`
50			`use Getopt::Long;`
51			`use English;`
52			`use File::Basename;`
53			`use Cwd;`
54			`use XML::LibXML;`
55			`use lib './tools';`
56			`use sys::lib;`
57			`use yp::lib;`
58
59
60			`$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.`
61
62
63			`############################################################################`
64			`### Process the options`
65			`############################################################################`
66
67			`Getopt::Long::config("require_order", "prefix=-");`
68			`GetOptions("h","help",`
69			`"view=s" => \$view,`
70			`"prefix=s" => \$prefix,`
71			`"vendor=s" => \$vendor,`
72			`"project=s" => \$project,`
73			`"component=s" => \$component,`
74			`"version=s" => \$version,`
75			`"dest_dir=s" => \$dest_dir`
76			`) \|\| die "(use '$program_name -h' for help)";`
77
78
79			`##############################################################################`
80			`## Help option`
81			`##############################################################################`
82			`if ( $opt_h or ($opt_help) )`
83			`{`
84			`print "\n gen_verilogLib -view {sim\|syn} -prefix /work -vendor vendor_name -project project_name -component component_name -version version_name -dest_dir dest_dir";`
85			`print "\n";`
86			`exit 1;`
87			`}`
88
89
90			`##############################################################################`
91			`##`
92			`##############################################################################`
93
94
95
96			`$home = cwd();`
97			`my $variant;`
98
99			`if($version) {$variant = "${component}_${version}";}`
100			`else {$variant = "${component}";}`
101
102			`my $lib_comp_sep = yp::lib::find_lib_comp_sep($vendor,$project);`
103			`my $comp_xml_sep = yp::lib::find_ipxact_component_path("spirit:component",$vendor,$project,$component,$version);`
104
105			`#############################################################################`
106			`##`
107			`##`
108			`#############################################################################`
109
110			`print "\n Building $view Verilog Lib RTL for $prefix $project $component $verison $variant $dest_dir \n" ;`
111
112			`my $path = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}";`
113			`mkdir $path,0755 unless( -e $path );`
114
115			`my $path = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}";`
116			`mkdir $path,0755 unless( -e $path );`
117
118			`my $parser = XML::LibXML->new();`
119			`my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact("spirit:component",$vendor,$project,$component,$version));`
120
121
122			`foreach my $comp_view ($spirit_component_file->findnodes("//spirit:component/spirit:model/spirit:views/spirit:view/spirit:name[./text() = '$view']"))`
123			`{`
124			`my($view_fileset) = $comp_view->findnodes('../spirit:fileSetRef/spirit:localName/text()')->to_literal ;`
125
126			`#/**********************************************************************/`
127			`#/* */`
128			#/* build a `define file for module names */
129			`#/* */`
130			`#/* */`
131			`#/* */`
132			`#/* */`
133			`#/**********************************************************************/`
134
135			`my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist";`
136			`open DEFLIST,">$outfile" or die "unable to open $outfile";`
137			`print DEFLIST " \n";`
138			`foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:logicalName"))`
139			`{`
140			`my($def_logic) = $i_name ->findnodes('./text()')->to_literal ;`
141			`my($def_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;`
142			if($def_logic ) {print DEFLIST sprintf( "\`define %s _%s\n", uc($def_logic) , $def_logic );}
143			`}`
144
145
146			`#/**********************************************************************/`
147			`#/* */`
148			`#/* build a fileset in the following order */`
149			`#/* */`
150			`#/* deflist for module names */`
151			`#/* all include files */`
152			`#/* verilogSource files */`
153			`#/* */`
154			`#/* */`
155			`#/**********************************************************************/`
156
157			`my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist";`
158			`open FILELIST,">$outfile" or die "unable to open $outfile";`
159
160			`print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist\n";`
161
162			`foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))`
163			`{`
164			`my($file_name) = $i_name ->findnodes('./text()')->to_literal ;`
165			`my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;`
166			`my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;`
167			`if(($file_type eq "verilogInclude")&& (($view_file eq $view_fileset)))`
168			`{ print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};`
169			`}`
170
171			`foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))`
172			`{`
173			`my($file_name) = $i_name ->findnodes('./text()')->to_literal ;`
174			`my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;`
175			`my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;`
176			`if(($file_type eq "verilogSource")&& (($view_file eq $view_fileset)))`
177			`{ print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};`
178			`}`
179
180
181
182			`#/**********************************************************************/`
183			`#/* */`
184			`#/* Every leaf cell is processed through a the verilog preprocessor */`
185			#/* to customize the module names,remove all verilog tic(`) statements */
186			`#/* and to create seperate versions for simulation and synthesys */`
187			`#/* */`
188			`#/* */`
189			`#/**********************************************************************/`
190
191
192			`my $file_out = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}/${variant}.v";`
193
194			`if( -e $file_out )`
195			`{`
196			`$cmd ="rm $file_out \n";`
197			`if (system($cmd)) {}`
198			`};`
199
200			`$cmd ="vppreproc --noline --noblank -DVARIANT=${variant} -I${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/../verilog -f ${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist >> $file_out \n";`
201
202			`if (system($cmd)) {}`
203
204
205
206
207
208
209
210			`}`
211
212
213			`1`
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