1 |
135 |
jt_eaton |
read_verilog /home/johne/socgen_xxx/children/opencores.org__Mos6502/ip/T6502/rtl/xml/../views/syn/T6502_ctrl.v
|
2 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__Mos6502/ip/T6502/rtl/xml/../views/syn/T6502_def.v
|
3 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__Mos6502/ip/core/rtl/xml/../views/syn/core_def.v
|
4 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__Mos6502/ip/cpu/rtl/xml/../views/syn/cpu_def.v
|
5 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/../views/syn/adv_dbg_if_jfifo.v
|
6 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/divider/rtl/xml/../views/syn/divider_def.v
|
7 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/jtag/rtl/xml/../views/syn/jtag_classic_sync.v
|
8 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/lifo/rtl/xml/../views/sim/lifo_def.v
|
9 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/pad/rtl/xml/../views/syn/pad_od_dig.v
|
10 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/pad/rtl/xml/../views/syn/pad_se_dig.v
|
11 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/serial/rtl/xml/../verilog/serial_xmit.v
|
12 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/serial/rtl/xml/../views/syn/serial_rcvr.v
|
13 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/sram/rtl/xml/../views/syn/sram_def.v
|
14 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/sram/rtl/xml/../views/syn/sram_dp.v
|
15 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/sram/rtl/xml/../views/syn/sram_word.v
|
16 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/sync/rtl/xml/../views/syn/sync_def.v
|
17 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__cde/ip/sync/rtl/xml/../views/syn/sync_with_hysteresis.v
|
18 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_ext_mem_interface/rtl/xml/../views/syn/io_ext_mem_interface_def.v
|
19 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_gpio/rtl/xml/../views/syn/io_gpio_def.v
|
20 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_module/rtl/xml/../views/syn/io_module_def.v
|
21 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_pic/rtl/xml/../views/syn/io_pic_def.v
|
22 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_ps2/rtl/xml/../views/syn/io_ps2_mouse.v
|
23 |
|
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read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_timer/rtl/xml/../views/syn/io_timer_def.v
|
24 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_uart/rtl/xml/../views/syn/io_uart_def.v
|
25 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_utimer/rtl/xml/../views/syn/io_utimer_def.v
|
26 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_vga/rtl/xml/../views/syn/io_vga_def.v
|
27 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__io/ip/io_vic/rtl/xml/../views/syn/io_vic_def.v
|
28 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/flash_memcontrl/rtl/xml/../views/syn/flash_memcontrl_def.v
|
29 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/micro_bus/rtl/xml/../views/syn/micro_bus_def.v
|
30 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/micro_bus/rtl/xml/../views/syn/micro_bus_exp9.v
|
31 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/ps2_interface/rtl/xml/../views/syn/ps2_interface_def.v
|
32 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/serial_rcvr/rtl/xml/../views/syn/serial_rcvr_def.v
|
33 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/uart/rtl/xml/../views/syn/uart_def.v
|
34 |
|
|
read_verilog /home/johne/socgen_xxx/children/opencores.org__logic/ip/vga_char_ctrl/rtl/xml/../views/syn/vga_char_ctrl_def.v
|
35 |
|
|
hierarchy -check -top T6502_def
|
36 |
|
|
proc; opt; fsm; opt; memory; opt
|
37 |
|
|
techmap;
|
38 |
|
|
opt
|
39 |
|
|
dfflibmap -liberty cells.lib
|
40 |
|
|
clean
|
41 |
|
|
write_verilog xxx.v
|
42 |
|
|
|